KR20170082356A - Image compression device and compression method for image compression device - Google Patents

Abstract

The image compression apparatus according to an embodiment of the present invention detects edge data through filtering of an image of a received frame and generates index signals corresponding to LCUs having different sizes, A delay buffer circuit for outputting a synchronous image signal in which an image of one frame and an index signal are synchronized and a synchronous image signal based on the synchronous image signal, And the index signals include information on the size of the maximum coding units (LCUs) corresponding to an image of one frame.

Description

Technical Field [0001] The present invention relates to an image compression apparatus and an image compression method using the same,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of encoding video or image signals, and more particularly, to an image compression apparatus for encoding image data and an image compression method using the same.

Various image processing methods have been used to display images on electronic devices. For example, Moving Picture Experts Groups (MPEG) develops a number of standards, including MPEG-1, MPEG-2 and MPEG-4. The video encoding standard encodes video data in a compression format to enhance the transmission efficiency of video data. When H.264 / AVC was standardized, there was no need to consider very high resolution images such as 4K UHD (Ultra High Definition: 3840 × 2160) or 8K UHD (7680 × 4320). In the actual specification of H.264 / AVC, the minimum resolution supported by H.264 / AVC supported by H.264 / AVC is 128 × 96, and the maximum resolution is 4096 × 2304. In other words, even if H.264 / AVC conforms to H.264 / AVC standard specification, it can compress 4K UHD image, but it does not mean that it can achieve optimal performance at the resolution.

An object of the present invention is to provide an image compression apparatus having an improved compression performance and an image compression method using the same.

Other image compression apparatuses according to embodiments of the present invention may include an index determination circuit, a delay buffer circuit, and an encoding circuit. The index determination circuit detects the edge data through filtering of the received image of one frame and determines an initial index signal among the index signals corresponding to the respective largest coding units (LCUs) having different sizes And index signals including information on the size of the maximum coding units (LCUs) corresponding to the image of the frame based on the edge data. The delay buffer circuit outputs a synchronous image signal which synchronizes the image of one frame and the index signals. The encoding circuit outputs a compressed bitstream based on the synchronous image signal.

According to an embodiment of the present invention, an image compression apparatus can divide an input image into a large coding unit (LCU) having an adaptive size. Accordingly, an image compression apparatus with improved compression performance and an image compression method using the same are provided.

1 is a block diagram illustrating an image compression apparatus according to an embodiment of the present invention.
2 is an internal block diagram of an index determination circuit according to an embodiment of the present invention.
3 is a diagram for explaining the operation of the edge detection circuit according to the embodiment of the present invention.
4 shows an edge image based on edge data.
Figure 5 shows a portion of a frame image divided into adaptive maximum coding units (LCUs) according to an embodiment of the present invention.
6 is a flowchart illustrating an image compressing method of an image compressing apparatus according to an embodiment of the present invention.
FIG. 7 shows a process of dividing the first through eleventh maximum coding units LCU1 through LCU11 in more detail.
8 is an internal block diagram of an encoding circuit of an image compression apparatus according to intra-picture prediction.
9 is a block diagram showing in detail an encoding circuit of an image compression apparatus according to inter-picture prediction.
10 is a block diagram showing an application example of the present invention applied to an electronic apparatus.

      The foregoing features and the following detailed description are exemplary of the invention in order to facilitate a description and understanding of the invention. That is, the present invention is not limited to these embodiments, but may be embodied in other forms. The following embodiments are merely examples for the purpose of fully disclosing the present invention and are intended to convey the present invention to those skilled in the art. Thus, where there are several ways to implement the components of the present invention, it is necessary to make it clear that the implementation of the present invention is possible by any of these methods or any of the equivalents thereof.

      It is to be understood that, in the context of this specification, when reference is made to a configuration including certain elements, or when it is mentioned that a process includes certain steps, other elements or other steps may be included. In other words, the terms used herein are for the purpose of describing specific embodiments only, and are not intended to limit the concept of the present invention. Further, the illustrative examples set forth to facilitate understanding of the invention include its complementary embodiments.

      The terms used herein have the meaning as commonly understood by one of ordinary skill in the art to which the present invention pertains. Commonly used terms should be construed in a manner consistent with the context of this specification. Also, terms used in the specification should not be construed as being excessively ideal or formal in nature unless the meaning is clearly defined. BRIEF DESCRIPTION OF THE DRAWINGS Fig.

1 is a block diagram illustrating an image compression apparatus according to an embodiment of the present invention.

Referring to FIG. 1, the image compression apparatus 100 may include an index determination circuit 110, a delay buffer circuit 120, and an encoding circuit 130.

The index determination circuit 110 receives the image O of one frame and detects edge data through filtering from the received image O of one frame and generates index signals I Can be output. The index signals I mean an initial index signal or a reduced index signal that is output each time a maximum coding unit (LCU) is assigned to edge data ED corresponding to an image O of one frame do. In other words, the index signals I contain information about the size of the largest coding units (LCUs) allocated to the edge data ED corresponding to the image O of one frame.

The index determination circuit 110 may sequentially receive a plurality of frame images transmitted from an external device (for example, image sensors) in units of an image (O) of one frame. For example, the index determination circuit 110 may output the index signals I by filtering data of pixels in the image O of one frame received.

While the image O of one frame is stored in the delay buffer circuit 120, the index determination circuit 110 may output the index signals I associated with the image O of one frame.

 The delay buffer circuit 120 may receive and store one frame of images O that are sequentially transmitted. The delay buffer circuit 120 may receive the image (O) of one frame in parallel with the index determination circuit 110. The delay buffer circuit 120 synchronizes the received image O of one frame and the index signals I corresponding to the image O of one frame and outputs the synchronized image signal OI .

There may be a delay between the image O of one frame input directly to the delay buffer circuit 120 and the index signals I output from the index determination circuit 110. [ For example, one frame of the image O may arrive in the delay buffer circuit 120 first, and the index signals I may arrive later. The delay buffer circuit 120 generates a synchronous image signal OI that synchronizes the image O of one frame with the index signals I considering the delay between the image O of one frame and the index signals I Can be output. For example, the delay buffer circuit 120 may output the synchronized image signal OI after both the image O of one frame and the index signals I are received.

The encoding circuit 130 generates a compressed bit stream (I) based on the synchronized image signal OI, i.e., the image O of one frame and the index signals I that determine the size of the maximum coding units , CBS). The encoding circuit 130 of the image compressing apparatus 100 will be described in detail in the following drawings.

According to the existing High Efficiency Video Coding (HEVC) specification, the size of the maximum coding unit (LCU) is determined to be one of 64 × 64, 32 × 32, and 16 × 16 sizes depending on the type of the input image. According to the existing HEVC specification, the video signals of the image O of one frame are uniformly divided into the largest coding units (LCUs) determined as one. Then, uniformly divided images are input into the encoding circuit with a maximum size coding unit (LCU) of a certain size.

On the other hand, according to the embodiment of the present invention, the video signals of the image O of one frame can be adaptively divided into 256X256 size, 128X128 size, 64X64 size, and 32X32 sizes based on the edge data ED. Illustratively, the image compressing apparatus 100 according to the embodiment of the present invention divides an image of one frame into a maximum coding unit (LCU) having a larger size than the maximum coding unit (LCU) according to the specification of the existing HEVC . Therefore, according to the embodiment of the present invention, when compression is performed on an ultrahigh-resolution image such as a 4K UHD (3840x2160) or an 8K UHD (7680x420), the compression efficiency of the image compression apparatus 100 is improved .

In other words, the image compressing apparatus 100 according to the present invention can allocate a maximum coding unit (LCU) having a size of 256X256 to a region where the edge data (ED) value is small, and set the compression rate of the corresponding region small . Also, in the image compression apparatus 100 according to the present invention, a maximum coding unit (LCU) having a size of 16 × 16 is allocated to an area having a large edge data (ED) value, and a compression ratio of the corresponding area is set large have. That is, according to an embodiment of the present invention, an image segmented into a variable-size maximum coding unit (LCU) may be encoded rather than an image divided into maximum-coding units (LCUs) of a certain size.

2 is an internal block diagram of the index determination circuit 110 according to the embodiment of the present invention.

Referring to FIGS. 1 and 2, the index determination circuit 110 may include a video input buffer circuit 111, an edge detection circuit 113, and an index circuit 115.

The video input buffer circuit 111 receives and stores an image O of one frame sequentially transmitted and sequentially outputs an image O of one frame to a single video signal SV.

The edge detection circuit 113 may receive the sequentially outputted single video signal SV and may detect the edge data ED through filtering. That is, the edge data ED may include the values of all pixels in one frame representing edge images. The operation of the edge detection circuit 113 will be described in detail with reference to the drawings described later.

The index circuit 115 adaptively determines the sizes of the maximum coding units (LCU) in an area corresponding to the image (O) of one frame, based on the detected edge data (ED) (I). For example, the indexing circuit 115 may compare the threshold value of the initial index signal with the average value of the pixels in the area of the maximum coding unit (LCU) corresponding to the initial index signal in the selected area of the edge data ED. If the comparison result is not suitable, the index circuit 115 may change the index signal and repeat the comparison. Once the maximum coding unit (LCU) and the index signal are determined, the indexing circuit 115 may determine the maximum coding unit (LCU) in another area of the edge data ED. The index circuit 115 determines the average value of the pixels in the size of the maximum coding unit LCU until the maximum coding unit LCU is allocated to all of the edge data ED corresponding to the image O of one frame, It is possible to repeatedly perform the operation of comparing the threshold value of the threshold value. The operation of the index circuit 115 will be described in more detail in the following figures.

3 is a diagram for explaining the operation of the edge detection circuit 113 according to the embodiment of the present invention. For the sake of brevity, we assume that one frame consists of 48 × 24 pixels and each of the 48 × 24 pixels has a digital value converted from the pixel value of the original image.

2 and 3, the edge detection circuit 113 performs filtering using any one of a Sobel filter, a Robert filter, and a Prewitt filter, (ED) can be detected. The edge data ED according to the embodiment of the present invention may include information indicating portions where data between pixel signals is abruptly changed. For the sake of brevity, it is assumed that the edge detection circuit 113 performs filtering using a Sobel filter.

The size of the Sobel filter may have a size of 3 × 3, 5 × 5, or 7 × 7. However, for the sake of brevity, it is assumed that the size of the Sobel filter has a size of 3 × 3.

Referring to FIG. 3, the edge detection circuit 113 performs a partial differentiation on the pixel values in the image O of one frame by moving the first Sobel filter BFx in the first direction. The edge detection circuit 113 can detect the slope Gx in the first direction in the image O of the frame based on the values of the partial derivatives. The determinant of the first direction Sobel filter (BFx) is shown in Table 1.

Referring to FIG. 3, the first direction Sobel filter BFx moves in the first direction with the first column C1 of the first row R1 as a starting point and the 48th column C48 of the 24th row R24 , It is possible to perform the convolution operation with the pixel values of the original image. The convolution operation for expressing the slope Gx in the first direction is expressed by the following equation (1).

In this case, N means a positive integer value when the size of the filter is (2N + 1) x (2N + 1). P denotes the position of the row of the filter, and q denotes the position of the column of the filter. m denotes the position of the row of the original image, and n denotes the position of the column of the pixel value of the original image.

In addition, the edge detection circuit 113 performs a partial differentiation on the pixel values in the image O of one frame by moving the second Sobel filter BFy in the second direction. The edge detection circuit 113 can detect the slope Gy in the second direction in the image O of the frame based on the values based on the partial derivatives. The determinant of the second direction Sobel filter (BFy) is shown in Table 2.

Referring to FIG. 3, the second direction Sobel filter BFy moves in the second direction with the first column C1 of the first row R1 as a starting point, and in the 48th column C48 of the 24th row R24 , It is possible to perform the convolution operation with the pixel values of the original image. The convolution operation for expressing the slope Gy in the second direction is expressed by the following equation (2).

N means a positive integer value when the size of the filter is (2N + 1) x (2N + 1). P denotes the position of the row of the filter, and q denotes the position of the column of the filter. m denotes the position of the row of the pixel value of the original image, and n denotes the position of the column of the pixel value of the original image.

In addition, the edge detection circuit 113 may perform the following operation (3) to obtain the final edge data ED.

Similarly, m denotes the position of the row of the pixel value of the original image, and n denotes the position of the column of the pixel value of the original image. Gx denotes a slope in the first direction as expressed by Equation (1), and Gy denotes a slope in the second direction as shown in Equation (2). Further, the edge detection circuit 113 can detect the edge data ED by performing the operation of Equation (3). For example, the edge data ED can be obtained by converting the data stored in the matrix of O (m, n) into bit stream form.

Figure 4 shows an edge image based on edge data (ED). An edge may refer to a portion where a change amount (slope) of a pixel value at a boundary of pixels of an original image is large. Referring to FIGS. 2 and 4, the index circuit 115 may adaptively divide the size of the maximum coding unit (LCU) based on the edge data ED.

Figure 5 shows a portion of a frame image divided into adaptive maximum coding units (LCUs) according to an embodiment of the present invention.

Referring to FIGS. 1 to 5, edge data ED corresponding to one frame image can be detected through filtering performed in the edge detection circuit 113. In the case of FIG. 5, it is assumed that the edge data ED corresponding to one frame image is data obtained by performing filtering in FIG. 3 and FIG. And the edge data ED corresponding to one frame is divided into the first to eleventh maximum coding units LCU1 to LCU11.

The index circuit 115 includes a first index signal I1 indicating that the size of the maximum coding unit LCU is a first size S1, a second index signal I2 indicating a second size S2, A third index signal I3 indicating that the first size is the third size S3 and a fourth index signal I4 indicating the fourth size S4.

For example, in the case of FIG. 5, the index circuit 115 outputs the fourth index signal I4 as the first maximum coding unit LCU1 having the fourth size S4 is allocated, And outputs the third index signal I3 as the second through fourth maximum coding units LCU2 through LCU4 having the first size S3 are allocated to the fifth through seventh maximum coding units LCU2 through LCU4, The second index signal I2 is output in accordance with the assignment of the first to sixth LCUs LCU5 to LCU7 and the eighth to eleventh maximum coding units LCU8 to LCU11 having the first size S1 are allocated, It is possible to output the signal I1.

6 is a flowchart illustrating an image compressing method of an image compressing apparatus according to an embodiment of the present invention.

1 to 6, in step S110, the image compression apparatus 100 sequentially receives images of a plurality of frames, and performs filtering using the filters of pixel signals constituting one frame image (O) can do. The image compression apparatus 100 may perform filtering to detect edge data ED corresponding to one frame image O. [ In addition, the filter used for filtering may be a Sobel filter, a prewitt filter, or a Robert filter. The process of performing the filtering and detecting the edge data ED has been described above with reference to FIG.

In step S120, the image compression apparatus 100 may determine an initial index signal among the first through fourth index signals I1 through I4. For example, the first index signal I1 may correspond to a first size S1 that is the smallest size. The second index signal I2 may correspond to a second size S2 that is larger than the first size S1. The third index signal I3 may correspond to a third size S3 that is larger than the second size S2. The fourth index signal I4 may correspond to a fourth size S4 that is larger than the third size S3.

Specifically, the first size S1 may comprise 32x32 pixel areas, the second size S2 may comprise 64x64 pixel areas, and the third size S3 may comprise And the fourth size S4 may include pixel regions of the size of 256x256.

      The image compression apparatus 100 may determine the initial index signal IF among the first to fourth index signals I1 to I4. For example, in step S120, the image compression apparatus 100 converts the fourth index signal I4 corresponding to the fourth largest size S4 of the first through fourth index signals I1 through I4 into an initial index Signal IF. That is, the maximum coding unit (LCU) of the fourth size S4 corresponding to the fourth index signal I4 may be selected.

In step S130, the image compression apparatus 100 calculates an edge ratio corresponding to a maximum coding unit (LCU) of the initial index signal IF based on the detected edge data ED as a threshold value of the initial index signal IF Can be compared. For example, the image compression apparatus 100 may calculate the edge index (IF) based on the detected edge data ED, that is, the fourth edge ratio corresponding to the maximum coding unit (LCU) of the fourth index signal I4 The threshold value of the first index signal ER4 and the threshold value of the initial index signal IF, i.e., the threshold value of the fourth index signal I4.

The edge ratio (ER ratio) of the maximum coding unit (LCU) is calculated by summing the sum of the edge data (ED) existing in the area covered by the size of the maximum coding unit (LCU) Means the size of the unit (LCU) divided by the number of pixels existing in the coverage area

For example, the first edge ratio ER1 is set such that the sum of the edge data ED existing in the first size S1 corresponding to the first index signal I1 exists in the area of the first size S1 Divided by the number of pixels. The second edge ratio ER2 is obtained by dividing the sum of the edge data ED existing in the second size S2 corresponding to the second index signal 12 by the number of pixels existing in the area of the second size S2 Value. The third edge ratio ER3 is obtained by dividing the sum of the edge data ED existing in the third size S3 corresponding to the third index signal 13 by the number of pixels existing in the area of the third size S3 Value. The fourth edge ratio ER4 is obtained by dividing the sum of the edge data ED existing in the fourth size S4 corresponding to the fourth index signal 14 by the number of pixels existing in the area of the fourth size S4 Value.

The threshold value of the index signal set in each of the index signals may be set differently depending on the type of the index signal. For example, the threshold value of the first index signal I1 may be set to the largest value among the threshold values of the first to fourth index signals I1 to I4. The threshold value of the second index signal I2 may be set to be smaller than the threshold value of the first index signal I1 and greater than the threshold value of the third index signal I3. The threshold value of the third index signal I3 may be smaller than the threshold value of the second index signal I2 and may be set to be larger than the threshold value of the fourth index signal I4. The threshold value of the fourth index signal I4 may be set to the smallest threshold among the threshold values of the first to fourth index signals I1 to I4.

In step S140, when the initial index signal IF, i.e., the fourth edge ratio ER4 corresponding to the fourth index signal I4 is less than the threshold value of the fourth index signal I4, 4 index signal I4. For example, the fourth index signal I4 assigns the first maximum coding unit LCU1 including the first edge data ED1 to the fourth size S4.

That is, the fourth edge ratio ER4 of the edge data ED covered by the maximum coding unit (LCU) having the fourth size S4 in the selected area of the image O of one frame is less than the threshold value of the index signal , The fourth index signal I4 for allocating the maximum coding unit (LCU) of the fourth size (S4) is outputted to the selected area.

Also, it may output a reduced index signal DI that can be output when performing steps S160 and S170 described later.

In step S150, the image compression apparatus 100 can determine whether or not the size of the maximum coding unit (LCU) is allocated to all of the edge data ED corresponding to one frame.

If the size of the maximum coding unit (LCU) is allocated to all edge data (ED) corresponding to one frame, the image compressing apparatus (100) ends the procedure. Conversely, when the size of the maximum coding unit (LCU) is not allocated, the size of the maximum coding unit (LCU) is allocated to the edge data (ED) area to which the size of the maximum coding unit The process may return to step S120 to perform the new procedure again.

That is, the image compressing apparatus 100 determines the size of each maximum coding unit (LCU) (LCU) until the maximum coding units (LCU) are allocated to the entire area of the edge data ED corresponding to the image Quot; For example, when the size allocation of the first coding unit (LCU1) of FIG. 5 is ended, there is remaining edge data to which the maximum coding unit (LCU) is not allocated. In the remaining edge data in which the maximum coding unit (LCU) is not allocated, allocation of a new maximum coding unit (LCU) may be attempted from the leftmost (or topmost) pixel of the topmost (or leftmost) pixels . For example, for allocation of a new maximum coding unit (LCU), step S120 may be performed again.

The image compression apparatus 100 can perform step S160 if the edge ratio corresponding to the maximum coding unit (LCU) of the initial index signal IF is equal to or exceeds the threshold of the initial index signal IF have. For example, if the initial index signal IF is the fourth index signal I4, and the fourth edge ratio ER4 is equal to or greater than the threshold value of the fourth index signal I4, step S160 is performed .

In step S160, the image compression apparatus 100 may redefine the initial index signal IF as a reduced index signal DI. For example, if the initial index signal IF is the fourth index signal I4, the reduced index signal DI is selected as the third index signal I3 in step S160. When the compared index signal is the third index signal I3 in step S130, the reduced index signal DI is selected as the second index signal I2 in step S160. If the compared index signal is the second index signal I2 in step S130, the reduced index signal D1 is selected as the first index signal I1 in step S160.

In step S170, the image compression apparatus 100 calculates the edge ratio corresponding to the maximum coding unit (LCU) of the reduced index signal DI based on the detected edge data ED and the threshold value of the reduced index signal DI You can compare the values. If the edge ratio corresponding to the reduced index signal DI is less than the threshold value of the reduced index signal DI, the image compression apparatus 100 may perform step S140 to output the reduced index signal DI .

Conversely, when the edge ratio corresponding to the maximum coding unit (LCU) of the reduced index signal DI is equal to or greater than a threshold value of the reduced index signal DI, the image compression apparatus 100 performs step S160 You can do it again.

In step S170, when the reduced index signal DI is the first index signal I1, the image compression apparatus 100 reduces the edge ratio corresponding to the maximum coding unit of the reduced index signal DI to the It is possible to directly output the first index signal I1 by performing step S140 without comparing the threshold value of the index signal DI.

FIG. 7 shows a process of dividing the first through eleventh maximum coding units LCU1 through LCU11 in more detail.

Referring to Figs. 1 to 7, the edge detection circuit 113 performs step S110 of Fig. 6 for one frame image O to detect the edge data ED. Following. The index circuit 115 performs step S120 with respect to the upper left corner of the first maximum coding unit LCU1. The index circuit 115 may set the initial index signal IF to the fourth index signal I4. Step S130 is then performed.

In step S130, the index circuit 115 determines that the first edge ratio ER1 corresponding to the maximum coding unit LCU1 of the fourth index signal I4 is smaller than the threshold value of the fourth index signal I4. Therefore, in step S140, the index circuit 115 may output the fourth index signal I4. The fourth index signal I4 allocates the first maximum coding unit LCU1 including the first edge data ED1 to the fourth size S4.

In step S150, since the index circuit 115 has an area not allocated to the maximum coding unit (LCU) among the edge data ED corresponding to one frame image O, the left side of the second maximum coding unit LCU2 Perform step S120 again based on the top.

Similarly, the edge detection circuit 113 may perform step S120 with respect to the upper left corner of the second maximum coding unit LCU2. The index circuit 115 sets the initial index signal IF to the fourth index signal I4. Step S130 is then performed. The index circuit 115 determines in step S130 that the fourth edge ratio ER4 corresponding to the maximum coding unit of the fourth index signal I4 exceeds the threshold value of the fourth index signal I4 or is equal to the threshold value do. Step S160 is then performed.

In step S160, the index circuit 115 reduces the fourth index signal I4 to the third index signal I3. In step S170, the index circuit 115 determines whether the edge ratio ER3 corresponding to the maximum coding unit of the third index signal I3, which is the reduced index signal DI, is smaller than the threshold value of the third index signal I3 . Therefore, the index circuit 115 can output the third index signal I3 in step S140. At this time, the third index signal I3 may allocate the second maximum coding unit LCU2 including the second edge data ED2 to the third size S3.

In step S150, since the index circuit 115 has an area not allocated to the maximum coding unit (LCU) among the edge data ED corresponding to one frame image O, the left side of the third maximum coding unit LCU3 Perform step S120 again based on the top.

The process of allocating the third size S3 to the third maximum coding unit LCU3 and the fourth maximum coding unit LCU4 for the sake of brevity may be performed by the second maximum coding unit LCU2 mentioned above in the third size S3 ) Is omitted.

The edge detection circuit 113 performs step S120 with reference to the upper left corner of the fifth maximum coding unit LCU5. Then, the index circuit 115 sets the initial index signal IF to the fourth index signal I4. Step S130 is then performed. In step S130, the index circuit 115 determines that the edge ratio ER4 corresponding to the maximum coding unit of the fourth index signal I4 exceeds or exceeds the threshold of the fourth index signal I4. Step S160 is then performed.

In step S160, the index circuit 115 reduces the fourth index signal I4 to the third index signal I3.

In step S170, the index circuit 115 determines whether the edge ratio ER3 corresponding to the maximum coding unit (LCU) of the third index signal I3, which is the reduced index signal DI, Value or equal to the threshold value. Step S160 is performed again.

The index circuit 115 reduces the third index signal I3 to the second index signal I2. In step S170, the index circuit 115 determines whether the edge ratio ER2 corresponding to the maximum coding unit of the second index signal I2, which is the reduced index signal DI, 2 index signal < RTI ID = 0.0 > I2. ≪ / RTI >

In step S140, the index circuit 115 may output the second index signal I2. At this time, the second index signal I2 may allocate the fifth maximum coding unit LCU5 including the fifth edge data ED5 to the second size S2.

In step S150, since the index circuit 115 has an area not allocated to the maximum coding unit (LCU) among the edge data ED corresponding to one frame image O, the left side of the sixth maximum coding unit LCU6 Perform step S120 again based on the top.

The process of allocating the second size S2 to the sixth maximum coding unit LCU6 and the seventh maximum coding unit LCU7 for the sake of brevity is the same as the process of allocating the second size S2 to the fifth maximum coding unit LCU5, ) Is omitted.

The edge detection circuit 113 performs step S120 with respect to the upper left corner of the eighth maximum coding unit LCU8. Then, the index circuit 115 sets the initial index signal IF to the fourth index signal I4. Step S130 is then performed. In step S130, the index circuit 115 determines that the edge ratio ER4 corresponding to the maximum coding unit of the fourth index signal I4 exceeds or exceeds the threshold of the fourth index signal I4. Step S160 is then performed.

In step S160, the index circuit 115 reduces the fourth index signal I4 to the third index signal I3.

In step S170, the index circuit 115 determines whether the edge ratio ER3 corresponding to the maximum coding unit of the third index signal I3, which is the reduced index signal DI, exceeds the threshold value of the third index signal I3 Or determines that it is equal to the threshold value. Therefore, step S160 is performed again.

In step S160, the index circuit 115 reduces the third index signal I3 to the second index signal I2.

In step S170, the index circuit 115 determines whether the edge ratio ER2 corresponding to the maximum coding unit of the second index signal I2, which is the reduced index signal DI, exceeds the threshold value of the second index signal I2 Or determines that it is equal to the threshold value. Therefore, step S160 is performed again.

In step S160, the index circuit 115 reduces the second index signal I2 to the first index signal I1. If the index circuit 115 is the first index signal I1, the process skips step S170 and enters the step S140 to output the first index signal I1. For example, the first index signal I1 may assign the eighth maximum coding unit (LCU8) including the eighth edge data (ED8) to the first size (S1).

In step S150, since the index circuit 115 has an area not allocated to the maximum coding unit (LCU) among the edge data ED corresponding to one frame image O, the left side of the ninth maximum coding unit LCU9 Step S120 is performed again with respect to the upper end.

The above process can be repeatedly performed until all the edge data ED corresponding to one frame image O are assigned to the maximum coding unit (LCU).

The process of assigning the first size S1 to the ninth maximum coding unit LCU9 to the eleventh maximum coding unit LCU11 for the sake of brevity is the same as the process of assigning the eighth maximum coding unit LCU8 to the first size S1 ) Is omitted.

It is to be understood that the order of allocating the size of the maximum coding unit (LCU) according to FIG. 7 is exemplary and not limited thereto. Also, in the course of performing step S130, when the edge rates of the first through eleventh maximum coding units LCU1 through LCU11 are compared with the threshold values of the index signals to allocate the size of the maximum coding unit (LCU) Although it is assumed that the upper left corner of each of the first through eleventh maximum coding units LCU1 through LCU11 is a reference pixel, the present invention is not limited to this, and it is understood that the sizes of the maximum coding units can be allocated using various reference pixels There will be.

Referring to Figures 1-7, it will be appreciated that an image within a frame can be divided into a maximum coding unit (LCU) having a variable size. Further, the compression ratio of the maximum coding unit (LCU) having the largest size among the variable maximum coding units (LCU) is made larger than the compression rate of the maximum coding unit (LCU) having the relatively small size. It will also be understood that the compression efficiency can be improved.

8 is an internal block diagram of the encoding circuit 130 of the video compression apparatus according to the intra prediction.

1 to 8, the encoding circuit 130 included in the image compression apparatus 100 includes a first adder 131, a conversion circuit 132, an entropy encoding circuit 133, an inverse conversion circuit 134, A second adder 135, a prediction module 136, an in-loop filter 137, and a frame memory 138. The input signal of the encoding circuit 130 of FIG. 8 corresponds to the synchronous image signal OI output from the delay buffer circuit 120.

The first adder 131 outputs a difference block R obtained by subtracting the intra-frame prediction value P output from the prediction module 136 from the synchronous image signal OI.

The converting circuit 132 receives the differential block R and converts it into a frequency-domain transform coefficient for the differential block. The correlation in the difference block can be removed. In this case, Discrete Cosine Transform (DCT), Discrete Sine Transform (DST), Integer Transform, or similar transforms may be used. Then, the conversion circuit 132 outputs the quantized data R 1 with respect to the transform coefficient in the frequency domain to further reduce the bit rate.

The entropy encoding circuit 133 receives the quantized data R1 and outputs a compressed bitstream (CBS) for storing or transmitting the quantized data R1.

The inverse transform circuit 134 receives the quantized data R1 in the frequency domain and performs an inverse quantization operation and an inverse transform operation for reconstructing the quantized data R1 into a pixel region to output a reconstructed differential block R2 . The reason for performing such a reverse conversion operation is to prevent a miss-match between the encoder circuit and the decoder circuit.

The second adder 135 outputs the restored block signal O1 obtained by adding the reconstructed difference block R2 and the intra prediction value P to the in-loop filter 137 and the intra prediction unit 136a in the prediction module 136 ). In this case, the restored block signal O2 is not the same signal as the synchronous image signal OI since it is a signal including an error generated in the quantization process.

The prediction module 136 may include an intra prediction unit 136a and an inter prediction unit 136b. The intra prediction unit 136a of the prediction module 136 of FIG. 8 generates a prediction block P from the pixel values around the data block to be coded and outputs the prediction block P to the first adder 131 and the second adder 135 can do.

The in-loop filter 137 outputs the compensation block signal O2 based on the reconstruction block signal O1. Specifically, the in-loop filter 137 removes the noise signal included in the received restored block signal O1 and compensates for the distortion between the original data signal and the restored block signal O1 to generate the compensated block signal O2 And output to an external output video device (not shown).

9 is a block diagram showing in detail an encoding circuit of an image compression apparatus according to inter-picture prediction. The inter-picture prediction unit 136b of the prediction module 136 shown in FIG. 9 generates a prediction block P from the previously coded data block of the data block to be coded at present and supplies it to the first adder 131 and the 2 adder 135 as shown in Fig. 9 will not be described in detail with respect to constituent elements having the same reference numerals as those shown in Fig.

10 is a block diagram showing an application example of the present invention applied to an electronic apparatus.

10, the electronic device 1000 includes a transceiver and a modem 1010, a CPU 1001, a DRAM 2001, a flash memory 1040, a display unit 1020, a user interface 1030, and an encoder 1050).

The CPU 1001 controls all operations of the electronic apparatus according to a preset program. The DRAM 2001 can function as a main memory of the CPU 1001. [ The DRAM 2001 may be a synchronous or asynchronous random access memory.

The transceiver and modem 1010 perform the modulation and demodulation function of the communication data. The display unit 1020 may have a touch screen as an element such as a liquid crystal having a backlight, a liquid crystal having an LED light source, or an OLED. The display unit 1020 functions as an output device for displaying images such as characters, numbers, pictures, and the like in color. The user interface 1030 may be an input device including a numeric key, a function key, and the like, and functions to interface between an electronic device and a person.

The flash memory 1040 may be a NOR type or a NAND type flash memory. The flash memory 1040 may store data information having various data types such as text, graphics, software code, and the like.

The encoder 1050 may refer to an image compression apparatus 100 according to an embodiment of the present invention. For example, the encoder 1050 may receive an image of a plurality of frames. The encoder 1050 can sequentially output the bitstream signals corresponding to the image of one frame among the images of the received plurality of frames.

The electronic device 1000 may function as a smart card or SSD by adding or subtracting components to or from the mobile communication device. The electronic device 1000 may be connected to an external communication device through a separate interface. The communication device may be a digital versatile disc (DVD) player, a computer, a set top box (STB), a game machine, a digital camcorder, and the like. It is apparent to those skilled in the art that a camera image processor (CIS) or the like may be further provided in the electronic device 1000 although not shown in the figure.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the equivalents of the claims of the present invention as well as the following claims.

100: image compressing apparatus 110: index judging circuit
111: Video input buffer circuit 112: Edge detection circuit
113: Index circuit 120: Delay buffer circuit
130: encoding circuit 131: first adder
132: conversion circuit 133: entropy coding circuit
134: Inverse conversion circuit 135: Second adder
136: prediction module 136a: intra prediction module
136b: inter-picture prediction unit 137: in-loop filter
138: Frame memory

Claims (14)

Detects edge data by filtering an image of a received frame, determines an initial index signal among index signals corresponding to each of a plurality of LCUs having different sizes, An index determination circuit for outputting the index signals based on the index signals;
A delay buffer circuit for outputting a synchronous image signal synchronized with an image of the frame and the index signals; And
And an encoding circuit outputting a compressed bitstream based on the synchronous image signal,
Wherein the index signals comprise information about a size of the maximum coding units (LCUs) corresponding to an image of the one frame. The method according to claim 1,
The index determination circuit determines,
A video input buffer circuit for receiving and storing images of a plurality of frames and sequentially outputting images of the plurality of frames;
An edge detection circuit receiving an image of each sequentially output frame and detecting the edge data through the filtering; And
The edge index corresponding to the maximum coding unit of the initial index signal is compared with the threshold value of the initial index signal based on the edge data and if the edge ratio is less than the threshold value of the initial index signal, And an index circuit for performing an image compression. 3. The method of claim 2,
Wherein the edge detection circuit performs the filtering using any one of a filter using a Sobel filter or a filter using a prewitt filter. The method of claim 3,
Wherein the edge detection circuit stores values obtained by convoluting values of the filter and the pixels corresponding to the pixels in the first direction and the second direction respectively with a first matrix and a second matrix, Wherein the filtering is performed by calculating and summing the magnitudes of the values stored in the second matrix and then storing the rooted values as a matrix corresponding to the image of the one frame. 3. The method of claim 2,
The index circuit decreasing the initial index signal when an edge ratio corresponding to a maximum coding unit of the initial index signal is equal to or exceeds a threshold value of the initial index signal, And compares the edge ratio corresponding to the maximum coding unit with the threshold value of the reduced index signal. 6. The method of claim 5,
The edge ratio is set such that the sum of the edge data of the area covered by the size of the maximum coding unit (LCU) of the initial index signal or the reduced index signal is smaller than the sum of the edge data of the initial index signal or the size of the maximum coding unit of the reduced index signal Which is a value divided by the number of pixels in the coverage area. The method according to claim 1,
Wherein the maximum coding units (LCUs) having different sizes have a size of 256X256, 128X128, 64X64, or 32X32 according to the index signals. 8. The method of claim 7,
Wherein the index determination circuit determines the size of the maximum coding unit (LCU) of the initial index signal to be the 256X256 size. Detecting edge data by filtering pixel signals constituting a received frame image;
Determining an initial index signal among index signals corresponding to maximum coding units (LCUs) having different sizes;
Outputting index signals indicating a size of the maximum coding units (LCUs) corresponding to the one frame based on the edge data;
Synchronizing the image of the frame with the index signals and outputting the synchronized image signal; And
And outputting a compressed bitstream based on the synchronous image signal. 10. The method of claim 9,
Wherein the step of detecting the edge data comprises:
And detecting portions of the pixel signals whose brightness changes rapidly. 10. The method of claim 9,
The step of outputting the index signals comprises:
The edge ratio corresponding to the maximum coding unit of the initial index signal is compared with the threshold value of the initial index signal based on the edge data and the edge ratio corresponding to the maximum coding unit of the initial index signal is compared with the index ratio And outputting the initial index signal if the index index is smaller than a threshold value. 10. The method of claim 9,
The step of outputting the index signals comprises:
If the edge ratio corresponding to the maximum coding unit of the initial index signal is equal to or exceeds the threshold value of the initial index signal, decreasing the initial index signal and corresponding to the maximum coding unit of the reduced index signal And outputting the reduced index signal if the edge ratio is less than a threshold value of the reduced index signal. 10. The method of claim 9,
Further comprising outputting the index signals based on the edge data until all pixel signals in the frame image are assigned maximum coding units (LCUs). 10. The method of claim 9,
Wherein the maximum coding unit (LCU) is further divided into a quad-tree form to form coding units (CUs).

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