KR20170080232A - Apparatus and Driving Method of Timing Controller and Display Device using the same - Google Patents

Abstract

The present invention generates and outputs a DE signal until the data voltage is supplied to the last horizontal line of the frame in which the no signal mode is started, that is, the time at which the data voltage is supplied in the frame in which the no signal mode is started, The present invention relates to a timing controller, a driving method thereof, and a display device using the timing controller, which can prevent an operation algorithm of a display device from being performed abnormally by driving using an internal DE after securing a period. A delay DE is generated using the last input DE in the no signal mode, and the delay DE is output for a period corresponding to a time at which a data voltage is to be supplied to all horizontal lines of the frame in which the no signal mode is started Next, a sufficient vertical blank interval is secured, and thereafter, Output internal data.

Description

[0001] The present invention relates to a timing controller, a driving method thereof, and a display device using the same,

The present invention relates to a timing controller and a driving method thereof. In particular, in a no-signal mode, a delay DE using an input DE input immediately before is generated and a supply of a delay DE is maintained until a vertical blank interval of one frame is reached, Mode, and a driving method thereof, and a display device using the timing controller.

An active matrix display device (hereinafter, referred to as 'display device') includes a display panel for displaying an image through a pixel matrix, a panel drive circuit for driving the display panel, And a timing controller for aligning image data input from outside with the gate and data driver and supplying the aligned image data to the gate and data driver to control the operation timing of the display panel.

The timing controller generates timing control signals for controlling the operation timings of the gate driver and the data driver based on the timing signals input with the input image data. In the timing controller, an operation mode such as a normal mode (Normal Mode) and a no signal mode (No Signal Mode) can be set.

In the normal mode, the timing controller generates various control signals in response to an input data enable signal (hereinafter referred to as 'input DE') provided from an external system.

The timing controller operates in the no-signal mode when there is no input data enable signal (hereinafter referred to as 'input DE') input from the outside or when it is inputted abnormally. In the no signal mode, the timing controller generates an internal data enable signal (hereinafter, referred to as 'internal DE') from the inside and supplies the pre-stored video data (hereinafter referred to as 'internal data' Thereby preventing noise on the display screen.

However, when the conventional timing controller operates in the no-signal mode, the frame immediately before the operation in the no-signal mode is forcibly terminated and image data is supplied only to some horizontal lines among the plurality of horizontal lines provided in the display panel And recognizes the point in time when the internal DE is input again as a new frame.

When the frame immediately before the operation in the non-signal mode is forcibly terminated as described above, the timing controller can not secure a sufficient vertical blank section in the frame, and accordingly, the panel data and the touch sensing or video A problem arises in driving the display device by abnormally performing an operation algorithm such as compensation of data.

SUMMARY OF THE INVENTION The present invention has been conceived in order to solve the above problems, and it is an object of the present invention to provide a method and apparatus for supplying a DE signal to a frame in which a data voltage is supplied to a last horizontal line of a frame in which a non- And then driving the display device by using the internal DE after ensuring a sufficient vertical blank interval to prevent the operation algorithm of the display device from being performed abnormally, a method of driving the same, and a display device using the same In order to solve the problem.

In order to solve the above problems, the timing controller according to the present invention generates a delay DE using the input DE last input in the no-signal mode, and supplies a data voltage to all horizontal lines of the frame in which the no-signal mode is started Outputting the delay DE for a period corresponding to the time to be performed, securing a sufficient vertical blank interval, and then outputting the internal data synchronized with the internal DE.

The timing controller according to the present invention generates a continuous delay DE (make_DE) for a period corresponding to the time for applying a data voltage to all the horizontal lines in the frame at the time of driving the non-signal mode, . Then, the vertical blank section is driven until the internal DE (internal_DE) and the internal data (internal_data) are outputted. Therefore, the timing controller according to the present invention secures a sufficient vertical blank period even in a frame driven in the non-signal mode, and the frame for starting the non-signal mode driving also normally ends.

FIG. 1 and FIG. 2 are diagrams for explaining the organic light emitting display device and the liquid crystal display device including the timing controller according to the present invention in more detail.
3 is a block diagram for explaining a timing controller according to the present invention.
4 is a waveform diagram showing the waveforms of DE and video data output when the present timing controller is driven in the non-signal mode.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description, a detailed description of known technologies or configurations related to the present invention will be omitted when it is determined that the gist of the present invention may be unnecessarily obscured. The component names used in the following description are selected in consideration of easiness of specification, and may be different from the parts names of actual products.

FIG. 1 and FIG. 2 are diagrams for explaining the organic light emitting display device and the liquid crystal display device including the timing controller according to the present invention in more detail.

The display device shown in Figs. 1 and 2 includes a display panel 1 defined in an area where a plurality of gate lines GL and data lines DL intersect and including a plurality of pixels arranged in a matrix form, A timing controller 4 for aligning video signals inputted from the outside and controlling the operation timing of the panel driving circuit so as to output the aligned video signal to the display panel 1, And a gate driver 3 and a data driver 2 for driving the gate line GL and the data line DL provided in the display panel 1 according to a signal from the display panel 1.

When the display panel 1 is an organic light emitting display, each pixel is provided with an organic light emitting diode (OLED) composed of an organic light emitting layer between the anode and the cathode, and a pixel circuit for independently driving the organic light emitting diode OLED .

The pixel circuit includes at least one switching transistor TR1, TR3, at least one capacitor Cst, and a driving transistor TR2. The plurality of switching transistors TR1 and TR3 charge a data signal to a capacitor Cst in response to a scan signal generated in units of horizontal periods. The driving transistor TR2 supplies the constant voltage V _DD to the organic light emitting element in accordance with the data voltage charged in the capacitor Cst to drive the organic light emitting element OLED.

When the display panel 1 is a liquid crystal display device, each pixel is provided with a thin film transistor (TFT) and a liquid crystal capacitor Clc connected to the thin film transistor. The liquid crystal capacitor Clc is composed of a pixel electrode connected to the thin film transistor, and a common electrode Vcom arranged between the pixel electrode and the liquid crystal. The thin film transistor supplies a video signal from each data line DL to the pixel electrode in response to a scan pulse from each gate line GL.

The liquid crystal capacitor Clc charges the difference voltage between the video signal supplied to the pixel electrode and the common voltage Vcom applied to the common electrode and adjusts the light transmittance by varying the arrangement of the liquid crystal molecules according to the difference voltage, .

3 is a block diagram for explaining the timing controller 4 according to the present invention.

3, the timing controller 4 according to the present invention includes a non-signal detecting unit 41, a delayed DE generating unit 42, a delay unit 43, an internal DE generating unit 44, An internal data generating unit 45, a first selecting unit 46 and a second selecting unit 47.

The non-signal detecting unit 41 receives the input DE input from the external system, analyzes the input DE, and when the input DE is absent or an abnormal signal is detected, the timing controller 4 is switched to the non-signal mode And outputs a no signal mode signal (abnormal_signal) for driving. At this time, the no signal mode abnormal signal is transmitted to the delay DE generating unit 41, the inner DE generating unit 42, the delay unit 43, and the first and second selecting units 46 and 47 .

The delayed DE generator 42 generates the first delay DE by delaying the input DE by n horizontal periods (n is a natural number equal to or greater than 1). Since the timing controller 4 receives image data from the outside and outputs the image data to the data driver 3 through various image processing, the timing controller 4 outputs the image data in a delayed manner compared to the input DE even if it is output in synchronization with the input DE. Accordingly, the delay DE generator 42 generates the first delay DE using the input DE, and outputs the video data to the data driver 3 in synchronization with the first delay DE.

However, when there is no input of the input DE or an abnormal signal is inputted, the delayed DE generator 42 also causes a problem in the drive for generating the first delay DE delaying the input DE.

In the non-signal mode, the delay DE generating unit 42 according to the present invention, in response to the non-signal mode signal (abnormal_signal) input from the non-signal detecting unit 41, In the frame in which the signal is input, the period during which the data voltage for the last horizontal line of the display panel 1 is to be output, that is, the no-signal mode is not input, is repeated until the output of all the image data of the frame is normally completed And generates and outputs a second delay DE. To this end, the delay DE generator 42 may include a latch unit (not shown) and a clock counter (not shown).

The latch unit latches the last input DE of the input DE input from the outside. Then, when the no signal mode signal is supplied, a second delay DE is generated using the latched input DE based on the polling edge of the last input DE.

In this case, the latch unit latches the voltage level when the input DE (input_DE) is risered, and then the latch unit changes the second delay DE . The delay DE generator 42 also counts an internal clock generated from an external clock supplied from an external system or an external clock supplied from the timing controller 4 to a predetermined k value by using a clock counter, an output interval of the second delay DE having a width corresponding to k internal clocks or the number of external clock inputs can be generated. The delay DE generator 42 can also determine the width of the non-output period of the second delay DE by using an external clock or an internal clock so that the second delay DE is the same waveform having the same period as the first delay DE .

The delay DE generating unit 42 generates a second delay DE during a period in which the data voltage of the last horizontal line of the display panel 1 is to be output in the frame in which the no signal mode signal is input, So that the frame in which the non-signal mode signal is input is stably terminated.

The delay unit 43 delays the output of the video data input_data synchronized with the input DE (input_DE), receives the first delay DE and synchronizes the video data input_data with the first delay DE 2 selection unit 47. [0050] To this end, the delay unit 43 may include a data memory. On the other hand, when the input DE (input_DE) is not input or an abnormal signal is inputted and the timing controller 4 is driven in the non-signal mode, the delay unit 43 stops outputting the video data (input_data).

The internal DE generating unit 44 generates an internal DE (internal_DE) in response to a no signal mode signal (abnormal_signal) input from the no signal detecting unit 41 and outputs the internal DE to the first selecting unit and the internal data generating unit 45 .

The internal data generation unit 45 stores internal data (internal_data) to be output to the display panel 1 in the no-signal mode. The internal data (internal_data) may be set to a minimum data such as a predetermined message, a logo, and time data. The internal data generation unit 45 receives the internal DE (internal_DE) and outputs the internal data to the second selection unit 47 in synchronization with the internal DE (internal_DE).

In the normal mode, the first selector 46 outputs the delay DE as an output DE (output_DE), and the second selector 47 outputs the delay DE as an output DE (output_DE) so that the image data input_data is synchronized with the output DE Output.

In the non-signal mode, the non-signal mode signal (Abnormal_mode) is input to the first selector (46) and the second selector (47).

In response to the non-signal mode signal (abnormal_mode), the first selector 46 outputs the data voltage of the last horizontal line of the display panel 1 in the frame in which the no signal mode signal (abnormal_mode) is input (Internal_DE) is outputted as the output DE (ontput_DE) when the internal DE (internal_DE) is inputted after the vertical blank interval after the second delay DE is output to the output DE (output_DE) 3).

In the non-signal mode, the supply of the video data input_data input from the delay unit 43 is stopped to the second selection unit 47. That is, after the non-signal mode signal (abnormal_signal) is input to the second selector 47, the second selector 47 stops outputting the video data (input_data) during the period in which the second delay DE is input . If the internal data internal_data is input to the second selector 47 after the vertical blank interval, the second selector 47 outputs the internal data internal_data as the output data output_data. Accordingly, the internal data (internal_data) is output to the data driver 3 in synchronization with the internal DE (internal_DE).

Here, the first and second selecting units may be provided with a multiplexer (MUX).

The non-signal detecting unit 41 may include a counter (not shown) for counting the number of times of input of the external DE. In the no-signal mode, the no-signal detector 41 counts the number of times the input DE is normally input using the counter.

When the input DE (input_DE) is normally input more than 1 times (l is a natural number equal to or greater than 1) during driving in the non-signal mode, the no signal detecting unit 41 stops outputting the no signal mode signal (abnormal_mode) (4) is driven in the normal mode. Where the value of l can vary from as low as 1-5 to as much as 10-100 depending on the design.

The timing controller 4 according to the present invention is capable of continuously delaying a period of time corresponding to the time for applying a data voltage to all the horizontal lines of the display panel 1 in the frame at the time of driving the non- DE (make_DE) and outputs it to the data driver 3. Then, the vertical blank section is driven until the internal DE (internal_DE) and the internal data (internal_data) are outputted. Therefore, the timing controller 4 according to the present invention secures a sufficient vertical blank interval even in a frame driven in the non-signal mode, and the frame for starting the non-signal mode driving also normally ends.

Therefore, the timing controller according to the present invention can secure a sufficient vertical blank interval in the frame, and accordingly, the display apparatus abnormally operates the operation algorithm such as the panel data and the touch sensing or compensation of the image data performed in the vertical blank interval You can solve the problem you are performing.

Hereinafter, a driving method of the timing controller according to the present invention will be described.

In the normal mode, the timing controller 4 according to the present invention receives the input DE (input_DE), the delay DE generator 42 generates a first delay DE delaying the input DE (input_DE) by n horizontal periods , And outputs the first delay DE 42 to the delay unit 43 and the first selector 46.

The delay unit 43 receives the first delay DE (make_DE) and the image data input_data, and outputs the image data to the second selector 47 in synchronization with the first delay DE (make_DE).

The first selector 46 outputs the first delay DE (make_DE) as an output DE (output_DE) to the data driver 3 and the second selector 47 outputs the image data (input_data) (output_data) to the data driver 3 in synchronization with the first delay DE (make_DE).

4 is a waveform diagram showing the waveforms of DE and video data outputted when the present timing controller 4 is driven in the non-signal mode.

When the input DE (input_DE) is being input, or when the input DE (input_DE) is not inputted or an abnormal signal is input, the timing controller 4 is driven in the non-signal mode.

For the non-signal mode driving, the non-signal detecting unit 41 outputs a no signal mode signal (abnormal_signal). At this time, the no signal mode abnormal signal is transmitted to the delay DE generating unit 42, the inner DE generating unit 42, the delay unit 43, and the first and second selecting units 46 and 47 .

The delayed DE generator 42 generates a delayed DE signal in response to the non-signal mode signal (abnormal_signal) until the data voltage of the last horizontal line of the display panel 1 is output in the frame in which the non- Generates a second delay DE (make_DE_2) on the basis of the input DE (input_DE), and outputs the second delay DE (make_DE_2) to the delay unit 43 and the first selector 46.

The delay unit 43 stops the output of the video data when the non-signal mode signal (abnormal_signal) is input.

The internal DE generation unit 42 generates an internal DE (internal_DE) in response to the no signal mode signal (abnormal_signal) and outputs the internal DE (internal_DE) to the first selection unit 46 and the internal data generation unit 45 do.

The internal data generation unit 45 generates internal data to be output to the display panel 1 in the no signal mode and outputs the generated internal data to the second selection unit 47. At this time, the internal data may be the data stored in advance.

The first selector 46 selects the second delay (delayed) until the data voltage of the last horizontal line of the display panel 1 is output in the frame in response to the no signal mode signal (abnormal_signal) DE, and then outputs the internal DE (internal_DE) to the data driver 3 as the output DE (output_DE) when the internal DE (internal_DE) is input after having the predetermined vertical blank interval.

At this time, the second selector 47 outputs the internal data in synchronization with the internal DE (internal_DE).

Here, the delayed DE generator 42 latches the last input DE (input_DE) of the input DE (input_DE) input from the outside and then inputs the latched input DE based on the polling edge of the last input DE And generates a second delay DE (make_DE_2) as a reference. At this time, the maximum voltage level of the second delay DE (make_DE_2) is equal to the maximum voltage level of the latched input DE. The delay DE generator 42 may determine an output interval and a period of the second delay DE by counting the internal clock generated by the timing controller 4 using an external clock input from the outside or the external clock.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Will be apparent to those of ordinary skill in the art.

1: display panel 2: gate driver
3: Data driver 4: Timing controller
41: No signal detection unit 42: Delay DE generation unit
43: Delay unit 44: Internal DE generation unit
45: internal data generation unit 46: first data selection unit
47: second selection unit

Claims (8)

A timing controller driven in a normal mode and a non-signal mode, arranged to output image data input from the outside in the normal mode, and controlling a display timing of the image data,
A non-signal detector for outputting a non-signal mode signal for driving in a non-signal mode when the external DE is inputted or an abnormal signal is detected by analyzing an external DE inputted from the outside,
Generating a first delay DE delaying the external DE and generating a second delay DE having the same pulse width as the external DE on the basis of the polling edge of the external DE in response to the no signal mode signal, A delay DE generator for repeatedly outputting the second delay DE until the output of all the image data of the frame in which the signal is detected is completed,
And an internal DE generator for generating and outputting an internal DE during driving in the no signal mode after having the predetermined second blank interval after the output of the second delay DE. The method according to claim 1,
A delay unit receiving the image data and outputting the image data in synchronization with the first delayed DE signal,
An internal data generating unit receiving the internal DE while driving in the no signal mode and outputting internal data of a specific pattern synchronized with the internal DE,
Wherein the first delay or the second delay DE and the internal DE are received and until the output of all the image data of the frame in which the abnormal signal is detected is completed in response to the non- A first selector for outputting the DE and outputting the internal DE from a time after the vertical blank interval to a time point at which the external DE is normally input,
Further comprising a second selecting unit for outputting the internal data from the vertical blanking interval to the driving time in the normal mode in response to the non-signal mode, stopping the output of the image data from the vertical blanking interval to the normal blanking interval, controller. 3. The method of claim 2,
Wherein the delayed DE generator comprises:
A latch for latching a voltage level when the external DE is risered and outputting the second internal DE so that the maximum voltage level of the second internal DE in the no signal mode becomes the latched voltage level;
Counting an external clock input from the outside or an internal clock generated by using the external clock to a predetermined value m (m is an input number of clock pulses for one horizontal period) 2 A timing controller that includes a clock counter to set the active interval of the internal DE. The method according to claim 1,
Wherein the non-signal detecting unit includes a counter for counting the number of times of inputting the input DE, and when the input DE is normally inputted more than 1 time (l is a natural number equal to or greater than 1) And stops the output of the signal mode signal, thereby driving the timing controller again in the normal mode. Outputting a no signal mode signal for driving in a non-signal mode when the external DE is not input or an abnormal signal is detected by analyzing an external DE input from the outside,
In response to the no signal mode signal, a second delay DE having a pulse width equal to that of the external DE is generated based on the polling edge of the external DE, and the output of all the image data of the frame in which the abnormal signal is detected is completed Repeatedly outputting the second delay DE until a time point when the first delay DE is reached,
Generating an internal DE and internal data by receiving the non-signal mode signal,
Having a predetermined vertical blank interval after the output of the second delay DE,
And outputting the internal DE and internal data after the vertical blank interval. 6. The method of claim 5,
The step of outputting the second delay (DE)
Wherein the latch circuit latches the voltage level when the external DE is risered and then determines that the maximum voltage level of the second internal DE in the no signal mode has the same voltage level as the latched voltage level, Counts an internal clock generated internally to a value of a predetermined m (m is an input number of clock pulses for one horizontal period) to set an active period of the second internal DE by using the clock pulse, . The method according to claim 6,
Wherein when the input DE is normally input more than one time during the non-signal mode driving, the abnormality detector stops outputting the non-signal mode signal, and then drives again in the normal mode. A display panel including a plurality of subpixels positioned in a matrix form in a region where a plurality of gate lines and data lines cross each other,
A gate driver for driving the gate line,
A data driver for driving the data lines,
And a timing controller according to any one of the first to fourth aspects for driving the gate driver and the data driver to control display timing of image data inputted from the outside.

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