KR20170080231A - Array Substrate, Fabricating Method Thereof, And Liquid Crystal Display Device Including The Same - Google Patents

Abstract

A liquid crystal display device of the present invention includes a gate wiring and a common wiring line spaced on a substrate, a data line crossing the gate line and defining a pixel region, a thin film transistor connected to the gate wiring and the data wiring, A color filter layer located in a pixel region above the protective layer, a light shielding layer located above the protective layer in correspondence with the common wiring, an overcoat layer located above the color filter layer and the light shielding layer, And the overcoat layer has a first protrusion corresponding to the common wiring, and the first protrusion has an annular planar structure including a hole therein. The first projection may contact the column spacer for holding the cell gap of the counter substrate.

Description

[0001] The present invention relates to an array substrate, a method of manufacturing the same, and a liquid crystal display device including the array substrate.

The present invention relates to an array substrate for a liquid crystal display, and more particularly to an array substrate including a color filter, a manufacturing method thereof, and a liquid crystal display including the same.

BACKGROUND ART [0002] As an information society has developed, there have been various demands for a display device for displaying an image, and a liquid crystal display (LCD) device and an organic light emitting diode (OLED) Flat panel display devices (FPDs) have been developed and applied to various fields.

Among these flat panel display devices, liquid crystal display devices are widely used because they have advantages of miniaturization, weight reduction, thinning, low power driving, and the like.

The liquid crystal display device utilizes optical anisotropy and permittivity anisotropy of a liquid crystal and includes two substrates, a liquid crystal layer between two substrates, and a pixel electrode and a common electrode for driving liquid crystal molecules in the liquid crystal layer. Therefore, the liquid crystal display device adjusts the arrangement of liquid crystal molecules by an electric field generated by applying a voltage to the pixel electrode and the common electrode, and displays the image by the transmittance of light depending on the arrangement. Such a liquid crystal display device is applied to a variety of applications ranging from a portable device such as a mobile phone or a multimedia device to a monitor of a notebook computer or a computer, and a large television.

In general, a thin film transistor for applying a signal to pixel electrodes of each pixel region is formed on a lower substrate of a liquid crystal display device, and a color filter is formed on an upper substrate corresponding to each pixel region. The lower substrate including the thin film transistor is referred to as an array substrate, and the upper substrate including the color filter is referred to as a color filter substrate.

Such a liquid crystal display device is formed through a process of forming two substrates and arranging the pixel electrodes of the array substrate and the color filters of the color filter substrate in a one-to-one correspondence relationship. In the process of arranging the two substrates, misalignment occurs, Can occur. In order to prevent this, it is possible to form a wide black matrix on the color filter substrate in consideration of the cohesion margin between the array substrate and the color filter substrate. However, in this case, the aperture ratio of the liquid crystal display device is lowered, and accordingly, the image quality is affected.

In particular, as the liquid crystal display device has a high resolution, the size of the pixel area is reduced within the same area, so that the image quality of the image is greatly affected even with a small difference in aperture ratio.

On the other hand, a spacer is provided between the array substrate and the color filter substrate to maintain a constant gap between the two substrates. Recently, a column spacer which can be formed in a desired shape at a specific position is widely used, and a column spacer is formed mainly on a color filter substrate having a relatively small number of processes.

A conventional liquid crystal display device including such a column spacer will be described with reference to Fig.

1 is a cross-sectional view schematically showing a conventional liquid crystal display device.

The lower substrate 10 and the upper substrate 20 are spaced apart from each other and the liquid crystal layer 30 is positioned between the lower substrate 10 and the upper substrate 20 as shown in FIG. On the inner surface of the upper substrate 20, a column spacer 40 is formed. The column spacer 40 contacts the uppermost layer 12 of the lower substrate 10 to maintain a gap between the lower substrate 10 and the upper substrate 20. [

These column spacers 40 are arranged at regular intervals. Accordingly, in the region where the column spacer 40 is not present, deflection of the upper substrate 20 may occur. In order to prevent this, the number of the column spacers 40 within the same area can be increased to increase the arrangement density of the column spacer 40. [ However, in this case, the contact area between the uppermost layer 12 of the lower substrate 10 and the column spacer 40 increases, and thus a touch failure may occur. That is, the contact area is increased and the contact density is increased. As a result, the flow of the upper substrate 20 is not free and the liquid crystal molecules are moved due to the touch of the upper substrate 20, . Especially, unevenness occurs in the black state, and the contrast ratio can be lowered.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems and aims to improve the aperture ratio of a liquid crystal display device.

Further, the present invention is intended to solve deflection and touch failure of a substrate in a liquid crystal display device.

In order to achieve the above object, a liquid crystal display device of the present invention includes: a gate wiring and a common wiring which are spaced on a substrate; a data wiring crossing the gate wiring and defining a pixel region; A protection layer covering the thin film transistor; a color filter layer located in the pixel region above the protection layer; a light shielding layer located above the protection layer in correspondence to the common wiring; And an overcoat layer positioned above the light-shielding layer, and pixel electrodes and a common electrode positioned in the pixel region above the overcoat layer, wherein the overcoat layer has a first protrusion corresponding to the common wiring, 1 projections have an annular planar structure including holes therein.

The hole of the first projection may be a contact hole located on the common wiring. At this time, the contact hole can expose the common wiring.

This first projection may contact the column spacer for holding the cell gap of the counter substrate.

The overcoat layer may have the first protrusion corresponding to the first pixel area and the second protrusion corresponding to the second pixel area and having a width and a thickness smaller than the first protrusion.

The first and second projections of the overcoat layer may be formed using an exposure mask including a blocking portion, a transmissive portion, and a semi-transmissive portion.

In the present invention, the color filter can be formed on the array substrate to increase the aperture ratio of the liquid crystal display device.

In addition, the stepped structure on the array substrate can increase the number of column spacers for maintaining the cell gap, preventing sagging of the substrate, and reducing the contact area of the column spacer, thereby preventing touch failure.

At this time, by arranging the column spacer above the contact hole, there is no restriction on the arrangement of the column spacer, and the aperture ratio can be further increased.

On the other hand, this step structure can be formed on the array substrate without adding a process.

1 is a cross-sectional view schematically showing a conventional liquid crystal display device.
2 is a cross-sectional view schematically showing a liquid crystal display device according to an embodiment of the present invention.
3 is a schematic plan view of an array substrate for a liquid crystal display according to an embodiment of the present invention.
4 is a schematic cross-sectional view of an array substrate for a liquid crystal display according to an embodiment of the present invention.
5 is a plan view schematically showing a liquid crystal display according to an embodiment of the present invention.
6 is a cross-sectional view schematically showing a liquid crystal display device according to an embodiment of the present invention, and shows cross sections corresponding to lines VIA-VI, VIB-VIB, and VIC-VIC in FIG.
7 is a three-dimensional micrograph image of the second projection according to the embodiment of the present invention viewed from above.
FIGS. 8A to 8F are cross-sectional views schematically showing an array substrate in each step of a manufacturing process of an array substrate for a liquid crystal display according to an embodiment of the present invention, in which VIA-VI line, VIB- Sectional view corresponding to the VIC line.
9 is a cross-sectional view schematically showing a liquid crystal display device according to another embodiment of the present invention.

The array substrate of the present invention includes a substrate, a gate wiring and a common wiring spaced on the substrate, a data wiring crossing the gate wiring and defining a pixel region, a thin film transistor connected to the gate wiring and the data wiring, A protective layer covering the thin film transistor; a color filter layer located in the pixel region above the protective layer; a light shielding layer located above the protective layer in correspondence with the common wiring; Wherein the overcoat layer has a first protrusion corresponding to the common wiring, and the first protrusion is formed in the overcoat layer, and the overcoat layer is formed on the overcoat layer, Holes.

The overcoat layer has a contact hole on the common wiring, and the contact hole is also formed in the first projection.

The contact hole exposes the common wiring.

The array substrate of the present invention further includes a common electrode contact portion connected to the common electrode on the overcoat layer, and the common electrode contact portion contacts the common wiring through the contact hole.

The first protrusion has a circular or polygonal annular planar structure.

The first projections include a plurality of grooves arranged at regular intervals.

The light-shielding layer includes a first color pattern and a second color pattern on the first color pattern.

Wherein the overcoat layer has the first protrusion corresponding to the first pixel area and has a second protrusion corresponding to the second pixel area, the width and the thickness of the first protrusion being greater than the width and thickness of the second protrusion .

The overcoat layer has a third protrusion corresponding to the third pixel region, and the width and thickness of the third protrusion are larger than the width and thickness of the first protrusion.

A liquid crystal display device according to the present invention includes an array substrate, an opposing substrate spaced apart from the array substrate, and a liquid crystal layer between the array substrate and the opposing substrate, wherein the opposing substrate has the third projections or the third projections Lt; / RTI >

Alternatively, the liquid crystal display of the present invention may include: an array substrate; an opposing substrate spaced apart from the array substrate; a liquid crystal layer between the array substrate and the opposing substrate; and a liquid crystal layer disposed between the array substrate and the opposing substrate, And a second column spacer, wherein the first column spacer is in contact with the film on the first projection or the first projection.

According to another aspect of the present invention, there is provided a method of manufacturing an array substrate, including: forming a gate wiring and a common wiring on a substrate; forming a data wiring crossing the gate wiring and defining a pixel region; And forming a thin film transistor connected to the data line; forming a protective layer covering the thin film transistor; forming a color filter layer in the pixel region above the protective layer; Forming an overcoat layer on the color filter layer and the light shielding layer; and forming a pixel electrode and a common electrode in the pixel region above the overcoat layer And the step of forming the overcoat layer includes the steps of: forming a first protrusion And a step of sex.

The step of forming the overcoat layer includes the steps of forming a photosensitive organic film, disposing an exposure mask including a blocking portion, a transmissive portion and a transflective portion on the photosensitive organic film, and exposing the photosensitive organic film And developing and curing the exposed photosensitive organic film, wherein the first protrusion corresponds to the transmissive portion.

Forming the overcoat layer includes forming the first protrusion corresponding to the first pixel region and forming a second protrusion corresponding to the second pixel region, wherein the width of the first protrusion And the thickness is greater than the width and thickness of the second projection.

The width of the transmissive portion of the exposure mask corresponding to the first projecting portion is larger than the width of the transmissive portion of the exposure mask corresponding to the second projecting portion.

The step of forming the overcoat layer may further include forming a third protrusion corresponding to the third pixel region, wherein the width and thickness of the third protrusion are larger than the width and thickness of the first protrusion.

The width of the transmissive portion of the exposure mask corresponding to the third projecting portion is larger than the width of the transmissive portion of the exposure mask corresponding to the first projecting portion.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

2 is a cross-sectional view schematically showing a liquid crystal display device according to an embodiment of the present invention.

The first substrate 102 and the second substrate 104 are spaced apart from each other and the liquid crystal layer 106 is positioned between the first substrate 102 and the second substrate 104 . A column spacer 108 is formed under the second substrate 104 and the column spacer 108 contacts the step structure 103 of the first substrate 102 to form the first substrate 102 and the second substrate 104).

At this time, the step structure 103 on the first substrate 102 has a hole therein and contacts a part of the column spacer 108. Therefore, in the present invention, the contact area between the stepped structure 103 on the first substrate 102 and the column spacer 108 is smaller than that in the prior art. Accordingly, even if the arrangement density of the column spacer 108 is increased, the contact density, that is, the contact area of the column spacer 108 can be smaller than or equal to the conventional one, It is possible to prevent a bad touch.

On the other hand, in the present invention, misalignment can be prevented and the aperture ratio of the liquid crystal display device can be increased by forming color filters on the array substrate. At this time, a color filter may be formed on the top of the thin film transistor, and this structure is referred to as a color filter on thin film transistor (COT) structure. An array substrate for a liquid crystal display according to an embodiment of the present invention will be described with reference to Figs. 3 and 4. Fig.

FIG. 3 is a schematic plan view of an array substrate for a liquid crystal display according to an embodiment of the present invention, and FIG. 4 is a schematic cross-sectional view of an array substrate for a liquid crystal display according to an embodiment of the present invention, . Here, FIG. 4 shows a cross section corresponding to line IV-IV in FIG.

As shown in FIGS. 3 and 4, a gate wiring 112, a gate electrode 114, and a common wiring 116 made of a conductive material are formed on a transparent insulating substrate 110.

The gate wiring 112 extends along the first direction, and the gate electrode 114 is connected to the gate wiring 112. The gate electrode 114 is formed of a part of the gate wiring 112. At this time, the gate electrode 114 may have a wider width than other portions of the gate wiring 112. Alternatively, the gate electrode 114 may extend from the gate wiring 112.

The common wiring 116 extends along the first direction and is spaced apart from the gate wiring 112.

The substrate 110 may be made of glass or plastic. The gate wiring 112, the gate electrode 114 and the common wiring 116 are formed of aluminum, molybdenum, nickel, chromium, copper, or an alloy thereof. And may be a single layer or a multilayer structure.

Then, a gate insulating film 120 is formed over the gate wiring 112, the gate electrode 114, and the common wiring 116 to cover them. A gate insulating film 120 is substantially can be formed on the front substrate 110, a gate insulating film 120 may be formed of a silicon nitride (SiNx) or silicon oxide (SiO _2).

A semiconductor layer 122 is formed on the gate insulating layer 120 above the gate electrode 114. The semiconductor layer 122 includes an active layer 122a of intrinsic amorphous silicon and an ohmic contact layer 122b of impurity doped amorphous silicon. Alternatively, the semiconductor layer 122 may be formed of an oxide semiconductor. In this case, the ohmic contact layer 122b may be omitted, and an etch stopping layer may be formed on the semiconductor layer 122 to correspond to the gate electrode 114.

A semiconductor pattern (not shown) is formed on the gate insulating layer 120. The semiconductor pattern includes a first semiconductor pattern (not shown) and a second semiconductor pattern (not shown). The first semiconductor pattern is made of the same material as the active layer 122a and the second semiconductor pattern is made of the same material as the ohmic contact layer 122b.

Next, source and drain electrodes 134 and 136 are formed on the semiconductor layer 122. The source and drain electrodes 134 and 136 are spaced about the gate electrode 114 above the semiconductor layer 122 and the ohmic contact layer 122b has the same shape as the source and drain electrodes 134 and 136 . And the active layer 122a is exposed between the source and drain electrodes 134 and 136. [

A part of the drain electrode 136 overlaps with the common wiring 116 to form a storage capacitor. The overlapped portion of the drain electrode 136 constitutes a first capacitor electrode and the overlapping portion of the common wiring 116 constitutes a second capacitor electrode. At this time, the overlapping portion of the common wiring 116 may have a wider width than the other portions.

The active layer 122a exposed between the source and drain electrodes 134 and 136 is a thin film transistor that is formed between the source electrode 134 and the drain electrode 136. The gate electrode 114, the semiconductor layer 122, the source electrode 134, Channel of the transistor. Here, the channel of the thin film transistor has a substantially U-shaped shape, but is not limited thereto, and the channel shape of the thin film transistor may be varied.

A data line 132 is formed on the semiconductor pattern. The data line 132 extends substantially along a second direction that intersects the first direction, and intersects with the gate line 112 to define a pixel region. The data wiring 132 has a structure bent around the center of the pixel region. The data line 132 may be connected to the source electrode 134 and the source electrode 134 may extend from the data line 132. At this time, the source electrode 134 may have an opening adjacent to the data line 132. The parasitic capacitance is generated by overlapping the source electrode 134 and the gate electrode 114. The opening of the source electrode 134 reduces the overlapping area between the source electrode 134 and the gate electrode 114, .

Alternatively, the source electrode 134 may be formed as a part of the data line 132.

On the other hand, auxiliary common wiring (not shown) may extend from the common wiring 116 along the second direction, and the auxiliary common wiring may include first and second patterns (not shown) spaced apart from and parallel to each other . At this time, the first side of the data wiring 132 overlaps with the first pattern of the auxiliary common wiring, and the second side of the data wiring 132 can overlap with the second pattern of the auxiliary common wiring. Alternatively, the data wiring 132 may be located between the first pattern and the second pattern of the auxiliary common wiring.

The source and drain electrodes 134 and 136 and the data line 132 may be made of aluminum, molybdenum, nickel, chromium, copper, or an alloy thereof, Layer or multi-layer structure.

Here, the semiconductor layer 122, the semiconductor pattern, the source and drain electrodes 134 and 136, and the data line 132 are formed through a photolithography process using a single mask. At this time, the source and drain electrodes 134 and 136 and the data line 132 have widths narrower than the active layer 122a of the semiconductor layer 122 and the first semiconductor pattern of the semiconductor pattern, respectively, The upper surface of the edge of the first semiconductor pattern can be exposed by the source and drain electrodes 134 and 136 and the data line 132, respectively.

Alternatively, the semiconductor layer 122 and the source and drain electrodes 134 and 136 may be formed through respective photolithography processes using different masks. In this case, Electrodes 134 and 136, and the semiconductor pattern under the data line 132 may be omitted.

Next, a protective layer 140 is formed on the source and drain electrodes 134 and 136 and the data line 132. The protective layer 140 may be formed of an inorganic insulating material of silicon oxide (SiO ₂₎ or silicon nitride (SiNx).

A color filter layer 152 is formed in a pixel region above the protective layer 140. The color filter layer 152 includes red (R), green (G), and blue (B) color filters, and one color filter corresponds to one pixel region. In one example, the color filter layer 152 of FIG. 4 may be a red color filter.

A light shielding layer 156 is formed on the protective layer 140. The light shielding layer 156 is located in the boundary region of the edge of the pixel region, and corresponds to the gate wiring 112, the common wiring 116, and the thin film transistor. The light shielding layer 156 blocks light from being output in a region other than the pixel region. Further, the light shielding layer 156 prevents external light from entering the thin film transistor, and blocks or reduces external light from being reflected from the gate wiring 112, the common wiring 116, and the thin film transistor.

The shading layer 156 includes a first color pattern 156a and a second color pattern 156b on the first color pattern 156a. The first color pattern 156a and the second color pattern 156b may be formed of the same material as the two color filters selected from the red, green and blue color filters, Is preferable for enhancing the shading effect.

As shown in the figure, when the color filter layer 152 is formed of the same color material as the first color pattern 156a, the first color pattern 156a and the color filter layer 152 can be connected to each other without overlapping.

In addition, when the color filter layer 152 is formed of the same color material as the second color pattern 156b, the second color pattern 156b and the color filter layer 152 can be connected without overlapping each other.

Alternatively, the light shielding layer 156 may overlap with the color filter layer 152. At this time, the first and second color patterns 156a and 156b of the light shielding layer 156 and the color filter layer 152 may be formed of different color materials. In this case, the first color pattern 156a is formed first, the color filter layer 152 is formed to overlap the first color pattern 156a on the first color pattern 156a, May be formed on the color filter layer 152 to overlap with the color filter layer 152.

However, the order of stacking the first and second color patterns 156a and 156b and the color filter layer 152 is not limited thereto.

On the other hand, although not shown, a light shielding layer may also be formed on the data wiring 132.

An overcoat layer 160 is formed on the color filter layer 152 and the light shielding layer 156. The overcoat layer 160 has a substantially planar surface in the pixel region and the top surface of the overcoat layer 160 above the color filter layer 152 may be lower than the top surface of the overcoat layer 160 above the light shade layer 156.

The overcoat layer 160 has a drain contact hole 162 exposing the drain electrode 136 together with the protective layer 140. At this time, the light shielding layer 156 may have a hole corresponding to the drain contact hole 162.

The overcoat layer 160 has a common contact hole 164 for exposing the common wiring 116 together with the protective layer 140 and the gate insulating film 120. At this time, the light shielding layer 156 may have a hole corresponding to the common contact hole 164.

The overcoat layer 160 may be formed of a photo-sensitive acryl.

A pixel electrode 172 and a common electrode 174 are formed in a pixel region above the overcoat layer 160. The pixel electrode 172 and the common electrode 174 each include a plurality of patterns extending substantially along the second direction and spaced apart from each other along the first direction. The patterns of the common electrodes 174 are alternately arranged with the pattern of the pixel electrodes 172 in the first direction. Each pattern of the pixel electrode 172 and the common electrode 174 is bent with respect to the center of the pixel region and has a certain angle with respect to the second direction, and the virtual line passing through the center of the pixel region in the first direction And has a structure that is substantially symmetric. Here, the pixel electrode 172 and the common electrode 174 are bent at an angle of 45 degrees or less with respect to the second direction.

On the other hand, one pattern of the common electrode 174 adjacent to the data wiring 132 can overlap with the data wiring 132. [ The first side of the data line 132 overlaps with one pattern of the common electrode 174 of the pixel region and the second side of the data line 132 overlaps with one pattern of the common electrode 174 of the adjacent pixel region can do.

The pixel electrode 172 and the common electrode 174 may be formed of a transparent conductive material such as indium tin oxide or indium zinc oxide.

The pixel electrode connection portion 173 as the first connection portion, the common electrode connection portion 175 as the second connection portion and the common electrode contact portion 176 are formed on the same layer as the pixel electrode 172 and the common electrode 174 with the same material .

The pixel electrode connection portion 173 and the common electrode connection portion 175 extend along the first direction and are located on opposite sides of the pixel region, respectively. The pixel electrode connection portion 173 is connected to one end of the pattern of the pixel electrode 172 and overlaps with the drain electrode 136 and contacts the drain electrode 136 through the drain contact hole 162.

In addition, the common electrode connection portion 175 is connected to one end of the patterns of the common electrode 174, and can partially overlap the gate wiring 112 of the previous stage. As shown in the figure, the common electrode connection portion 175 corresponding to one pixel region can be connected to the common electrode connection portion 175 corresponding to the adjacent pixel region. Alternatively, the common electrode connection portion 175 corresponding to one pixel region may be separated from the common electrode connection portion 175 corresponding to the adjacent pixel region, and the common electrode connection portion 175 may be separated for each pixel region.

On the other hand, the common electrode contact portion 176 extends from one pattern of the common electrode 174 and / or the common electrode connection portion 175 and overlaps with the common wiring 116. The common electrode contact portion 176 contacts the common wiring 116 through the common contact hole 164.

As described above, in the embodiment of the present invention, the color filter layer 152 and the light shielding layer 156 are formed over the thin film transistors of the array substrate, thereby omitting the black matrix of the upper substrate (not shown) The aperture ratio of the liquid crystal display device can be increased.

The array substrate according to an embodiment of the present invention is bonded to an upper substrate including a column spacer to constitute a liquid crystal display device. At this time, a second column spacer for preventing the upper substrate from being pressed is formed on the upper substrate in addition to the first column spacer for maintaining the cell gap between the array substrate and the upper substrate. Within the same area, the number of second column spacers is greater than the number of first column spacers.

The first and second column spacers are formed through the same process wherein the thickness of the second column spacer is less than the thickness of the first column spacer and in order to secure a certain distance between the second column spacer and the top layer of the array substrate, The difference in thickness between the first column spacer and the second column spacer should be within a certain range.

Here, when the difference in thickness between the first column spacer and the second column spacer is smaller than a certain range, the second column spacer comes into contact with the uppermost layer of the array substrate even with a small external force. As a result, the contact density between the column spacer and the array substrate increases, and a touch failure may occur. On the other hand, when the difference between the thicknesses of the first and second column spacers is larger than a certain range, the second column spacer does not contact the uppermost layer on the array substrate even if an external force is applied.

Since the first and second column spacers are formed in the boundary region, in the liquid crystal display device including the array substrate according to the embodiment of the present invention, the first and second column spacers are formed on the light shielding layer 156 of the array substrate, As shown in FIG. At this time, the cell gap in the boundary region is smaller than the cell gap in the pixel region due to the thickness of the light shielding layer 156. Accordingly, the thicknesses of the first and second column spacers become smaller than those of the prior art, and it is difficult to form the first and second column spacers having the thickness difference within a certain range through the same process. Therefore, in the liquid crystal display device of the present invention, the gap between the second column spacer and the array substrate is secured by the step on the array substrate.

At this time, the region near the drain contact hole 162 and the common contact hole 164 is lower in height than the other regions, and it is difficult to form the first column spacer. Accordingly, the first column spacer must be disposed at a certain distance from the drain contact hole 162 and the common contact hole 164, thereby restricting the arrangement of the first column spacer. This also imposes restrictions on the arrangement of the second column spacer. Further, in order to dispose the first and second column spacers in the region except for the drain contact hole 162 and the common contact hole 164, an area of the boundary region is further required, so that the aperture ratio can be lowered.

Therefore, in the embodiment of the present invention, a step structure is formed corresponding to the drain contact hole 162 and / or the common contact hole 164 to increase the degree of freedom in arrangement of the first and second column spacers, prevent. At this time, as shown in FIG. 2, the step structure has a hole therein.

A liquid crystal display according to an embodiment of the present invention will be described with reference to FIGS. 5 and 6. FIG.

FIG. 5 is a plan view schematically illustrating a liquid crystal display device according to an embodiment of the present invention, FIG. 6 is a cross-sectional view schematically showing a liquid crystal display device according to an embodiment of the present invention, -VIB line and the VIC-VIC line. Here, FIGS. 5 and 6 show the first to third pixel regions, and each pixel region has the same structure as that shown in FIGS. 3 and 4 except for the region where the common contact hole is formed, The description is omitted or simplified.

5 and 6, a common wiring 116 is formed on a transparent first substrate 110 on which first, second, and third pixel regions P1, P2, and P3 are defined. A gate insulating layer 120 is formed on the common wiring 116 and a passivation layer 140 is formed on the gate insulating layer 120.

A light shielding layer 156 is formed on the protective layer 140. The shading layer 156 includes a first color pattern 156a and a second color pattern 156b on the first color pattern 156a. For example, the first color pattern 156a may be made of the same material as the red color filter, and the second color pattern 156b may be made of the same material as the blue color filter.

An overcoat layer 160 is formed on the light-shielding layer 156. The overcoat layer 160 has a common contact hole 164 that exposes the common wiring 116. At this time, the common contact hole 164 is also formed in the protective layer 140 and the gate insulating film 120.

Here, each of the first and second color patterns 156a and 156b may have a hole corresponding to the common contact hole 164. More specifically, the common contact hole 164 is located in the holes of the first and second color patterns 156a and 156b, and the hole of the second color pattern 156b is located in the hole of the first color pattern 156a , The second color pattern 156b may cover the side surface of the first color pattern 156a.

Alternatively, holes of the first and second color patterns 156a and 156b may be omitted, and a common contact hole 164 may also be formed in the first and second color patterns 156a and 156b.

The overcoat layer 160 may have a first protrusion 166 corresponding to the common contact hole 164 of the first pixel region P1 and a common contact hole 164 of the second pixel region P2. And may not have a protrusion corresponding to the common contact hole 164 of the third pixel region P3. The common contact hole 164 of the first pixel region P1 is also formed in the first protrusion 166 and the common contact hole 164 of the second pixel region P2 is formed in the second protrusion 168 .

Alternatively, the overcoat layer 160 may have the second protrusion 168 corresponding to the common contact hole 164 of the first pixel region P1, may not have the protrusion, and the third pixel region P3 The first contact hole 164 may have a first protrusion 166 corresponding to the common contact hole 164.

The first and second protrusions 166 and 168 protrude upward from the top surface of the overcoat layer 160 and the width w2 and the thickness of the second protrusion 168 are respectively equal to the width w1 of the first protrusion 166 ) And the thickness. For example, the overcoat layer 160, except for the first and second protrusions 166 and 168, may have a thickness of 2000 Å to 3000 Å. The width w1 of the first protrusion 166 may be 3 to 5 占 퐉 and the thickness may be 500 to 1000 占 and the width w2 of the second protrusion 168 may be 5 to 8 占 퐉 And the thickness may be 2000 A to 4000 A. However, the thickness of the overcoat layer 160 and the width and thickness of the first and second projections 166 and 168 are not limited thereto.

A common electrode contact portion 176 is formed on at least one of the overcoat layer 160 of the first to third pixel regions P1, P2 and P3 and the common electrode contact portion 176 is electrically connected to the common contact hole 164 through the common contact hole 164 And contacts the common wiring 116. At this time, the common electrode contact portion 176 may be formed in the first and third pixel regions P1 and P3, and may be omitted in the second pixel region P2. Accordingly, the common electrode contact portion 176 in the first pixel region P1 can cover the first projection portion 166. [

Alternatively, the common electrode contact portion 176 may be formed only in the first pixel region P1 or the third pixel region P3 and may be formed in all of the first to third pixel regions P1, P2, and P3 have.

Meanwhile, the second substrate 180 is disposed apart from the first substrate 110. The second substrate 180 is made of a transparent insulating material and may be made of glass or plastic.

First and second column spacers 182 and 184 are formed under the second substrate 180. At this time, the first column spacer 182 is located in the second pixel region P2, the second column spacer 184 is located in the third pixel region P3, and the first pixel region P1 is provided with a column spacer May not be formed. The first and second column spacers 182 and 184 may be formed of a transparent or opaque organic material.

Here, the first column spacer 182 is a cell gap holding spacer, the second column spacer 184 is an anti-collapse spacer, and the thickness of the first column spacer 182 is greater than the thickness of the second column spacer 184. [ The thickness of the first column spacer 182 and the thickness of the second column spacer 184 are preferably equal to or greater than 3000 angstroms. For example, the thickness of the first column spacer 182 ranges from 2.0 to 2.5 占 퐉, The thickness of the spacer 184 may be 1.7 탆 to 2.2 탆.

The first column spacer 182 corresponds to the second projection 168 and contacts the membrane on the second projection 168 or the second projection 168. On the other hand, the second column spacer 184 is spaced apart from the uppermost layer on the first substrate 110.

At this time, the lower surface of the first column spacer 182, which is in contact with the film on the second projection 168 or the second projection 168, may have an edge placed in the upper surface of the second projection 168. Accordingly, even if the second substrate 180 and the first and second column spacers 182 and 184 move due to an external force, the first column spacer 182 can be supported by the second projection 168.

Alternatively, the upper surface of the second projection 168 may be positioned within the lower surface of the first column spacer 182, but is not limited thereto.

Each of the first and second column spacers 182 and 184 may have a circular, bar or square planar structure and the maximum width of the second column spacer 184 may be a first column spacer 182, Is preferably greater than the maximum width of the first layer. For example, the first and second column spacers 182 and 184 may have a circular planar structure, and the diameter of the second column spacer 184 may be about twice the diameter of the first column spacer 182 . For example, the diameter of the first column spacer 182 may be about 15 microns, and the diameter of the second column spacer 184 may be about 30 microns.

A liquid crystal layer 190 is formed between the first substrate 110 including the common electrode contact portion 176 and the second substrate 180 including the first and second column spacers 182 and 184.

Although not shown, a first alignment layer is formed on the common electrode contact portion 176, a second alignment layer is formed on the lower or upper portion of the first and second column spacers 182 and 184, And the second alignment film. The surfaces of the first and second alignment films have a constant directional orientation by the rubbing alignment method or the photo alignment method, and the liquid crystal molecules of the liquid crystal layer 190 are initially aligned along the alignment direction of the first and second alignment films.

7 is a three-dimensional micrograph image of the second projection according to the embodiment of the present invention viewed from above.

As shown in Fig. 7, the second projection (168 in Fig. 6) has a chimney shape including a hole, i.e., a common contact hole (1624 in Fig. 6) therein, and can have an annular planar structure. At this time, the second projection (168 in Fig. 6) may have a substantially rectangular planar structure. Alternatively, the second projection (168 in Fig. 6) may have a circular planar structure. In addition, the second projection (168 in Fig. 6) may include a plurality of grooves arranged at regular intervals.

On the other hand, the first projecting portion (166 in Fig. 6) may have substantially the same shape as the second projecting portion (168 in Fig. 6).

Thus, in the liquid crystal display device according to the embodiment of the present invention, the first and second column spacers (182 in FIG. 6 and 184 in FIG. 6) are arranged above the common contact hole (168 in FIG. 6). At this time, a second protrusion (168 in Fig. 6) having a relatively thick thickness corresponding to the first column spacer (182 in Fig. 6) and including a common contact hole (164 in Fig. 6) The spacer (182 in Fig. 6) is brought into contact with the film above the second projection (168 in Fig. 6) or the second projection (168 in Fig. Also, a first protrusion (166 in Fig. 6) is formed which does not form a protrusion corresponding to the second column spacer (184 in Fig. 6) or is relatively thin.

6) by the step structure of the second projection (168 in Fig. 6) and the upper surface of the overcoat layer (160 in Fig. 6) and the second column spacer 184 can be ensured.

At this time, it is possible to reduce the contact area between the first column spacer (182 in FIG. 6) and the uppermost layer on the first substrate (110 in FIG. 6) to prevent the touch failure and to arrange the first column spacer The density of the second substrate (180 in Fig. 6) can be prevented from being deflected.

Further, the degree of freedom of arranging the first and second column spacers (182 in FIG. 6 and 184 in FIG. 6) can be increased, the area of the boundary region can be reduced, and the aperture ratio can be increased.

In the embodiment of the present invention, the first and second protrusions (166 in FIG. 6 and 168 in FIG. 6) have been described in correspondence with the common contact hole (164 in FIG. 6), but the present invention is not limited thereto. In other words, the first and second protrusions (166 in Fig. 6, 168 in Fig. 6) may be formed corresponding to the drain contact holes (162 in Fig. 4), in which case the first and second column spacers 182, 184 in FIG. 6) may be located above the drain contact hole (162 in FIG. 4).

A method of manufacturing an array substrate for a liquid crystal display according to an embodiment of the present invention will be described in detail with reference to FIGS. 8A to 8F and FIG.

FIGS. 8A to 8F are cross-sectional views schematically showing an array substrate in each step of a manufacturing process of an array substrate for a liquid crystal display according to an embodiment of the present invention, in which VIA-VI line, VIB- Sectional view corresponding to the VIC line.

8A, a first conductive material is deposited on a transparent insulating substrate 110 having first, second, and third pixel regions P1, P2, and P3 defined therein by sputtering or the like, A material layer (not shown) is formed, and the first conductive material layer is selectively patterned through a photolithography process using a mask to form the common wiring 116.

At this time, a gate electrode (114 in Fig. 4) and a gate wiring (112 in Fig. 5) are also formed. The gate electrode (114 in FIG. 4) may be part of the gate wiring (112 in FIG. 5) located in each pixel region P1, P2, and P3.

The substrate 110 may be made of glass or plastic and the first layer of conductive material may include aluminum, molybdenum, nickel, chromium, copper, or alloys thereof. And may be a single layer or multilayer structure.

Next, as shown in Fig. 8B, a gate insulating film 120 is formed on the common wiring 116, the gate electrode (114 in Fig. 4) and the gate wiring (112 in Fig. 5). The gate insulating layer 120 may be formed by depositing a first insulating material on the entire surface of the substrate 110 by a chemical vapor deposition (CVD) method using plasma. In this case, the first insulating material may be an inorganic insulating material of silicon nitride (SiNx) or silicon oxide (SiO _2), for example, it may be silicon nitride.

Next, a first semiconductor material layer (not shown) and a second semiconductor material layer (not shown) are sequentially formed on the gate insulating layer 120, and a second conductive material layer 4) and a semiconductor pattern (not shown in FIG. 4) is formed by selectively patterning the second conductive material layer and the first and second semiconductor material layers through a photolithography process using a mask, ), A source electrode (134 in FIG. 4), a drain electrode (136 in FIG. 4), and a data line (132 in FIG. Here, the mask may include a light blocking portion, a light transmitting portion, and an optically semitransmissive portion.

The first semiconductor material layer and the second semiconductor material layer may be formed by depositing amorphous silicon containing impurity and intrinsic amorphous silicon respectively by a CVD method using plasma and the second conductive material layer may be formed by sputtering a conductive material such as metal For example, by evaporation. The second conductive material layer may include aluminum, molybdenum, nickel, chromium, copper, or an alloy thereof, and may be a single layer or a multilayer structure.

Next, a protective layer 140 is formed on the source and drain electrodes (134 in FIG. 4, 136 in FIG. 4) and on the data line (132 in FIG. 4). The protective layer 140 may be formed by depositing a second insulating material on the entire surface of the substrate 110 by a CVD method using plasma. The second insulating material may be an inorganic insulating material of silicon nitride (SiNx) or silicon oxide (SiO _2), it may be in one example, silicon nitride.

Next, a first color resist (not shown) is formed on one pixel region by applying a first color resist to the entire surface of the substrate 110 substantially over the passivation layer 140 and patterning through a photolithography process using a mask And a first color pattern 156a is formed on the common wiring 116. [ At this time, the first color pattern 156a may also be formed on the source and drain electrodes (134 in Fig. 4, 136 in Fig. 4). In one example, the first color resist may be a red resist.

Here, the first color pattern 156a may have a first hole corresponding to the common wiring 116 and the drain electrode (136 in Fig. 4).

Next, as shown in FIG. 8C, a second color resist is applied to the entire surface of the substrate 110 substantially over the first color pattern 156a and the first color filter (not shown), and a photolithography process A second color filter (not shown) is formed in another pixel region, and a second color pattern 156b is formed on the first color pattern 156a. The first and second color patterns 156a and 156b form a light shielding layer 156. [ As an example, the second color resist may be a blue resist.

Here, the second color pattern 156b may have a second hole corresponding to the first hole of the first color pattern 156a. At this time, the second hole of the second color pattern 156b may be located in the first hole of the first color pattern 156a, and the second color pattern 156b may be located in the first color pattern 156b corresponding to the first hole 156a.

Next, a third color resist is applied to the entire surface of the substrate 110 substantially over the light shielding layer 156 and the second color filter, and patterned through a photolithography process using a mask, thereby forming a third color filter . The first, second and third color filters form a color filter layer (152 in Fig. 4). As an example, the third color resist may be a green resist.

Here, the order of forming the first and second color patterns 156a and 156b and the first, second, and third color filters of the light shielding layer 156 is not limited to this, and may vary.

Next, as shown in FIG. 8D, a photosensitive organic material is applied on the light shielding layer 156 and the color filter layer 152 (FIG. 4) to form a photosensitive organic film 160a. Next, the drying process may be performed to remove the solvent of the photosensitive organic film 160a. Here, the photosensitive organic layer 160a may be a photo acryl.

Next, an exposure mask 200 is disposed on the photosensitive organic film 160a, and the photosensitive organic film 160a is exposed through the exposure mask 200. [ At this time, the exposure mask 200 includes a blocking portion A1 for blocking light, a transmitting portion A2 for transmitting light, and a semi-transmitting portion A3 for partially transmitting light. That is, the transmittance of the transflective portion A3 may be lower than the transmittance of the transmissive portion A2, and the transmittance of the transflective portion A3 may be about 30% to 50%.

Here, the photosensitive organic layer 160a may have a negative photosensitive property such that a portion exposed to light remains after development. The blocking portion A1 corresponds to the upper portion of the common wiring 116 of the first to third pixel regions P1, P2 and P3 and the transmissive portion A2 corresponds to the upper portion of the first and second pixel regions P1 and P2. The transflective portion A3 is located on both sides of the blocking portion A1 of the first and second pixel regions P1 and P2 so as to surround the blocking portion A1. At this time, the width of the transmitting portion A2 of the second pixel region P2 is larger than the width of the transmitting portion A2 of the first pixel region P1. For example, the width of the transmissive portion A2 of the first pixel region P1 may be between 3 탆 and 5 탆, and the width of the transmissive portion A2 of the second pixel region P2 may be between 5 탆 and 8 탆.

Alternatively, the photosensitive organic layer 160a may have a photosensitivity in which a portion exposed to light is removed after development. In this case, the positions of the blocking portions A1 and the transmissive portions A2 are reversed.

On the other hand, although not shown, the blocking portion A1 is also located above the drain electrode (136 in Fig. 4).

Next, as shown in Fig. 8E, the exposed photosensitive organic film (160a in Fig. 8D) is developed and cured to form the overcoat layer 160. [

A common contact hole 164 is formed in each of the first to third pixel regions P1, P2, and P3 corresponding to the blocking portion (A1 in FIG. 8D) of the exposure mask (200 in FIG. 8D). 8D) of the exposure mask (200 in Fig. 8D) is formed in the first pixel region P1, and the first projection portion 166 is formed in the second pixel region P2 in the exposure mask 8D) corresponding to the transmissive portion (A2 in Fig. 8D) of the exposure mask (200 in Fig. 8D) and the remaining region is provided with a photosensitive portion An overcoat layer 160 having a lower thickness than the organic film (160a in Fig. 8D) is formed.

The common contact hole 164 of the first pixel region P1 is also formed in the first protrusion 166 and the common contact hole 164 of the second pixel region P2 is formed in the second protrusion 168 . Accordingly, the first and second projections 166 and 168 have a ring-shaped planar structure.

On the other hand, the overcoat layer 160 near the common contact hole 164 and the first and second protrusions 166 and 168 flow down into the common contact hole 164 in the curing step, The width of the second protrusion 168 is smaller than the width of the first protrusion 166 so that the degree of flow of the second protrusion 168 is smaller than that of the first protrusion 166, 166).

For example, the overcoat layer 160 excluding the first and second protrusions 166 and 168 may have a thickness of 2000 Å to 3000 Å. In addition, the width of the first protrusion 166 may be between 3 탆 and 5 탆, the thickness may be between 500 Å and 1000 Å, the width of the second protrusion 168 may be between 5 袖 m and 8 袖 m, Lt; / RTI > to 4000 Angstroms.

Next, the protective layer 140 and the gate insulating layer 120 are removed using the overcoat layer 160 as an etching mask. The common contact hole 164 is also formed in the protective layer 140 and the gate insulating film 120 and the common wiring 116 is exposed through the common contact hole 164.

4) is formed in the overcoat layer 160 of each of the first to third pixel regions P1, P2, and P3, and a drain contact hole (not shown in FIG. The hole (162 in FIG. 4) is also formed in the protective layer 140.

Next, as shown in FIG. 8F, a third conductive material layer (not shown) is deposited on the overcoat layer 160 by a method such as sputtering to form a third conductive material layer, and a photolithography process using a mask To form a common electrode contact portion 176. The common electrode contact portion 176 is formed by patterning the third conductive material layer. The common electrode contact portion 176 is formed in the first and third pixel regions P1 and P3 and is in contact with the common wiring 116 through the common contact hole 164.

4), a common electrode (174 in FIG. 4), and a common electrode connection (175 in FIG. 5) are formed in the pixel regions P1, P2, and P3, Is formed.

Here, the third conductive material layer may be formed of a transparent conductive material such as indium tin oxide or indium zinc oxide.

As described above, according to the method of manufacturing an array substrate for a liquid crystal display according to an embodiment of the present invention, the first and second protrusions 166 and 168 having different thicknesses can be formed through a single photolithography process , A stepped structure can be formed on the array substrate without increasing the number of steps.

In the above embodiment, the second protrusion 168 on the first substrate 110 includes the common contact hole 164 therein to reduce the contact area with the first column spacer 182. Alternatively, A contact area of the first column spacer 182 may be reduced by forming a protrusion not including a hole on the substrate 110 and forming a hole in the first column spacer 182.

9 is a cross-sectional view schematically showing a liquid crystal display device according to another embodiment of the present invention. The liquid crystal display device according to another embodiment of the present invention has the same structure as the previous embodiment except for the region where the common contact hole is formed, and a description of the same portion will be simplified or omitted.

9, a common wiring 216 is formed on a transparent first substrate 210 on which first, second, and third pixel regions P1, P2, and P3 are defined.

A gate insulating layer 220 is formed on the common wiring 216 and a protective layer 240 is formed on the gate insulating layer 220.

A light shielding layer 256 is formed on the protective layer 240. The shading layer 256 includes a first color pattern 256a and a second color pattern 256b over the first color pattern 256a. For example, the first color pattern 256a may be made of the same material as the red color filter, and the second color pattern 256b may be made of the same material as the blue color filter.

An overcoat layer 260 is formed on the light-shielding layer 256. The overcoat layer 260 has a common contact hole 264 that exposes the common wiring 216. At this time, the common contact hole 264 is also formed in the protective layer 240 and the gate insulating film 220.

Here, each of the first and second color patterns 256a and 256b may have a hole corresponding to the common contact hole 264. More specifically, the common contact holes 264 are located in the holes of the first and second color patterns 256a and 256b and the holes of the second color pattern 256b are located in the holes of the first color pattern 256a , The second color pattern 256b may cover the side surface of the first color pattern 156a.

Alternatively, holes of the first and second color patterns 256a and 256b may be omitted, and a common contact hole 264 may be formed in the first and second color patterns 256a and 256b.

The overcoat layer 260 may have a first protrusion 266 corresponding to the common contact hole 264 of the first pixel region P1 and a common contact hole 264 of the second pixel region P2. And may have a third protrusion 269 corresponding to the common contact hole 264 of the third pixel region P3. The common contact hole 264 of the first pixel region P1 is also formed in the first protrusion 266 and the common contact hole 264 of the second pixel region P2 is formed in the second protrusion 268 And the common contact hole 264 of the third pixel region P3 is also formed in the third projection 269. [

Alternatively, the overcoat layer 260 may have the third protrusion 269 corresponding to the common contact hole 264 of the first pixel region P1, or may not have the protrusion.

The width w13 of the third protrusion 269 and the thickness of the third protrusion 269 protrude upward from the top surface of the overcoat layer 260 such that the width of the first protrusion 266 (w11) and the width (w12) of the second projection 268 and the thickness. For example, the overcoat layer 260, excluding the first to third protrusions 266, 268, and 269, may have a thickness of 2000 Å to 3000 Å. In addition, the width w11 of the first protrusion 266 may be 3 占 퐉 to 5 占 퐉, the thickness may be 500 占 퐉 to 1000 占 and the width w12 of the second protrusion 268 may be 15 占 퐉 to 20 占 퐉 And the thickness may be 2.0 占 퐉 to 3.0 占 퐉 and the width w13 of the third protrusion 269 may be 5 占 퐉 to 8 占 퐉 and the thickness may be 2000 占 퐉 to 4000 占 퐉. However, the thickness of the overcoat layer 260 and the width and thickness of the first to third projections 266, 268, 269 are not limited thereto.

A common electrode contact portion 276 is formed on at least one of the overcoat layers 260 of the first to third pixel regions P1 to P3 and the common electrode contact portion 276 is electrically connected to the common contact hole 264 And contacts the common wiring 216. At this time, the common electrode contact portion 276 may be formed only in the first pixel region P1 and may be omitted in the second and third pixel regions P2 and P3. Thus, the common electrode contact portion 276 in the first pixel region P1 can cover the first projection 266. [ Alternatively, the common electrode contact portion 276 may also be formed in the third pixel region P3.

Meanwhile, the second substrate 280 is disposed apart from the first substrate 210. The second substrate 280 is made of a transparent insulating material and may be made of glass or plastic.

The second substrate 280 contacts the film on the second projection 268 or the second projection 268 and is spaced apart from the film on the third projection 269 or the third projection 269. [ At this time, the second projections 268 serve as cell gap holding spacers, and the third projections 269 serve as anti-collapse spacers.

Here, the overcoat layer 260 may not have protrusions corresponding to the common contact holes 264 of the third pixel region P3. In this case, under the second substrate 280 of the third pixel region P3, A spacer for preventing the pressing can be formed.

A liquid crystal layer 290 is formed between the first substrate 210 and the second substrate 280 including the common electrode contact portion 276.

Although not shown, a first alignment layer is formed on the common electrode contact portion 276, a second alignment layer is formed on the second substrate 280, and a liquid crystal layer 290 is disposed between the first and second alignment layers . The surfaces of the first and second alignment layers have a constant directionality by the rubbing alignment method or the photo alignment method, and the liquid crystal molecules of the liquid crystal layer 290 are initially arranged along the alignment direction of the first and second alignment layers.

The array substrate for a liquid crystal display according to another embodiment of the present invention may be manufactured according to the processes of FIGS. 8A to 8F, and the first to third protrusions 266, 268, The width of the transmissive portion (A2 in FIG.

As described above, in the liquid crystal display device according to another embodiment of the present invention, the second protrusion 268 on the first substrate 210 can be used as the first column spacer. Therefore, the step of forming the first column spacer on the second substrate 280 can be omitted, and the process can be simplified. At this time, the third protrusion 269 may be used as a second column spacer, and the third protrusion 269 may be omitted and a column spacer may be formed on the lower surface of the second substrate 280 to prevent the second protrusion 269 from being pressed.

In addition, in the liquid crystal display device according to another embodiment of the present invention, the contact area between the second substrate 280 and the film on the second projection 268 or the second projection 268 can be reduced, The arrangement density of the second protrusions 268 can be increased to prevent deflection of the second substrate 280.

In addition, since the second projection 268 serving as the first column spacer can be formed corresponding to the common contact hole 164, the area of the boundary region can be reduced and the aperture ratio can be increased.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention as defined in the appended claims. And changes may be made without departing from the spirit and scope of the invention.

110: substrate 112: gate wiring
114: gate electrode 116: common wiring
120: gate insulating film 122: semiconductor layer
132: data line 134: source electrode
136: drain electrode 140: protective layer
152: Color filter layer 156: Shading layer
160: Overcoat layer 162: Drain contact hole
164: common contact hole 166: first protrusion
168: second projection 172: pixel electrode
173: pixel electrode connection portion 174: common electrode
175: common electrode connection part 176: common electrode contact part

Claims (17)

Claims [1]
A gate wiring and a common wiring on the substrate;
A data line crossing the gate line and defining a pixel region;
A thin film transistor connected to the gate wiring and the data wiring;
A protective layer covering the thin film transistor;
A color filter layer located in the pixel region above the protective layer;
A light shielding layer located above the protective layer in correspondence with the common wiring;
An overcoat layer located above the color filter layer and the light blocking layer;
The pixel electrode and the common electrode located in the pixel region above the overcoat layer,
/ RTI >
Wherein the overcoat layer has a first protrusion corresponding to the common wiring, and the first protrusion includes a hole therein.
The method according to claim 1,
Wherein the overcoat layer has a contact hole on the common wiring, and the contact hole is also formed in the first projection.
3. The method of claim 2,
And the contact hole exposes the common wiring.
The method of claim 3,
And a common electrode contact portion connected to the common electrode on the overcoat layer, wherein the common electrode contact portion contacts the common wiring through the contact hole.
The method according to claim 1,
Wherein the first projection has a circular or polygonal annular planar structure.
6. The method of claim 5,
Wherein the first protrusions include a plurality of grooves arranged at regular intervals.
The method according to claim 1,
Wherein the light-shielding layer includes a first color pattern and a second color pattern on the first color pattern.
The method according to claim 1,
Wherein the overcoat layer has the first protrusion corresponding to the first pixel area and has a second protrusion corresponding to the second pixel area, the width and thickness of the first protrusion being greater than the width and thickness of the second protrusion Array substrate.
9. The method of claim 8,
Wherein the overcoat layer has a third protrusion corresponding to the third pixel region, and the width and the thickness of the third protrusion are larger than the width and thickness of the first protrusion.
An array substrate according to claim 9;
An opposing substrate spaced apart from the array substrate;
The liquid crystal layer between the array substrate and the counter substrate
/ RTI >
And the counter substrate is in contact with the film on the third projection or the third projection.
An array substrate according to any one of claims 1 to 8;
An opposing substrate spaced apart from the array substrate;
A liquid crystal layer between the array substrate and the counter substrate;
The first and second column spacers, which are located on the inner surface of the counter substrate and have different thicknesses,
Lt; / RTI >
Wherein the first column spacer is in contact with the film on the first projection or the first projection.
Forming a gate wiring and a common wiring on the substrate;
Forming a data line crossing the gate line and defining a pixel region;
Forming a thin film transistor connected to the gate wiring and the data wiring;
Forming a protective layer covering the thin film transistor;
Forming a color filter layer on the pixel region above the protective layer;
Forming a light-shielding layer on the protective layer corresponding to the common wiring;
Forming an overcoat layer on the color filter layer and the light blocking layer;
Forming a pixel electrode and a common electrode in the pixel region above the overcoat layer
Lt; / RTI >
Wherein forming the overcoat layer includes forming a first protrusion having a hole therein corresponding to the common wiring.
13. The method of claim 12,
Wherein forming the overcoat layer comprises:
Forming a photosensitive organic film;
Disposing an exposure mask including blocking portions, transmissive portions and transflective portions on the photosensitive organic film;
Exposing the photosensitive organic film through the exposure mask;
Developing and curing the exposed photosensitive organic film
Lt; / RTI >
Wherein the first protrusion corresponds to the transmissive portion.
14. The method of claim 13,
Forming the overcoat layer includes forming the first protrusion corresponding to the first pixel region and forming a second protrusion corresponding to the second pixel region, wherein the width of the first protrusion And the thickness is larger than the width and the thickness of the second projecting portion.
15. The method of claim 14,
Wherein the width of the transmissive portion of the exposure mask corresponding to the first projecting portion is larger than the width of the transmissive portion of the exposure mask corresponding to the second projecting portion.
15. The method of claim 14,
Wherein the step of forming the overcoat layer further includes the step of forming a third protrusion corresponding to the third pixel region, wherein the width and thickness of the third protrusion are larger than the width and thickness of the first protrusion, Gt;
17. The method of claim 16,
Wherein the width of the transmissive portion of the exposure mask corresponding to the third projecting portion is larger than the width of the transmissive portion of the exposure mask corresponding to the first projecting portion.

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