KR20170076184A - Array Substrate For Display Device And Method Of Fabricating The Same - Google Patents

Abstract

A thin film transistor including an active layer, a gate electrode, a source electrode, and a drain electrode disposed on the light shielding layer and having a thickness different from that of the light shielding layer and the data wiring, Wherein a light shielding layer of the first metal layer and a portion of the data wiring and a remaining portion of the data wiring of the first and second metal layers are simultaneously formed by using a transflective mask to reduce the number of exposure masks Manufacturing cost and manufacturing time are reduced, cutting of the active layer by the step is prevented, and resistance of the data wiring is reduced.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate for a display device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to an array substrate for a display device including a data line and a light-shielding layer having different thicknesses, and a manufacturing method thereof.

In view of the information age, the display field has also been rapidly developed. As a flat panel display device (FPD) having the advantages of thinning, light weight, and low power consumption in response to the information age, ), A plasma display panel device (PDP), an organic light emitting diode (OLED) display device, and a field emission display device (FED) cathode ray tube (CRT).

Recently, a touch display device (or a touch screen) having a touch panel mounted on a display panel has been spotlighted.

The touch display device is used as an output means for displaying an image and is used as an input means for inputting a user's command by touching a specific portion of the displayed image. The touch panel is operated in accordance with a position information detection method, Method, an infrared method, and an ultrasonic method.

That is, when the user touches the touch panel while viewing the image displayed on the display panel, the touch panel can detect the position information of the corresponding part and compare the detected position information with the position information of the image to recognize the user's command.

In recent years, in order to make a portable terminal such as a smart phone, a tablet PC, and the like slimmer, electrodes and wiring constituting the touch panel are connected to the substrate of the display panel (In-cell type) touch display device in which the touch panel is formed and integrated with the touch panel.

Such an insensitive-type touch display device will be described with reference to the drawings.

1 is a cross-sectional view of a conventional array substrate for an in-cell type touch display device.

1, the conventional array substrate for an in-cell type touch display device includes a substrate 20, a thin film transistor T, a common wiring 44, a common electrode 48, and a pixel electrode 50 do.

Specifically, a light shielding layer 22 is formed on each pixel region on the substrate 20, and a buffer layer 24 is formed on the entire surface of the substrate 20 above the light shielding layer 22.

An active layer 26 is formed on the buffer layer 24 corresponding to the light shielding layer 22 and a gate insulating layer 28 is formed on the entire surface of the substrate 20 above the active layer 26.

A gate electrode 30 is formed on the gate insulating layer 28 corresponding to the active layer 26 and an interlayer insulating layer 32 is formed on the entire surface of the substrate 20 above the gate electrode 30, The layer 32 and the gate insulating layer 28 have contact holes that expose both ends of the active layer 26.

A source electrode 34 and a drain electrode 36 and a data line 35 are formed on the interlayer insulating layer 32 corresponding to the active layer 26. The source electrode 34 and the drain electrode 36 Are respectively connected to both ends of the active layer 26 through the contact holes of the interlayer insulating layer 32 and the gate insulating layer 28 and the data line 35 is connected to the source electrode 34. [

The active layer 26, the gate electrode 30, the source electrode 34 and the drain electrode 36 constitute a thin film transistor (TFT) T, and the light shielding layer 22 is a thin film transistor And blocks the light that is incident on the active layer 26 of the pixel T.

A first passivation layer 38 is formed on the entire surface of the substrate 20 above the source electrode 34 and the drain electrode 36. A planarization layer 40 is formed on the entire surface of the substrate 20 above the first passivation layer 38, The planarization layer 40 has an opening exposing the first passivation layer 38 on the drain electrode 36. [

A second protection layer 42 is formed on the entire surface of the substrate 20 on the planarization layer 40. A common wiring 44 is formed on the second protection layer 42, A third passivation layer 46 is formed on the front surface of the second passivation layer 20, and the third passivation layer 46 has a contact hole exposing the common wiring 44.

A common electrode 48 is formed in each pixel region on the third passivation layer 46 and the common electrode 48 is connected to the common wiring 44 through the contact hole of the third passivation layer 46.

A fourth protective layer 50 is formed on the entire surface of the substrate 20 above the common electrode 48. The fourth protective layer 50, the third protective layer 46, the second protective layer 42, The protective layer 38 has a contact hole exposing the drain electrode 36 in the opening of the planarization layer 40.

A pixel electrode 52 is formed in each pixel region on the fifth passivation layer 50. The pixel electrode 52 includes a fourth passivation layer 50, a third passivation layer 46, a second passivation layer 42 And the contact hole of the first passivation layer 38, as shown in Fig.

Here, the common electrode 48 may be patterned for each touch block including a specific number of pixel regions, and the common electrode 48 of each touch block may be independently connected to the driver through the common line 44.

The pixel electrodes 52 may have a plurality of bar shapes spaced apart from each other.

A conventional in-cell type touch display device including such an array substrate can operate by dividing one frame into a display period and a touch period. During the display period, a common voltage is applied to the common electrode 48, A data voltage is applied to display an image by rearranging the liquid crystal layer by an electric field generated between the common electrode 48 and the pixel electrode 52. During the touch period, a touch voltage is applied to the common electrode 48, The position of the touch input can be sensed by analyzing the change of capacitance of the common electrode 48 according to the voltage.

In the conventional array substrate for an in-cell type touch display device, the common wiring 44 and the common electrode 48 of the same touch block are connected to each other. However, the common wiring 44 and the common electrode 48 of the different touch blocks, It is necessary to form the common wiring 44 and the common electrode 48 by patterning them in different layers independently of each other.

In order to prevent the common wiring 44 and the common electrode 48 of the different touch blocks from being affected by coupling or the like, a third protective layer 46 The contact hole should be formed by patterning the third passivation layer 46 to connect the common wiring 44 and the common electrode 48 of the same touch block formed of different layers.

The thickness of the dielectric layer between the common electrode 48 and the pixel electrode 52 forming the storage capacitor must be minimized so that only one insulating layer is formed in a cross sectional area The common electrode 48 and the pixel electrode 52 should be formed.

Such a limitation has a problem in that the number of exposure masks used in the fabrication of the conventional array substrate for an in-cell type touch display device increases.

For example, in a conventional array substrate for an in-cell type touch display device, a first mask for the light-shielding layer 22, a second mask for the active layer 26, a third mask for the gate electrode 30, an interlayer insulating layer 32 A fourth mask for the contact hole of the gate insulating layer 28, a fifth mask for the source electrode 34 and the drain electrode 36, a sixth mask for the opening of the planarization layer 40, 7 mask, the eighth mask for the contact hole of the third protective layer 46, the ninth mask for the common electrode 48, the fourth protective layer 50, the third protective layer 46, the second protective layer 42, The tenth mask for the contact hole of the first protective layer 38, and the eleventh mask for the pixel electrode 52, so that the manufacturing steps are increased and the manufacturing cost and the manufacturing time There is an increasing problem.

SUMMARY OF THE INVENTION The present invention has been made in order to solve such a problem, and it is an object of the present invention to provide a method of manufacturing a semiconductor device, which comprises forming a data wiring and a light shielding layer simultaneously, and simultaneously forming a source electrode, a drain electrode, And an object of the present invention is to provide an array substrate for a touch display device and a method of manufacturing the same.

According to the present invention, the light-shielding layer of the first metal layer, the data wiring part and the remaining part of the data wiring of the first and second metal layers are simultaneously formed by using the transflective mask, whereby the number of exposure masks is reduced, Another object of the present invention is to provide an array substrate for a touch display device in which breakage of an active layer due to a stepped portion is prevented and resistance of a data line is reduced.

In order to solve the above problems, the present invention provides a light-emitting device comprising a substrate, a light-shielding layer and a data wiring disposed on the substrate and having different thicknesses from each other, and an active layer, a gate electrode, And a thin film transistor including a drain electrode.

The first portion of the data line overlapping the active layer has the first thickness, and the second portion of the data line spaced apart from the active layer has the first thickness and the second thickness, Lt; RTI ID = 0.0 > 1 < / RTI > thick.

The first portion of the data wiring is made of a single layer of the first metal material, and the second portion of the data wiring is formed of a single layer of the first metal material, A first metal layer of a metal material and a second metal layer of a second metal material.

The etch selectivity of the second metal material to the first metal material may be at least 10: 1.

The array substrate for a display includes a common wiring line spaced apart from the source electrode and the drain electrode, a planarization layer disposed over the thin film transistor and the common wiring line and having an opening corresponding to the drain electrode, A common electrode disposed on the planarization layer; a first protection layer disposed on the common electrode and including a first contact hole exposing the common wiring; and a second protection layer disposed on the first protection layer, And a pixel electrode connected to the drain electrode, the pixel electrode being disposed on the first passivation layer and connected to the common electrode.

The source electrode, the drain electrode, and the common wiring may be formed of the same layer and the same material, and the connection pattern and the pixel electrode may be formed of the same layer and the same material.

The first protection layer may further include a second contact hole exposing the common electrode and a third contact hole exposing the drain electrode, and the connection pattern may be connected to the common electrode through the second contact hole And the pixel electrode may be connected to the drain electrode through the third contact hole.

In addition, the source electrode and the drain electrode may be in side contact with both ends of the active layer, and the source electrode may be connected to the data line.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor, comprising: forming a light-shielding layer and a data line having different thicknesses on a substrate; forming a thin film transistor including an active layer, a gate electrode, a source electrode and a drain electrode on the light- The present invention also provides a method of manufacturing an array substrate for a display device.

The step of forming the light shielding layer and the data line may include sequentially forming first and second metal material layers having first and second thicknesses on the substrate, The second metal material layer is exposed on the second metal material layer in a region corresponding to the light shielding layer and the data wiring outside and a third thickness is formed in a region corresponding to the data wiring spaced apart from the active layer Forming a first photoresist pattern having a fourth thickness smaller than the third thickness in an area corresponding to the light shielding layer and the data line immediately below the active layer; Forming a light shielding layer pattern and a data wiring pattern by etching the second metal material layer and the first metal material layer using a mask as a mask, Shielding layer pattern and the data wiring pattern are exposed in an area corresponding to the data line spaced from the active layer, and in a region corresponding to the light-shielding layer and the data line immediately below the active layer, Forming a second photoresist pattern having a fifth thickness by etching the light shielding layer pattern and the data wiring pattern using the second photoresist pattern as an etching mask to form the light shielding layer and the data wiring Step < / RTI >

Also, the etch selectivity of the second layer of metal material to the first layer of metal material may be at least 10: 1.

The manufacturing method of the array substrate for a display device according to the present invention includes the steps of: forming a common wiring line spaced apart from the source electrode and the drain electrode; Forming a planarization layer having an opening corresponding to the drain electrode on the thin film transistor and the common wiring; forming a common electrode on the planarization layer; exposing the common wiring to an upper portion of the common electrode; Forming a first passivation layer including a first contact hole, a pixel electrode connected to the drain electrode on the first passivation layer, and a second electrode connected to the common electrode, To form a connection pattern that is connected to the first terminal.

According to the present invention, the data wiring and the light shielding layer are formed at the same time, and the source electrode, the drain electrode, and the common wiring are simultaneously formed of the same layer and the same material, thereby reducing the number of exposure masks and reducing manufacturing cost and manufacturing time.

According to the present invention, the light-shielding layer of the first metal layer, the data wiring part and the remaining part of the data wiring of the first and second metal layers are simultaneously formed by using the transflective mask, whereby the number of exposure masks is reduced, The cutoff of the active layer due to the stepped portion is prevented, and the resistance of the data line is reduced.

1 is a cross-sectional view of a conventional array substrate for an in-cell type touch display device.
2 is a sectional view of an array substrate for a self-capacitance type in-cell type touch display device according to a first embodiment of the present invention.
3 is a plan view of a self-capacitance type in-cell type touch display device according to a second embodiment of the present invention.
4 is a sectional view of an array substrate for a self-capacitance type in-cell type touch display device according to a second embodiment of the present invention.
5A to 5M are cross-sectional views for explaining a manufacturing method of an array substrate for a self-capacitance type in-cell type touch display device according to a second embodiment of the present invention.

Hereinafter, an array substrate for a display device and a method of manufacturing the same according to the present invention will be described with reference to the accompanying drawings, taking an in-cell type touch display device as an example.

2 is a cross-sectional view of an array substrate for an in-cell type touch display device of the self-capacitance type according to the first embodiment of the present invention.

2, an array substrate for a self-capacitance type in-cell type touch display device according to the first embodiment of the present invention includes a substrate 120, a light-shielding layer 122, The common electrode 146 and the pixel electrode 150. The substrate 120 may be one of two substrates constituting the liquid crystal panel.

A light shielding layer 122 and a data wiring 124 are formed in each pixel region on the substrate 120 and a buffer layer 126 is formed on the entire surface of the substrate 120 over the light shielding layer 122 and the data wiring 124. [ Is formed.

The light shielding layer 122 is for blocking light incident on the active layer 126 of the thin film transistor T and may be made of an opaque metal material, for example.

The data line 124 is for transferring a data voltage to the thin film transistor T, and defines a pixel region intersecting with a gate line (not shown).

The light-shielding layer 122 and the data line 124 are formed using one exposure mask, and may be formed of the same layer and the same material.

An active layer 128 is formed on the buffer layer 126 corresponding to the light shielding layer 122 and a gate insulating layer 130 is formed on the entire surface of the substrate 120 over the active layer 128.

The active layer 128 may be formed of silicon such as amorphous silicon, polycrystalline silicon, indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), zinc indium And an oxide semiconductor material such as zinc indium oxide (ZIO).

A gate electrode 132 is formed on the gate insulating layer 130 corresponding to the active layer 128 and an interlayer insulating layer 134 is formed on the entire surface of the substrate 120 over the gate electrode 132. In the interlayer insulating layer 134, The gate insulating layer 130, the active layer 128 and the buffer layer 126 have contact holes that expose the data wiring 124 and the buffer layer 126.

A source electrode 136 and a drain electrode 138 are formed on the upper portion of the interlayer insulating layer 134 corresponding to the active layer 128 and the interlayer insulating layer 134 in a region spaced apart from the active layer 128, A source line 136 is formed on the gate insulating layer 130 and the active layer 128. The source line 136 is formed on the gate insulating layer 130 and the active layer 128, And the data line 124 through the contact hole of the buffer layer 126.

At this time, the source electrode 136 and the drain electrode 138 are electrically connected to the active layer 128 through the contact holes of the interlayer insulating layer 134, the gate insulating layer 130, the active layer 128 and the buffer layer 126, respectively. And is laterally contacted at both ends.

The source electrode 136, the drain electrode 138 and the common wiring 140 may be formed of the same material and the same material and may be formed of a material such as aluminum (Al), molybdenum (Mo), titanium (Ti), neodymium Nd). ≪ / RTI >

Here, the active layer 128, the gate electrode 132, the source electrode 136, and the drain electrode 138 constitute a thin film transistor (TFT) T.

A first passivation layer 142 is formed on the entire surface of the substrate 120 over the source electrode 136, the drain electrode 138 and the common wiring 140. The first passivation layer 142 is formed on the front surface of the substrate 120 The planarization layer 144 has an opening exposing the drain electrode 138 and the first passivation layer 142 on the common wiring 140. The planarization layer 144 is formed on the planarization layer 144,

The first passivation layer 142 may be formed of an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiN x), and the planarization layer 144 may be formed of an organic insulating material such as photo acryl have.

The first passivation layer 142 is used to improve the contact characteristics between the planarization layer 144 of the organic insulating material and the source electrode 136, the drain electrode 138 and the common wiring 140 of the metal material. The first protective layer 142 may be omitted in another embodiment in which the characteristics are not problematic.

A common electrode 146 is formed on the planarization layer 144 and a second passivation layer 148 is formed on the entire surface of the substrate 120 above the common electrode 146. The second passivation layer 148 is formed on the common electrode 146, The second passivation layer 148 and the first passivation layer 142 have a contact hole exposing the drain electrode 138 and the common wiring 140.

The common electrode 146 is made of a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) ) it may be formed of an inorganic insulating material such as silicon oxide (SiO ₂₎ or silicon nitride (SiNx).

The pixel electrode 150 is formed on the second passivation layer 148 corresponding to the drain electrode 138 and the pixel electrode 150 is formed on the second passivation layer 148 corresponding to the common electrode 146 and the common wiring 140 The pixel electrode 150 is connected to the drain electrode 138 through the contact hole of the second passivation layer 148 and the first passivation layer 142 and the connection pattern 152 is connected to the drain electrode 138 through the contact hole of the first passivation layer 148 and the first passivation layer 142, 2 protective layer 148 to the common electrode 146 and is connected to the common wiring 140 through the contact holes of the second protective layer 148 and the first protective layer 142. [

That is, the common wiring 140 and the common electrode 146 are electrically connected to each other through the connection pattern 152.

The pixel electrode 150 and the connection pattern 152 may be made of a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) .

Here, the common electrode 146 may be patterned for each touch block including a specific number of pixel regions, and the common electrode 146 of each touch block is electrically connected to the driver (180 in FIG. 2) Can be connected.

The pixel electrode 150 may have a plurality of bar shapes spaced apart from each other and a horizontal electric field may be generated between the common electrode 146 and the pixel electrode 150 by a common voltage and a data voltage.

As described above, in the array substrate for an in-cell type touch display device of the self-capacitance type according to the first embodiment of the present invention, the light-shielding layer 122 and the data line 124 are formed simultaneously with one exposure mask, The contact hole and the connection pattern 152 for connecting the pixel electrode 150 and the drain electrode 138 are formed simultaneously with the formation of the electrode 136 and the drain electrode 138 and the common wiring 140 with one exposure mask, The total number of exposure masks used in the manufacturing process can be reduced from 11 to 9 in the related art by simultaneously forming the contact holes for connecting the common electrode 146 and the common wiring 140 with one exposure mask, As a result, manufacturing cost and manufacturing time can be reduced.

However, in the array substrate for an in-cell type touch display device of the self-capacitance type according to the first embodiment of the present invention, when the thin film transistor T includes the active layer 128 of polycrystalline silicon, The polycrystalline silicon layer is formed by crystallization after the polycrystalline silicon is used as the active layer 128. The process of forming the thin film transistor T using polycrystalline silicon as the active layer 128 includes a dehydrogenation process, a hydrogenation process, Temperature heat treatment process.

Since the high-temperature heat treatment process proceeds after formation of the light-shielding layer 122 and the data line 124 under the active layer 128, a relatively weak heat-resistant metal material such as aluminum (Al) 124). ≪ / RTI >

Accordingly, the light-shielding layer 122 and the data wiring 124 are formed of a relatively heat-resistant metal material such as molybdenum (Mo). Since molybdenum (Mo) has a higher resistance than aluminum (Al) The light shielding layer 122 and the data wiring 124 must be formed with a relatively thick thickness in order to reduce the resistance of the light shielding layer 122 and the data wiring 124 after the crystallization process. S may be cut off due to the breakage of the active layer 128.

In another embodiment, in order to prevent disconnection of the active layer, the light-shielding layer and the data wiring under the active layer are formed of a single layer of the first metal layer, and the data wiring spaced apart from the active layer is formed of the first and second metal layers It can be formed as a double layer, which will be described with reference to the drawings.

FIG. 3 is a plan view of a self-capacitance type in-cell type touch display device according to a second embodiment of the present invention, and FIG. 4 is a cross- A buffer layer 226, an active layer 228, a gate insulating layer 230, a gate electrode 232, an interlayer insulating layer 234, a source electrode 236, a drain electrode 238, The configuration of the pixel electrode 250 and the connection pattern 252 are the same as those of the first embodiment (the first embodiment), the first protection layer 242, the planarization layer 244, the common electrode 246, the second protection layer 248, And description thereof will be omitted.

3, the self-capacitance type in-cell type touch display apparatus according to the second embodiment of the present invention includes a touch display panel 210 and a driving unit 280. As shown in FIG.

The touch display panel 210 includes a plurality of common electrodes 246 disposed on each touch block on the substrate 220 and a plurality of common electrodes 246 connecting the common electrodes 246 and the driving unit 280 And common wiring 240, wherein the common electrodes 246 of each touch block may have a rectangular shape.

Although not shown, the touch display panel 210 may be a liquid crystal panel including two substrates spaced apart from each other and a liquid crystal layer between two substrates, and the plurality of common electrodes 246 may be formed of two substrates The touch display panel 210 may perform a display operation using a common voltage or perform a touch operation using a touch voltage.

The driving unit 280 applies a common voltage to a plurality of common electrodes 246 of the touch display panel 210 during a display period of one frame and generates a common voltage between the common electrode 240 and the pixel electrode 250 The liquid crystal molecules of the liquid crystal layer may be rearranged into an electric field to display an image or a touch voltage may be applied to a plurality of common electrodes 246 of the touch display panel 210 during a touch period of one frame, The position of the touch input is sensed by analyzing the change of the capacitance of the common electrode 246.

The driving unit 280 may further supply a gate voltage and a data voltage to the touch display panel 210 for a display operation.

4, an array substrate for an in-cell type touch display device of the self-capacitance type according to the second embodiment of the present invention includes a substrate 220, a light-shielding layer 222, a data wiring 224, A common electrode 240, a common electrode 246 and a pixel electrode 250. The substrate 220 may be one of two substrates constituting a liquid crystal panel.

A light shielding layer 222 and a data wiring 224 are formed in each pixel region on the substrate 220 and a buffer layer 226 is formed on the entire surface of the substrate 220 over the light shielding layer 222 and the data wiring 224. [ Is formed.

The light shielding layer 222 is for blocking light incident on the active layer 226 of the thin film transistor T and may be made of a relatively opaque first metal material such as titanium have.

The data line 224 is for transferring a data voltage to the thin film transistor T. The data line 224 intersects the gate line (not shown) to define the pixel region. The data line 224 has a relatively small first thickness (t1 in FIG. 5A) A first metal layer 224a of a first metal layer 224a and a second metal layer 224b of a second metal layer 224b formed on the first metal layer 224a and having a relatively large second thickness (t2 in Figure 5a) , The second metal material may be a material that is relatively heat resistant and has a relatively high etch selectivity to the first metal material.

The first metal layer 224a is formed on the entire data line 224 while the second metal layer 224b is formed on a portion of the data line 224 to expose the first metal layer 224a. The first metal layer 224a exposed to the outside of the first metal layer 224b and the second metal layer 224b is overlapped with the active layer 228 immediately below the active layer 228 formed in the subsequent process, May be spaced apart from the active layer 228 in areas other than immediately below and below the active layer 228.

That is, the light-shielding layer 222 and the data wiring 224 immediately under the active layer 228 are formed with the first thickness t1, and the data wiring 224 in the region other than directly below the active layer 228 And a thickness t1 + t2 corresponding to the sum of the first thickness t1 and the second thickness t2.

As described above, since the light-shielding layer 222 and the data line 224 overlapping the active layer 228 have a relatively small first thickness t1, they have relatively small stepped portions S, Cutting of the active layer 228 after the crystallization process by the step S of the light-shielding layer 222 and the data line 224 overlapping the active layer 228 is prevented.

The data line 224 spaced from the active layer 228 has a thickness t1 + t2 corresponding to the sum of the relatively large first and second thicknesses t1 and t2, And as a result, the voltage drop and the delay of the signal flowing through the data line 224 can be prevented.

The light shielding layer 222 and the data wiring 224 may be formed simultaneously using a transflective mask including a transmissive region, a blocking region, and a transflective region, and the first metal layer 224a of the data line 224 and the light- The light-shielding layer 222 may be composed of the same material and the same material.

An active layer 228 is formed on the buffer layer 226 corresponding to the light shielding layer 222 and a gate insulating layer 230 is formed on the entire surface of the substrate 220 over the active layer 228.

The active layer 228 may be formed of silicon such as amorphous silicon, polycrystalline silicon, indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), zinc indium And an oxide semiconductor material such as zinc indium oxide (ZIO).

In particular, since the light-shielding layer 222 and the data line 224 overlapping the active layer 228 are formed with a relatively small first thickness t1, the amorphous silicon layer is deposited and crystallized to form a polycrystalline silicon layer Cutting of the active layer 228 by the step S of the light-shielding layer 222 and the data wiring 224 overlapping the active layer 228 after the crystallization process is prevented.

A gate electrode 232 is formed on the gate insulating layer 230 corresponding to the active layer 228 and an interlayer insulating layer 234 is formed on the entire surface of the substrate 120 over the gate electrode 232, A source electrode 236 and a drain electrode 238 which are spaced apart from each other are formed on an upper portion of the interlayer insulating layer 234 corresponding to the active layer 228 and on an upper portion of the interlayer insulating layer 234 in a region spaced apart from the active layer 228 A common wiring 240 that is spaced apart from the source electrode 236 and the drain electrode 238 is formed.

Here, the source electrode 236 is connected to the data line 224 through the contact holes of the interlayer insulating layer 234, the gate insulating layer 230, the active layer 228 and the buffer layer 226, and the source electrode 236 And the drain electrode 238 are in contact with both ends of the active layer 228 through the contact holes of the interlayer insulating layer 234, the gate insulating layer 230, the active layer 228 and the buffer layer 226, contact.

The active layer 228, the gate electrode 232, the source electrode 236 and the drain electrode 238 constitute a thin film transistor (TFT) T.

A first passivation layer 242 is formed on the entire surface of the substrate 220 above the source electrode 236, the drain electrode 238 and the common wiring 240. The front surface of the substrate 220 on the first passivation layer 242 A common electrode 246 is formed on the planarization layer 244 and a second protective layer 248 is formed on the entire surface of the substrate 220 over the common electrode 246. The planarization layer 244 is formed on the planarization layer 244, A pixel electrode 250 is formed on the second passivation layer 248 corresponding to the drain electrode 238 and a second passivation layer 248 is formed on the common electrode 246 and the common wiring 240, And a connection pattern 252 is formed on the upper portion.

Here, the pixel electrode 250 is connected to the drain electrode 238 through the contact holes of the second passivation layer 248 and the first passivation layer 242, and the connection pattern 252 is connected to the second passivation layer 248, And is connected to the common wiring 240 through the contact hole of the first passivation layer 242 and the second passivation layer 248 and is connected to the common wiring 240 through the contact hole of the second passivation layer 248 and the first passivation layer 242, The common electrodes 246 are electrically connected to each other through the connection pattern 252.

As described above, in the array substrate for an in-cell type touch display device of the self-capacitance type according to the second embodiment of the present invention, the light shielding layer 222 and the data wiring 224 are formed as a single exposure mask And the source electrode 236 and the drain electrode 238 and the common wiring 240 are simultaneously formed with one exposure mask and connected to the contact hole for connection between the pixel electrode 250 and the drain electrode 238 The contact holes for connecting the pattern 252 to the common electrode 246 and the common wiring 240 are simultaneously formed with one exposure mask so that the total number of exposure masks used in the manufacturing process is changed from 11 to 9 And as a result, manufacturing cost and manufacturing time can be reduced.

The light shielding layer 222 and the data wiring 224 overlapping the active layer 228 immediately under the active layer 228 are formed with a relatively small first thickness t1 and are formed directly on the active layer 228 The data wiring 224 spaced apart from the active layer 228 in a region other than the lower portion is formed with a sum t1 + t2 of the first and second thicknesses t1 and t2 which are relatively large, It is possible to prevent the active layer 228 from being cut by the step portion S of the light shielding layer 222 and the data wiring 224 overlapping with the layer 228 and reduce the resistance of the data wiring 224. [

A manufacturing method of the array substrate according to the second embodiment will be described with reference to the drawings.

5A to 5M are cross-sectional views for explaining a manufacturing method of an array substrate for a self-capacitance type Insel-type touch display device according to a second embodiment of the present invention.

5A, a first metal material layer 260 and a second metal material layer 262 are sequentially formed on the substrate 220 using the first and second metal materials, After a photoresist layer (not shown) is formed over the material layer 262, a first mask (not shown) is disposed over the photoresist layer.

The first metal material layer 260 is made of a relatively opaque first metal material such as titanium and has a first thickness t1 and the second metal material layer 262 is molybdenum Mo, And a second thickness t2 that is greater than the first thickness t1, wherein the etching rate of the second metal material is greater than the etching rate of the first metal material, The etching selectivity of the second metal material to the first metal material is relatively large. For example, the etch selectivity ratio of the second metal material to the first metal material may be at least about 10: 1.

At this time, the first mask includes a semi-transmissive region A including ultraviolet rays, a blocking region C blocking ultraviolet rays, and a semi-transmissive region B having a transmissivity with respect to ultraviolet rays larger than that of the transmissive region, And the transmissive mask may correspond to an area where the transmissive area A is not formed with the light shielding layer 222 (FIG. 4) and the data line (FIG. 4) 224, The photoresist layer 224 is formed so as to correspond to the data line 224 other than directly below the layer 228 and to correspond to the light shielding layer 222 and the data line 224 immediately below the active layer 228, As shown in FIG.

Then, the photoresist layer is exposed by irradiating ultraviolet rays through the semi-transparent mask, and the exposed photoresist layer is developed to form the first photoresist pattern 270, The photoresist layer is completely removed and the photoresist layer corresponding to the blocking region C of the semi-transparent mask is maintained as it is and has the third thickness t3, and the photoresist layer corresponding to the semi-transparent region B of the semi- The resist layer is partly removed and partly remains to have a fourth thickness t4.

Accordingly, the first photoresist pattern 270 exposes the second metal material layer 262 in the region where the light shielding layer (222 in FIG. 4) and the data line (224 in FIG. 4) are not formed, and the active layer 228 In the region corresponding to the data line 224 except for the lower portion directly below the active layer 228 and the third thickness t3 in the region corresponding to the data line 224 immediately under the active layer 228, And a fourth thickness t4 that is less than the thickness t3.

5B, the second metal material layer 262 and the first metal material layer 260 are sequentially etched using the first photoresist pattern 270 as an etching mask, A pattern 264 and a data wiring pattern 266. The light shielding layer pattern 264 includes a first layer 264a of a first metal material and a second layer 264b of a second metal material, The wiring pattern 266 includes a first layer 266a of a first metallic material and a second layer 266b of a second metallic material.

For example, the second metal material layer 262 may be etched by wet etching and the first metal material layer 260 may be etched by dry etching in succession, The second metal material layer 262 can be etched without affecting the first metal material layer 260 during wet etching because the etching selectivity ratio of the second metal material to the first metal material layer 260 is greater than about 10: 1.

The second photoresist pattern 272 is formed by ashing the first photoresist pattern 270 to form a third photoresist pattern 272 having a third thickness corresponding to the blocking region C of the semi- a part of the first photoresist pattern 270 having a thickness t3 is removed and a part of the first photoresist pattern 270 is left to have the fifth thickness t5 and the fourth thickness t4 corresponding to the transflective region B of the semi- The first photoresist pattern 270 is completely removed.

The second photoresist pattern 272 is formed between the second layer 264b of the light shielding layer pattern 222 and the light shielding layer pattern 264 in the region corresponding to the data wiring 224, The second layer 266b of the wiring pattern 266 is exposed and the fourth thickness t4 is subtracted from the third thickness t3 in a region corresponding to the data wiring 224 other than immediately below the active layer 228 And a fifth thickness t5, which is a value.

The second layer 264b of the light shielding layer pattern 264 and the second layer 266b of the data wiring pattern 266 are patterned by using the second photoresist pattern 272 as an etching mask, And the light-shielding layer 222 and the data wiring 224 are formed by etching.

For example, the second layer 264b of the light-shielding layer pattern 264 and the second layer 266b of the data wiring pattern 266 may be etched by wet etching or dry etching, The first layer 264a of the light layer pattern 264 and the first layer 266a of the data wiring pattern 266 do not affect the wet etching or dry etching because the etch selectivity ratio of the metal material is not less than about 10: The second layer 264b of the light-shielding layer pattern 264 and the second layer 266b of the data wiring pattern 266 can be etched.

The second photoresist pattern 272 is removed to complete the light shielding layer 222 and the data wiring 224 as shown in FIG. 5E.

As described above, after the first and second metal material layers 260 and 262 are continuously formed on the substrate 220, the first mask having the first thickness t1 is formed using the first mask as the semi- The first metal layer 224a of the first thickness t1 and the first metal layer 224a of the first thickness t1 are formed only in the regions directly under the active layer 228 and the first metal layer 224a of the first thickness t1 immediately below the active layer 228, And the second metal layer 224b of the second thickness t2 can be formed at the same time.

Therefore, the step difference S between the light-shielding layer 222 overlapping the active layer 228 and the data line 224, which is a relatively small first thickness t1, without increasing the number of exposure masks, The voltage drop and the delay of the signal flowing through the data line 224 can be prevented by the relatively large second thickness t2.

A buffer layer 226 may be formed on the entire surface of the substrate 220 over the light-shielding layer 222 and the data line 224 using an insulating material such as silicon or oxide semiconductor material, (Not shown) is formed on the light-shielding layer 226, and a photolithography process using a second mask including an exposure of the photoresist layer, development and etching of the active material layer, An active layer 228 is formed over the buffer layer 226.

Since the light-shielding layer 222 and the data line 224 overlapping the active layer 228 are formed with a relatively small first thickness t1, the amorphous silicon layer is deposited and then crystallized to form a polycrystalline silicon layer Cutting of the active layer 228 by the step S of the light-shielding layer 222 and the data wiring 224 overlapping the active layer 228 after the crystallization process is prevented.

A gate insulating layer 230 is formed of an insulating material on the entire surface of the substrate 220 over the active layer 228 and then a gate insulating layer 230 is formed on the gate insulating layer 230 using a metal material. (Not shown), and a photolithography process using a third mask, including exposure and development of the photoresist layer and etching of the gate material layer, to form the upper portion of the gate insulation layer 230 corresponding to the active layer 228 A gate electrode 232 is formed.

An interlayer insulating layer 234 is formed of an insulating material on the entire surface of the substrate 220 above the gate electrode 232 and the exposed and developed portions of the photoresist layer and the interlayer insulating layer 234, The gate insulating layer 230, the active layer 228, and the gate insulating layer 230 through the photolithography process using the fourth mask including the etching of the insulating layer 230, the active layer 228 and the buffer layer 226, And a contact hole exposing the inside of the buffer layer 226 and the data line 224 are formed in the buffer layer 226.

As shown in FIG. 5I, a metal material layer (not shown) is formed on the interlayer insulating layer 234 using a metal material, and a fifth layer including a photoresist layer, A source electrode 236 and a drain electrode 238 spaced apart from each other are formed on the interlayer insulating layer 234 corresponding to the active layer 228 through a photolithography process using a mask and the source electrode 236 and the drain electrode 238 spaced apart from the active layer 228 A common wiring 240 spaced apart from the source electrode 236 and the drain electrode 238 is formed on the interlayer insulating layer 234 in the region.

At this time, the source electrode 236 is connected to the data line 224 through the contact holes of the interlayer insulating layer 234, the gate insulating layer 230, the active layer 228 and the buffer layer 226, and the source electrode 236 And the drain electrode 238 are in contact with both ends of the active layer 228 through the contact holes of the interlayer insulating layer 234, the gate insulating layer 230, the active layer 228 and the buffer layer 226, contact.

The light shielding layer 222 and the data wiring 224 are formed simultaneously with the first mask and the source electrode 236 and the drain electrode 238 and the common wiring 240 are formed simultaneously with the fifth mask, The number of masks can be reduced.

A first protective layer 242 is formed on the entire surface of the substrate 220 over the source electrode 236, the drain electrode 238 and the common wiring 240 using an inorganic insulating material as shown in FIG. 5J A planarization layer 244 is formed on the entire surface of the substrate 220 on the first protective layer 242 using an organic insulating material and a photolithography process using a sixth mask including exposure and development of the planarization layer 244 An opening is formed in the planarization layer 244 to expose the drain electrode 238 and the first passivation layer 242 over the common wiring 240.

In the second embodiment, the planarization layer 244 is formed of a photosensitive organic insulation material. However, in another embodiment, a photoresist layer may be formed on the planarization layer 244 of a photosensitive organic insulation material, The photoresist layer may be exposed and developed using a mask, and the planarization layer 244 may be etched to form openings.

As shown in FIG. 5K, a common electrode material layer (not shown) is formed on the planarization layer 244 using a transparent conductive material, and a photoresist layer is formed on the planarization layer 244, A common electrode 246 is formed on the planarization layer 244 through a photolithography process using a mask.

A second protective layer 248 is formed on the entire surface of the substrate 220 above the common electrode 246 by using an inorganic insulating material, and exposure and development of the photoresist layer, A common electrode 246 is formed on the second passivation layer 248 through a photolithography process using an etch of the first passivation layer 248 and an eighth mask including the second passivation layer 248 and the etching of the first passivation layer 242 A contact hole exposing the drain electrode 238 and the common wiring 240 is formed in the second passivation layer 248 and the first passivation layer 242. [

As shown in FIG. 5M, a pixel electrode material layer (not shown) is formed on the second passivation layer 248 using a transparent conductive material, and the photoresist layer is exposed and developed and the pixel electrode material layer is etched The pixel electrode 250 is formed on the second passivation layer 248 corresponding to the drain electrode 238 through the photolithography process using the ninth mask including the ninth mask and the pixel electrode 250 is formed on the common electrode 246 and the common wiring 240 And a connection pattern 252 is formed on the corresponding second protective layer 248.

At this time, the pixel electrode 250 is connected to the drain electrode 238 through the contact holes of the second passivation layer 248 and the first passivation layer 242, and the connection pattern 252 is connected to the second passivation layer 248, And is connected to the common electrode 240 through the contact hole of the first passivation layer 242 and the second passivation layer 248.

That is, the common wiring 240 and the common electrode 246 are electrically connected to each other through the connection pattern 252.

The common electrode 240 and the common electrode 240 are formed in the same layer and the same material as the source electrode 236 and the drain electrode 238 and the common electrode 240 and the common electrode 240 are formed in the same layer as the pixel electrode 250, The second protective layer 248 for connecting the pixel electrode 250 and the drain electrode 238 and the second protective layer 248 for connecting the first protective layer 242 and the second protective layer 242, A second protection layer 248 for connecting the connection pattern 252 and the common electrode 246 and a second protection layer 248 for connecting the connection pattern 252 and the common wiring 240 And the contact hole of the first protective layer 242 can be formed simultaneously with the seventh mask, and as a result, the number of exposure masks can be reduced, thereby reducing manufacturing cost and manufacturing time.

The data line 224 under the buffer layer 226 can be applied to a display area including a pixel area in a part requiring the light shielding layer 222 in the touch display panel 210, In a non-display region where the layer 222 includes unnecessary portions, for example, a circuit portion such as a gate-in-panel (GIP) or a multiplexer (MUX), the source electrode 236, The data wiring can be formed in the same layer as the common wiring 240 and the common wiring 238 and the common wiring 240.

As described above, in the array substrate for an in-cell type touch display device of the self-capacitance type according to the second embodiment of the present invention, the light shielding layer 222 and the data wiring 224 are formed as a single exposure mask And the source electrode 236 and the drain electrode 238 and the common wiring 240 are simultaneously formed with one exposure mask and connected to the contact hole for connection between the pixel electrode 250 and the drain electrode 238 The contact holes for connecting the pattern 252 to the common electrode 246 and the common wiring 240 are simultaneously formed with one exposure mask so that the total number of exposure masks used in the manufacturing process is changed from 11 to 9 And as a result, manufacturing cost and manufacturing time can be reduced.

The thickness of the insulating layer between the common electrode 246 and the data wiring 224 is increased by the formation of the data wiring 224 under the buffer layer 226 and the distance between the common electrode 246 and the data wiring 224 The parasitic capacitance can be minimized and as a result the thickness of the planarization layer 244 can be reduced to simplify the process and reduce manufacturing costs.

The light shielding layer 222 and the data wiring 224 overlapping the active layer 228 immediately under the active layer 228 are formed with a relatively small first thickness t1 and are formed directly on the active layer 228 The data wiring 224 spaced apart from the active layer 228 in a region other than the lower portion is formed with a sum t1 + t2 of the first and second thicknesses t1 and t2 which are relatively large, It is possible to prevent the breakage of the active layer 228 due to the step S of the light shielding layer 222 and the data wiring 224 overlapping with the layer 228 and reduce the resistance of the data wiring 224, And delay can be prevented.

In the first and second embodiments, the data wiring and the light shielding layer formed on the substrate having different thicknesses are applied to the array substrate for the in-cell type touch display device. However, The data wiring and the light shielding layer having a thin thickness and the portion not overlapped with the active layer overlapping with the layer can be applied to an array substrate for a liquid crystal display device or an array substrate for an organic light emitting diode display device, The cutting of the active layer after the crystallization process is prevented by the portion having a thin thickness of the data wiring and the light shielding layer and the wiring resistance is reduced by the portion having the thick thickness of the data wiring and the light shielding layer, Delay can be prevented.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It can be understood that

110: touch display panel 120: substrate
222: shielding layer 224: data wiring
T: thin film transistor 140: common wiring
144: planarization layer 146: common electrode
150: pixel electrode

Claims (12)

Claims [1]
A light-shielding layer and a data line disposed on the substrate and having different thicknesses;
A thin film transistor arranged on the light shielding layer and including an active layer, a gate electrode, a source electrode and a drain electrode,
And a plurality of pixel electrodes.
The method according to claim 1,
Wherein the light-shielding layer has a first thickness,
Wherein a first portion of the data line overlapping the active layer has the first thickness and a second portion spaced apart from the active layer corresponds to a sum of the first thickness and a second thickness greater than the first thickness And a thickness of the first substrate.
3. The method of claim 2,
Wherein the light-shielding layer comprises a single layer of a first metal material,
Wherein the first portion of the data line comprises a single layer of the first metal material and the second portion of the data line comprises a first metal layer of the first metal material and a second layer of a second metal layer of the second metal material, And a plurality of pixel electrodes.
The method of claim 3,
Wherein the etch selectivity of the second metal material to the first metal material is at least 10: 1.
The method according to claim 1,
A common wiring line spaced apart from the source electrode and the drain electrode;
A planarization layer disposed on the thin film transistor and the common wiring and having an opening corresponding to the drain electrode;
A common electrode disposed on the planarization layer;
A first protection layer disposed on the common electrode and including a first contact hole exposing the common wiring;
A connection pattern disposed on the first protection layer and connected to the common electrode and connected to the common wiring through the first contact hole;
A pixel electrode disposed on the first passivation layer and connected to the drain electrode,
Further comprising: a substrate;
6. The method of claim 5,
Wherein the source electrode, the drain electrode, and the common wiring are formed of the same layer and the same material,
Wherein the connection pattern and the pixel electrode are made of the same layer and the same material.
The method according to claim 6,
Wherein the first protective layer further includes a second contact hole exposing the common electrode and a third contact hole exposing the drain electrode,
The connection pattern is connected to the common electrode through the second contact hole,
And the pixel electrode is connected to the drain electrode through the third contact hole.
8. The method of claim 7,
The source electrode and the drain electrode are in side contact with both ends of the active layer,
And the source electrode is connected to the data line.
Forming light-shielding layers and data lines having different thicknesses on the substrate;
Forming a thin film transistor including an active layer, a gate electrode, a source electrode, and a drain electrode on the light shielding layer
And a step of forming an array substrate.
10. The method of claim 9,
Wherein the step of forming the light-shielding layer and the data wiring comprises:
Sequentially forming first and second metallic material layers having first and second thicknesses on the substrate, respectively;
The second metal material layer is exposed on the second metal material layer using a transflective mask in a region corresponding to the light shielding layer and the data wiring outside, Forming a first photoresist pattern having a third thickness in the region and a fourth thickness smaller than the third thickness in a region corresponding to the light shielding layer and the data line immediately below the active layer;
Forming a light shielding layer pattern and a data wiring pattern by etching the second metal material layer and the first metal material layer using the first photoresist pattern as an etching mask;
The first photoresist pattern is ashed to expose the light shielding layer pattern and the data wiring pattern in a region corresponding to the data wiring spaced apart from the active layer, and the light shielding layer and the data wiring Forming a second photoresist pattern having a fifth thickness in a region corresponding to the first photoresist pattern;
Forming the light shielding layer and the data wiring by etching the light shielding layer pattern and the data wiring pattern using the second photoresist pattern as an etching mask
And a step of forming an array substrate.
10. The method of claim 9,
Wherein the etch selectivity of the second metal material layer to the first metal material layer is at least 10: 1.
10. The method of claim 9,
Forming a common wiring line spaced apart from the source electrode and the drain electrode;
Forming a planarization layer having an opening corresponding to the drain electrode on the thin film transistor and the common wiring;
Forming a common electrode on the planarization layer;
Forming a first protective layer on the common electrode, the first protective layer including a first contact hole exposing the common wiring;
A pixel electrode connected to the drain electrode on the first passivation layer and a connection pattern connected to the common electrode and connected to the common line through the first contact hole,
And forming a plurality of pixel electrodes on the array substrate.

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