KR20170060299A - Liquid Crystal Display Device And Driving Method Of The Same - Google Patents

Abstract

According to another aspect of the present invention, there is provided a liquid crystal display comprising a display panel, a data driving circuit for generating a data voltage to be applied to the data lines of the display panel, And a plurality of DEMUX switches connected to each output channel of the data driving circuit and switched in accordance with the DEMUX control signals, And distributes the data to the plurality of data lines in a time division manner.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal display device,

The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device and a driving method thereof that can reduce the number of output channels of a data driving circuit.

A liquid crystal display device of an active matrix driving type displays a moving picture by using a thin film transistor (hereinafter referred to as "TFT") as a switching element.

The liquid crystal display includes a data driving circuit for converting digital video data into analog data voltages and supplying the data to the data lines of the display panel. Usually, the output channels of the data driving circuit are connected in a 1: 1 manner to the data lines formed on the display panel. However, since the data driver circuit is more expensive than other components, a demultiplexer (deMUX) technique has been proposed to reduce the size and manufacturing cost of the data driver circuit. deMUX technology is a technique of connecting one output channel of a data driving circuit to a plurality of data lines in a time-division manner.

For example, the 1: 3 deMUX technique time-divides one horizontal period defined by gate pulses into three by using the demux control signals DM1, DM2, and DM3 as shown in FIG. The 1: 3 deMUX technique converts the first data voltage DR1 from one output channel CH1 of the data driving circuit D-IC to the demux switch DS during a period in which the first demux control signal DM1 is on, IC from the one output channel CH1 of the data driving circuit D-IC during the period in which the second demux control signal DM2 is turned on after supplying the second data voltage D-1 is supplied to the second data line D2 through the demultiplexer switch DS and then to the one output channel D-IC of the data driving circuit D-IC during the period in which the third demultiplexing control signal DM3 is on. And supplies the third data voltage DB1 from the data line CH1 to the third data line D3 through the demultiplexer switch DS. Since 1: 3 deMUX technology drives three data lines through a single output channel in a time-division manner, the number of output channels can be reduced to 1/3 of the number of data lines, thereby reducing the size and manufacturing cost of the data driving circuit Effective.

The demux switch DS may be implemented as an NMOS type as shown in FIG. 1, or may be implemented as a PMOS type. When the demux switch DS is implemented in the NMOS type (or the PMOS type), the manufacturing process is simplified, but the voltage swing width of the demux control signals DM1, DM2, and DM3 is large and the power consumption is increased . For example, when the voltage range of the data voltage is -5V to 5V, the voltage swing width of the NMOS type demux control signals DM1, DM2, and DM3 is relatively large as about 19V (-7.5V to 11.5V).

In order to reduce the voltage swing width of the D-MUX control signals, a method of implementing the D-MUX switch DS as a CMOS type as shown in FIG. 2 has been proposed. The CMOS-type demultiplexer switch DS is composed of an NMOS-type switch and a PMOS-type switch connected in parallel between one output channel of the data driving circuit (D-IC) and one data line of the display panel. The NMOS type switches are operated according to any one of the NMOS type demux control signals NDM1, NDM2 and NDM3, and the PMOS type switches are operated according to any one of the PMOS type demux control signals PDM1, PDM2 and PDM3. do. The NMOS type switch is selectively turned on according to the NMOS type demux control signals NDM1, NDM2, and NDM3 when the data voltage is negative. On the contrary, the PMOS type switch is selectively turned on according to the PMOS type demux control signals PDM1, PDM2, and PDM3 when the data voltage is positive.

When the Dmux switch DS is implemented in the CMOS type, the voltage swing width of the Dmux control signals NDM1, NDM2, NDM3, PDM1, PDM2, and PDM3 is relatively small and power consumption is reduced. The voltage swing width of the demux control signals NDM1, NDM2, NDM3, PDM1, PDM2, and PDM3 is approximately 11.4 V (-5.7 V to 5.7 V) when the voltage range of the data voltage is -5V to 5V Is reduced compared with the case of implementing the demux switch DS in the NMOS type (or PMOS type).

However, when a demux switch (DS) is implemented as a CMOS type, both the NMOS forming process and the PMOS forming process must be included, resulting in a complicated manufacturing process and a reduced yield.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a liquid crystal display device and a method of driving the same that can simplify the manufacturing process and reduce the voltage swing width of the DEMUX control signals.

According to an aspect of the present invention, there is provided a liquid crystal display device including a display panel, a data driving circuit for generating a data voltage to be applied to data lines of the display panel, A control signal generator for making the voltage levels of the demultiplexer control signals different from each other in accordance with the polarity of the data voltage; and a plurality of switching elements connected to one output channel of the data driving circuit and switched according to the demultiplexing control signals. And a demux switch array for dividing the data voltage into a plurality of data lines by time division, including demux switches.

The voltage levels of the demux control signals change in frame units.

The demux control signals include first demux control signals and second demux control signals that are generated at different voltage levels within the same frame.

The voltage swing width of the first DEMUX control signals is equal to the voltage swing width of the second DEMUX control signals.

 The demultiplexer switch array includes a plurality of first demux switches connected to the odd output channel of the data driving circuit and switched in response to the first demux control signals and a second demux switch connected to the output channel of the data driving circuit, And a plurality of second demux switches that are switched according to the second demux control signals.

Wherein in the odd output channel of the data driving circuit, the positive polarity data voltage is outputted during the odd frame, the negative polarity data voltage is outputted during the odd frame, and in the odd output channel of the data driving circuit, And the first differential control voltage is applied between the first high level and the first low level corresponding to the positive polarity data voltage during the odd frame period, And swings between a second high level and a second low level corresponding to the negative data voltage during the even frame, and the second diplex control signals swing in correspondence to the negative data voltage during the odd frame Swinging between the second high level and the second low level, Swings between the first high level and the first low level corresponding to the positive polarity data voltage, and satisfies the first high level> the second high level> the first low level> the second low level .

The output terminals of some switches among the first demux switches that output the data voltage of the first polarity and the output terminals of some of the second demux switches that output the data voltage of the second polarity cross each other, Lt; / RTI >

The demultiplexer switches are implemented in either NMOS or PMOS.

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display including generating a data voltage to be applied to data lines of a display panel through a data driving circuit, generating a plurality of DEMUX control signals, The method comprising the steps of: varying the voltage levels of the demux control signals according to a polarity of a voltage; switching the demultiplexer through a plurality of demultiplexer switches connected in each output channel of the data driving circuit, Dividing the data voltage into a plurality of data lines by time-sharing.

The present invention simplifies the fabrication process by configuring DIMUX switches in the NMOS type (or PMOS type), and adaptively changes the voltage level of the DEMUX control signals for controlling the DEMUX switches according to the polarity of the data voltage, The voltage swing width of the demux control signals can be reduced to the level of the CMOS type, so that the power consumption can be effectively reduced.

1 illustrates a conventional 1: 3 deMUX technique including an NMOS type demux switch.
2 is a diagram illustrating a conventional 1: 3 deMUX technique including a CMOS-type DEMUX switch.
3 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention.
4 is a view showing a connection structure of an NMOS type demux switch array 15 according to an embodiment of the present invention.
5 shows an example in which the voltage level of the NMOS type DEMUX control signals for driving the demultiplexer switch array 15 of FIG. 4 varies according to the polarity of the data voltage.
FIG. 6 is a diagram showing that the amplitude of the NMOS-type demultiplexing control signals according to the present invention is reduced compared with the amplitude of the conventional NMOS-type demultiplexing control signals. FIG.
7 is a diagram showing a connection structure of a PMOS type demux switch array 15 according to an embodiment of the present invention.
8 is a diagram showing an example in which the voltage level of the PMOS-type DEMUX control signals for driving the demultiplexer switch array 15 of FIG. 7 changes according to the polarity of the data voltage. FIG.
9 is a view showing that the amplitude of PMOS-type demultiplexing control signals according to the present invention is reduced compared to the amplitude of demultiplexing control signals of PMOS type.
10 is a diagram illustrating a comparison between conventional NMOS type demux control signals, conventional CMOS type demux control signals, and NMOS type demux control signals of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

3 shows a liquid crystal display according to an embodiment of the present invention.

3, a liquid crystal display according to an exemplary embodiment of the present invention includes a display panel 10, a data driving circuit 12, a gate driving circuit 13, a timing controller 11, a demux switch array 15, And a control signal generator 16, and the like.

The display panel 10 has two glass substrates and liquid crystal molecules formed therebetween. The display panel 10 is provided with a plurality of liquid crystal cells Clc arranged in a matrix form by the intersection structure of the data lines 18 and the gate lines 19. [

A plurality of data lines 18, a plurality of gate lines 19, TFTs (Thin Film Transistors), pixels of a liquid crystal cell Clc connected to the TFTs, A pixel array 14 including an electrode 1, a common electrode 2 opposed to the pixel electrode 1, and a storage capacitor Cst is formed. The pixel array 14 is provided with a plurality of pixels for image display. Each of the pixels includes an R liquid crystal cell for red implementation, a G liquid crystal cell for green implementation, and a B liquid crystal cell for blue implementation.

On the upper glass substrate of the display panel 10, a black matrix, a color filter, and a common electrode 2 are formed. The common electrode 2 is formed on an upper glass substrate in a vertical electric field driving mode such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. The common electrode 2 is formed of an IPS (In Plane Switching) mode, an FFS (Fringe Field Switching) Is formed on the lower glass substrate together with the pixel electrode 1 in the same horizontal electric field driving system.

On the upper glass substrate and the lower glass substrate of the display panel 10, polarizing plates having optical axes orthogonal to each other are attached, and an alignment film for forming a pretilt angle of liquid crystal on the inner surface in contact with the liquid crystal is formed.

The data driving circuit 12 has output channels having a smaller number than the number of data lines 18 and the output channels are connected to the demux switch array 15 through the source bus lines 17. [ The data driving circuit 12 converts the input digital video data (R, G, B) into analog data voltages under the control of the timing controller 11. [ Then, the data driving circuit 12 supplies the data voltage to the source bus lines 17 through the output channels.

The data driving circuit 12 can control the polarity of the data voltage according to a column-version method in order to prevent deterioration of the liquid crystal. The column inversion scheme is a polarity inversion technique for inverting the polarity of the data voltage output from the same output channel frame by frame and inverting the polarity of the data voltage in the same frame for each output channel.

The demux switch array 15 includes a plurality of demux switches connected to one output channel of the data driving circuit 12 and switched in accordance with the demux control signals DM to time-division the data voltages, Lines 18, respectively. The demux switch array 15 includes a plurality of first demux switches connected to the odd output channels of the data driving circuit 12 and switched in accordance with the first demux control signals DM1a, DM1b and DM1c And a plurality of second demux switches connected to the even output channels of the data driving circuit 12 and switched in accordance with the second demux control signals DM2a, DM2b and DM2c And DS2 in Fig. 7). The demux switch array 15 may include three demux switches connected to each output channel of the data drive circuit 12 according to the 1: 3 deMUX technique (see FIGS. 4 and 7). These DEMUX switches are implemented as either an NMOS type or a PMOS type. Therefore, the manufacturing process of the demux switch array 15 is simplified.

4 and 7) for outputting a data voltage of the first polarity and second demux switches (see FIG. 4 (a) and FIG. 4) for outputting an output terminal of some of the switches among the first demux switches And DS2 in FIG. 7) are connected to the data lines D2, D5, D8 and D11 so that the potentials of the data lines are inverted in units of one data line. At this time, in order to prevent an electrical short between the intersecting data lines, the intersection point may further include an insulating film and a jump line.

The control signal generator 16 generates a plurality of demux control signals DM under the control of the timing controller 11 and controls the polarity of the data voltage to reduce the voltage swing width of the demux control signals DM. (High-peak voltage, low-peak voltage) of the demux control signals DM are different from each other. Since the polarity of the data voltage output through the same output channel is inverted in units of frames, the voltage level of the demux control signals DM applied to the demux switches connected to the output channel is changed frame by frame. The high peak voltage of the demux control signals DM in the n-th (n is an integer) frame in which the positive polarity data voltage is output is output to the demux control signals DM in the (n + 1) (See Figs. 5 and 8). The low peak voltage of the demux control signals DM in the n-th frame in which the positive polarity data voltage is output is the peak of the low peak of the demux control signals DM in the (n + 1) (See Figs. 5 and 8).

The demux control signals DM include first demux control signals DM1a, DM1b and DM1c and second demux control signals DM2a, DM2b and DM2c generated at different voltage levels in the same frame . The first and second demux control signals DM1a, DM1b and DM1c and the second demux control signals DM2a, DM2b and DM2c have different high and low peak voltages, but have the same voltage swing widths.

The gate drive circuit 13 generates scan pulses under the control of the timing controller 11 and supplies the scan pulses to the gate lines 19 in a line sequential manner to generate a horizontal Select a pixel line. The gate drive circuit 13 includes a gate shift register for generating a scan pulse, and a level shifter for shifting the voltage of the scan pulse to a level suitable for driving the liquid crystal cell. The gate shift register of the gate drive circuit 13 can be formed directly in the non-display area of the display panel 10. [ The non-display area is located outside the pixel array 14 in the display panel 10. [

The timing controller 11 refers to the data driver circuit 12 (see FIG. 1) by referring to a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a data enable signal DE and a clock signal DCLK supplied from a system ), The gate drive circuit 13, and the control signal generator 16. [

A source start pulse (SSP), a source shift clock (SSC), and a source output enable signal (Source Output Enable) are input to the data control signal DDC for controlling the data driving circuit 12. [ SOE), a polarity control signal (POL), and the like. The gate control signal GDC for controlling the gate drive circuit 13 includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE ) And the like.

The timing controller 11 aligns the digital video data RGB inputted from the system to the pixel array 14 of the display panel 10 and supplies the aligned data to the data driving circuit 12. The timing controller 11 controls the control signal generator 16 to generate the demux control signals DM in a desired timing.

4 shows a connection structure of an NMOS type demux switch array 15 according to an embodiment of the present invention. FIG. 5 shows an example in which the voltage level of the NMOS-type DEMUX control signals for driving the demultiplexer switch array 15 of FIG. 4 varies according to the polarity of the data voltage. 6 shows that the amplitudes of the NMOS-type DEMUX control signals according to the present invention are smaller than those of the NMOS-type DEMUX control signals.

4, the NMOS-type demultiplexer switch array 15 according to an embodiment of the present invention is connected to the odd output channels CH1 and CH3 of the data driving circuit 12 and outputs first demux control signals A plurality of first demux switches DS1 which are switched according to the first to third demultiplexer DM1a, DM1b and DM1c and a second demultiplexer which is connected to the even output channels CH2 and CH4 of the data driving circuit 12, DM2a, DM2b, and DM2c, respectively.

The odd output channels CH1 and CH3 and the even output channels CH2 and CH4 of the data driving circuit 12 output data voltages of opposite polarities. Specifically, in the odd output channels CH1 and CH3 of the data driving circuit 12, a positive (+) data voltage is output during the odd frame and a negative (-) data voltage is output during the odd frame. On the other hand, in the even-numbered output channels CH2 and CH4 of the data driving circuit 12, the negative (-) data voltage is output during the odd frame and the positive (+) data voltage is output during the odd frame.

In this case, the first demux control signals DM1a, DM1b and DM1c are set to the first high level HL1 and the first low level LL1 ) And swings between the second high level (HL2) and the second low level (LL2) in response to the negative (-) data voltage during the even frame. The second demux control signals DM2a, DM2b and DM2c swing between the second high level HL2 and the second low level LL2 corresponding to the negative (-) data voltage during the odd frame And swings between the first high level (HL1) and the first low level (LL1) corresponding to the positive (+) data voltage during the odd frame. Here, the first high level HL1 is 11.5V, the second high level HL2 is 5.75V, the first low level LL1 is 0V (GND), and the second low level LL2 is -5.75 V < / RTI > Therefore, the first high level HL1> the second high level HL2> the first low level LL1> the second low level LL2.

In other words, the first demux control signals DM1a, DM1b and DM1c are set to 0V (first low peak voltage) in correspondence with the positive polarity data voltages W (+) and B (+) during the odd- (Second low peak voltage) corresponding to the negative (-) data voltages W (-), B (-) during the excellent frame, And swings between 5.75V (second high peak voltage). In contrast, the second demux control signals DM2a, DM2b, and DM2c are set between -5.75V and 5.75V corresponding to the negative (-) data voltages W (-) and B (- And swings between 0V and 11.5V corresponding to the positive polarity data voltages W (+) and B (+) during the beat frame.

On the other hand, in this example, the voltage range of the data voltage is -5V to 5V and the common voltage is 0V (GND). The polarity of the data voltage becomes positive (+) in a range where the data voltage is larger than the common voltage and becomes negative (-) in a small range in which the data voltage is smaller than the common voltage. The display gradation according to the data voltage becomes closer to the white gradation W as the potential difference between the data voltage and the common voltage becomes larger. On the other hand, as the potential difference between the data voltage and the common voltage becomes smaller, the display gradation becomes closer to the black gradation B. Further, a plurality of gray gradations are located between the black gradation (B) and the white gradation (W). 5, black gradation (B) and white gradation (W) are illustrated.

6, the conventional NMOS type DEMUX control signals have a high peak voltage fixed to the gate high voltage (VGH) and a low peak voltage fixed to the gate low voltage (VGL) regardless of the polarity of the data voltage . Thus, the voltage swing width AM2 of the DEMUX control signals was large.

In contrast, the NMOS type demux control signals DM1a, DM1b, DM1c, DM2a, DM2b, and DM2c of the present invention, as in the dotted line pulse waveform of FIG. 6, The first high peak voltage is selected as the gate high voltage VGH and the first low peak voltage is selected as the base voltage GND so as to be swung between the first high level HL1 and the first low level LL1. 6, the NMOS type DEMUX control signals DM1a, DM1b, DM1c, DM2a, DM2b and DM2c of the present invention are applied to the frame in which the negative (-) data voltage Vdata is outputted The second high peak voltage is lower than the gate high voltage VGH to swing between the second high level HL2 and the second low level LL2 and is higher than the positive polarity data voltage V1 Level and the second row peak voltage is selected to be a specific voltage level lower than the negative (-) data voltage (V2, white gradation) and higher than the gate low voltage (VGL). The present invention differs from the conventional NMOS type demux control signals AM2 by setting the voltage levels of the demux control signals DM1a, DM1b, DM1c, DM2a, DM2b and DM2c to be different from each other according to the polarity of the data voltage Vdata. The voltage swing width AM1 of the demux control signals can be significantly reduced.

7 shows a connection structure of a PMOS type demultiplexer switch array 15 according to an embodiment of the present invention. FIG. 8 shows an example in which the voltage level of the PMOS type demux control signals for driving the demultiplexer switch array 15 of FIG. 7 varies according to the polarity of the data voltage. 9 shows that the amplitude of PMOS-type demultiplexing control signals according to the present invention is reduced in comparison with the amplitude of the PMOS-type demultiplexing control signals.

7, a PMOS-type demultiplexer switch array 15 according to an embodiment of the present invention is connected to the odd output channels CH1 and CH3 of the data driving circuit 12 and outputs first demux control signals A plurality of first demux switches DS1 which are switched according to the first to third demultiplexer DM1a, DM1b and DM1c and a second demultiplexer which is connected to the even output channels CH2 and CH4 of the data driving circuit 12, DM2a, DM2b, and DM2c, respectively.

The odd output channels CH1 and CH3 and the even output channels CH2 and CH4 of the data driving circuit 12 output data voltages of opposite polarities. Specifically, in the odd output channels CH1 and CH3 of the data driving circuit 12, a positive (+) data voltage is output during the odd frame and a negative (-) data voltage is output during the odd frame. On the other hand, in the even-numbered output channels CH2 and CH4 of the data driving circuit 12, the negative (-) data voltage is output during the odd frame and the positive (+) data voltage is output during the odd frame.

In this case, the first demux control signals DM1a, DM1b and DM1c correspond to the first high level HL1 and the first low level LL1 ) And swings between the second high level (HL2) and the second low level (LL2) in response to the negative (-) data voltage during the even frame. The second demux control signals DM2a, DM2b and DM2c swing between the second high level HL2 and the second low level LL2 corresponding to the negative (-) data voltage during the odd frame And swings between the first high level (HL1) and the first low level (LL1) corresponding to the positive (+) data voltage during the odd frame. Here, the first high level HL1 is 5.75V, the second high level HL2 is 0V (GND), the first low level LL1 is -5.75V, and the second low level LL2 is - Lt; / RTI > Therefore, the first high level HL1> the second high level HL2> the first low level LL1> the second low level LL2.

In other words, the first demux control signals DM1a, DM1b and DM1c are set to -5.75V (corresponding to the positive polarity data voltages W (+) and B (+)) during the odd- (-) and B (-) corresponding to the negative (-) data voltages W (-) and B (-) during the good frame, ) To 0V (second high peak voltage). In contrast, the second DEMUX control signals DM2a, DM2b and DM2c are swung between -11.5V and 0V corresponding to the negative (-) data voltages W (-) and B (- And swings between -5.75V and 5.75V corresponding to the positive polarity data voltages W (+) and B (+) during the odd frame.

On the other hand, in this example, the voltage range of the data voltage is -5V to 5V and the common voltage is 0V (GND). The polarity of the data voltage becomes positive (+) in a range where the data voltage is larger than the common voltage and becomes negative (-) in a small range in which the data voltage is smaller than the common voltage. The display gradation according to the data voltage becomes closer to the white gradation W as the potential difference between the data voltage and the common voltage becomes larger. On the other hand, as the potential difference between the data voltage and the common voltage becomes smaller, the display gradation becomes closer to the black gradation B. Further, a plurality of gray gradations are located between the black gradation (B) and the white gradation (W). 8 shows black gradation (B) and white gradation (W).

9, the conventional PMOS type demultiplexer control signals have a high peak voltage fixed to the gate high voltage VGH and a low peak voltage fixed to the gate low voltage VGL irrespective of the polarity of the data voltage . Thus, the voltage swing width AM2 of the DEMUX control signals was large.

In contrast, the PMOS type demux control signals DM1a, DM1b, DM1c, DM2a, DM2b, and DM2c of the present invention have the same waveform as the dotted line pulse waveform of FIG. 9 except that the positive polarity data voltage Vdata The first high peak voltage is lower than the gate high voltage VGH and higher than the positive polarity data voltage V1 (white gradation) so as to swing between the first high level HL1 and the first low level LL1, The first low peak voltage is selected as a specific voltage level which is lower than the negative (-) data voltage (V2, white gradation) and higher than the gate low voltage (VGL). The PMOS-type demultiplexing control signals DM1a, DM1b, DM1c, DM2a, DM2b and DM2c of the present invention are generated in the frame in which the negative (-) data voltage Vdata is outputted The second high peak voltage is selected as the base voltage GND and the second low peak voltage is selected as the gate low voltage VGL. The present invention differs from the conventional PMOS type demultiplexing control signals AM2 by setting the voltage levels of the demux control signals DM1a, DM1b, DM1c, DM2a, DM2b and DM2c to be different from each other according to the polarity of the data voltage Vdata. The voltage swing width AM1 of the demux control signals can be significantly reduced.

FIG. 10 shows a comparison between conventional NMOS type DEMUX control signals, conventional CMOS DEMUX control signals, and NMOS type DEMUX control signals of the present invention.

The demux switch is turned on when its gate-source voltage (Vgs) is higher than its threshold voltage. Since the DEMUX control signal is applied to the gate electrode of the DEMUX switch and the data voltage is applied to the source electrode of the DEMUX switch, the voltage swing width of the DEMUX control signal is set to the gate-source voltage Vgs ) Should be set sufficiently higher than its threshold voltage.

Conventionally, the NMOS type DEMUX control signals are designed to have a first swing width between the gate high voltage (VGH) and the gate low voltage (VGL) as shown in FIG. The conventional CMOS type DEMUX control signals are designed to have a second swing width (smaller than the first swing width) between the first voltage (lower than AVDDH and VGH) and the second voltage (higher than AVDDN and VGL) .

The NMOS type DEMUX control signals have a second swing width between a gate high voltage (VGH) and a base voltage (GND) in a frame in which a positive polarity data voltage is output as shown in FIG. 10, A second swing width between the first voltage AVDDH and the second voltage AVDDN in the frame.

In this way, the present invention simplifies the fabrication process of the NMOS type (or PMOS type) demultiplexer switches and adaptively changes the voltage level of the demux control signals for controlling the demux switches according to the polarity of the data voltage , The voltage swing width of the DEMUX control signals can be reduced to the CMOS level, thereby effectively reducing power consumption.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 11: Timing controller
12: data driving circuit 13: gate driving circuit
14: Pixel array 15: DEMUX switch array
16:

Claims (12)

Display panel;
A data driving circuit for generating a data voltage to be applied to the data lines of the display panel;
A control signal generator for generating a plurality of demultiplexing control signals to make the voltage levels of the demux control signals different from each other according to the polarity of the data voltage; And
And a plurality of DEMUX switches connected to one output channel of the data driving circuit and switched in accordance with the DEMUX control signals to divide the data voltages into a plurality of data lines Liquid crystal display device. The method according to claim 1,
Wherein the voltage level of the demux control signals is changed in units of frames. The method according to claim 1,
Wherein the DEMUX control signals include first DEMUX control signals and second DEMUX control signals generated at different voltage levels in the same frame. The method of claim 3,
Wherein the voltage swing width of the first demux control signals is equal to the voltage swing width of the second demux control signals. The method according to claim 1,
The demux switch array includes:
A plurality of first demux switches connected to the odd output channel of the data driving circuit and switched in response to the first demux control signals and a plurality of first demux switches connected to the output channel of the data driving circuit, And a plurality of second DEMUX switches that are switched according to the second DEMUX switches. 6. The method of claim 5,
A positive polarity data voltage is outputted during an odd numbered frame and a negative polarity data voltage is outputted during an odd numbered frame in an odd output channel of the data driving circuit,
The negative data voltage is output during the odd numbered frame and the positive data voltage is output during the odd numbered frame in the odd output channel of the data driving circuit,
Wherein the first demux control signals swing between a first high level and a first low level corresponding to the positive polarity data voltage during the odd numbered frame and a second high level And a second low level,
Wherein the second demux control signals swing between the second high level and the second low level corresponding to the negative polarity data voltage during the odd frame, 1 swings between a high level and the first low level,
The first high level> the second high level> the first low level> the second low level. 6. The method of claim 5,
The output terminals of some of the first demux switches that output the data voltage of the first polarity and the output terminals of some of the second demux switches that output the data voltage of the second polarity cross each other, And is connected to the data lines. The method according to claim 1,
Wherein the demultiplexer switches are implemented by one of an NMOS type and a PMOS type. Generating a data voltage to be applied to the data lines of the display panel through the data driving circuit;
Generating a plurality of demultiplexing control signals, wherein the voltage levels of the demultiplexing control signals are different from each other according to polarities of the data voltages; And
And distributing the data voltage to a plurality of data lines by time-division through a plurality of demultiplexer switches connected to each output channel of the data driving circuit, the data voltage being switched according to the demux control signals. Driving method. 10. The method of claim 9,
Wherein the voltage level of the demux control signals is changed in units of frames. 10. The method of claim 9,
Wherein the DEMUX control signals include first DEMUX control signals and second DEMUX control signals generated at different voltage levels in the same frame. 12. The method of claim 11,
Wherein the voltage swing width of the first demux control signals is equal to the voltage swing width of the second demux control signals.

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