KR20170047463A - Electrostatic protection storage pattern and display device including the same - Google Patents

Abstract

Disclosed are an antistatic storage pattern and a display device including the same capable of preventing insulation breakdown, which is caused by static electricity defects generated by an instantly applied surge during a process, beforehand through designing the antistatic storage pattern between a substrate and a buffer layer. The present invention is provided to design the antistatic storage pattern to be overlapped with a plurality of gate driving wires; to form a storage capacitor between the antistatic storage pattern and the gate driving wires, and between a buffer layer and a gate insulating film which are interposed the antistatic storage pattern and the gate driving wires; and to distribute the instantly applied surge during the process, thereby controlling the static electricity defects. The present invention is provided to form the antistatic storage pattern in a mesh-shaped integrated island structure; and to extend an area overlapped between the antistatic storage pattern and the gate driving wires, thereby maximizing capacity of the storage capacitor.

Description

TECHNICAL FIELD [0001] The present invention relates to an electrostatic discharge (ESD) storage device,

The present invention relates to an antistatic storage pattern capable of improving initial lighting defects and long-term reliability defects due to static electricity, and a display device including the same.

Liquid crystal display devices are less in power consumption, thinner and thinner than cathode-ray tubes, and do not emit harmful electromagnetic waves, and their demand is gradually increasing. In particular, an active matrix liquid crystal display (AM-LCD) using a thin film transistor as a switching device has been widely used because of its excellent resolution and video realization capability.

The liquid crystal display device includes a data driver for supplying a data voltage to a data line on a substrate, a gate driver for supplying a gate voltage to a gate line on the substrate, and a timing controller for controlling the data driver and the gate driver. In general, a liquid crystal display device uses a gate driver and a data driver in the form of an integrated circuit and is attached to a substrate using a TCP (Tape Carrier Package) or COF (Chip on Film) method.

However, in the conventional liquid crystal display device, the number of component elements increases due to attaching the gate driver and the data driver to the substrate by using the TCP or the COP method. As a result, the number of component elements increases, The difficulties are coming.

To solve this problem, recently, a liquid crystal display device of a GIP (gate in panel) structure in which a gate driver is directly embedded in a substrate has been proposed.

In a liquid crystal display device of such a GIP structure, a data driver is formed in a chip form and attached to a substrate using a TCP or COF method, and a plurality of gates and data lines defining liquid crystal cells are formed in a display region of the substrate so as to intersect with each other And a GIP driving element including a plurality of driving transistors is mounted in a non-display area disposed outside the display area.

FIG. 1 is an enlarged plan view showing a part of a GIP driving element formed in a non-display area of a liquid crystal display of a conventional GIP structure.

As shown in FIG. 1, in the conventional liquid crystal display having a GIP structure, in order to appropriately output a signal input to a plurality of gate wirings (not shown) in a non-display area NAA on the substrate 10 A GIP driving element 60 including a thin film transistor of a complementary metal-oxide semiconductor (CMOS) structure having a plurality of driving transistors which is an inverter is incorporated.

A plurality of gate driving wirings 70 are provided in the non-display area NAA on the substrate 10 so as to be electrically connected to the GIP driving elements 60 to supply gate voltages to the plurality of gate wirings.

In recent years, efforts have been actively made to manufacture a slim and compact display device by reducing the bezel size by reducing the area of the non-display area NAA in which no image is implemented, Which inevitably serves as a factor for increasing the density of the GIP driving element 60 and the gate driving wiring 70 in order to reduce the area of the area NAA.

FIG. 2 is a sectional view of the process taken along the line II-II 'of FIG. 1, and will be described in more detail in connection with FIG.

1 and 2, a buffer layer 5, a polycrystalline semiconductor layer 61 and a gate insulating film 62 are sequentially formed on the upper surface 10a of the substrate 10. On the gate insulating film 62, The wiring 70 and the driving gate electrode 63 are laminated.

The buffer layer 5 may be formed of a single layer of silicon oxide (SiOx) or silicon nitride (SiNx), or may have a multi-layer structure in which silicon oxide and silicon nitride are stacked at least once. The buffer layer 5 is formed for the purpose of preventing the alkaline component or the like flowing out from the substrate 10 from being eluted while improving the adhesion with the substrate 10.

A plurality of polycrystalline semiconductor layers 61 may be arranged so as to be spaced apart from each other. The plurality of polycrystalline semiconductor layers 61 may be formed of a combination of an n-type semiconductor layer and a p-type semiconductor layer. At this time, the number of the polycrystalline semiconductor layers 61 may be the same as the number of the n-type semiconductor layers and the number of the p-type semiconductor layers, but the present invention is not limited thereto.

The gate insulating film 62 is formed so as to cover the upper portions of the plurality of polycrystalline semiconductor layers 61. As the gate insulating film 62, silicon oxide (SiOx) or silicon nitride (SiNx) may be used.

A plurality of gate drive wirings 70 are arranged on the gate insulating film 62. The plurality of gate driving wirings 70 are electrically connected to the GIP driving elements 60 to supply gate voltages to the plurality of gate wirings. A plurality of drive gate electrodes 63 are formed on the upper portions of the plurality of polycrystalline semiconductor layers 61, respectively. At this time, the plurality of drive gate electrodes 63 are protruded from the plurality of gate drive wirings 70. Thus, the plurality of drive gate electrodes 63 and the plurality of gate drive wirings 70 are formed of the same material in the same layer.

At this time, the polycrystalline semiconductor layers 61 are formed by depositing amorphous silicon (a-Si) on the buffer layer 5, performing dehydrogenation and crystallization to form a polycrystalline silicon layer, The gate electrode 63 may be formed and then the n < + > -type semiconductor layer and the p-type semiconductor layer may be formed by sequentially performing n + doping and p + doping in the source region and the drain region of the polycrystalline silicon layer by ion implantation .

As described above, in order to reduce the bezel size by reducing the area of the non-display area NAA that does not implement an image and to produce a slim and compact display device, the GIP driving device 60 and / The density of the gate drive wiring 70 is increasing. In particular, in the circuit design of the GIP driving device 60 for reducing the size of the bezel, a dual gate electrode structure in which two driving gate electrodes 63 are arranged in parallel at adjacent positions has been adopted and used. However, Has a structural disadvantage that it is susceptible to surges from the outside due to a decrease in the spacing distance between the two driving gate electrodes 63. [

In order to increase the doping efficiency of the polycrystalline semiconductor layer 61, the thickness of the gate insulating film 62 is designed to be lowered, which decreases the breakdown voltage between the polycrystalline semiconductor layer 61 and the driving gate electrode 63 As a result.

As described above, in the conventional GIP structure liquid crystal display device, the pattern density is increased due to reduction of the area of the non-display area NAA for reducing the bezel size, and the gate insulating film 62 decrease due to the decrease in the breakdown voltage between the polycrystalline semiconductor layer 61 and the driving gate electrode 63, which is vulnerable to surge from the outside and thus acts as a cause of generation of a static electricity failure.

That is, a buffer layer 5, a polycrystalline semiconductor layer 61, a gate insulating film 62, a gate driving wiring 70 and a driving gate electrode 63 are sequentially formed on a substrate 10, When the substrate 10 and the conveying roller R come into contact with each other in the course of being placed on the conveying roller R in order to convey the plurality of polycrystalline semiconductor layers, A static electricity is generated due to a surge that instantaneously flows into the gate electrode 61 and the plurality of drive gate electrodes 63. [

When the substrate 10 is brought into contact with the glass lifting apparatus for lifting the substrate 10 in order to transport the substrate 10 from the process chamber, the glass lifting apparatus acts as a whole to form a plurality of polycrystalline semiconductor layers 61 and the surge that instantaneously flows into the portions of the plurality of drive gate electrodes 63 cause a static electricity failure.

3 is a photograph showing a state in which a static electricity failure occurs.

A surge introduced from the outside into the gate insulating film 62 disposed between the polycrystalline semiconductor layer 61 disposed on the buffer layer 5 and the driving gate electrode 63 as shown in Fig. It can be confirmed that an insulation failure occurs due to a failure.

In order to solve this problem, in recent years, researches have been actively conducted to disperse surges introduced from the outside in order to minimize static electricity defects during the manufacturing process of a liquid crystal display of a GIP structure.

A related prior art is Korean Patent Laid-Open Publication No. 10-2011-0052986 (published May 19, 2011), which discloses a liquid crystal display device and its compensation method.

The present invention relates to an antistatic storage pattern capable of preventing the occurrence of dielectric breakdown due to a static electricity caused by a surge that instantaneously flows during a process through designing an antistatic storage pattern between a substrate and a buffer layer, And a display device including the same.

In addition, the present invention is designed to form an antistatic storage pattern so as to overlap with a plurality of gate drive wirings, thereby forming a storage capacitor between the antistatic storage pattern and the gate drive wiring, the buffer layer interposed therebetween, and the gate insulating film, An object of the present invention is to provide an antistatic storage pattern and a display device including the same that can disperse surges flowing instantaneously to control static electricity failure.

In addition, the present invention does not form an antistatic storage pattern in the lower part of the driving source electrode, the driving drain electrode, and the polycrystalline semiconductor layer, which overlaps with the driving transistor and overlaps with the polycrystalline semiconductor layer. An object of the present invention is to provide an anti-static storage pattern and a display device including the anti-static storage pattern, which can prevent short-circuiting of the anti-static storage pattern and operation defect of the driving transistor.

In addition, the present invention provides an anti-static storage pattern capable of maximizing the capacity of the storage capacitor by enlarging the overlapping area between the anti-static storage pattern and the gate drive wiring by forming the anti-static storage pattern in a mesh- And a display device including the same.

An antistatic storage pattern according to the present invention is disposed in a non-display region of a substrate and is disposed between a substrate and a buffer layer disposed on the substrate so as to overlap with a plurality of gate driving wirings for supplying gate voltages to a plurality of gate wirings do.

At this time, the anti-static storage pattern according to the present invention includes a plurality of horizontal portions arranged along a horizontal direction on a substrate, and a plurality of vertical portions arranged along a vertical direction intersecting the plurality of horizontal portions, By having a mesh structure in which a plurality of vertical portions are integrally connected, the overlapping area with a plurality of gate drive wirings can be maximized.

An antistatic storage pattern and a display device including the same according to the present invention include a GIP driving element formed in a non-display area on a substrate having a display area and a non-display area disposed outside the display area; And a plurality of gate drive wirings for supplying gate voltages to the plurality of gate wirings.

In particular, the antistatic storage pattern according to the present invention and the display device including the same can be manufactured by designing an antistatic storage pattern so as to overlap with a plurality of gate drive wirings, thereby forming an antistatic storage pattern and a gate drive wiring, A storage capacitor is formed between the gate insulating films, and surges introduced instantaneously during the process are dispersed to control the static electricity failure.

At this time, it is preferable that the anti-static storage pattern according to the present invention is disposed on a substrate under the buffer layer and has an island structure electrically isolated.

In particular, a display device according to the present invention includes a plurality of horizontal portions arranged along a horizontal direction on a substrate, and a plurality of vertical portions arranged along a vertical direction intersecting the plurality of horizontal portions, wherein a plurality of It is more preferable that the horizontal portion and the plurality of vertical portions are integrally connected to each other.

Accordingly, the antistatic storage pattern and the display device including the same according to the present invention are designed to have an antistatic storage pattern having a plurality of horizontal portions and a plurality of vertical portions connected integrally to each other, The area can be maximized, which maximizes the capacity of the storage capacitor.

The antistatic storage pattern and the display device including the same according to the present invention may have a dual gate electrode structure in which two driving gate electrodes are arranged in parallel at adjacent positions, The surge introduced during the process can be dispersed by the formation of the storage capacitor, so that the defective static electricity can be prevented beforehand, and it becomes possible to realize the narrow bezel.

In addition, the electrostatic discharge storage pattern and the display device including the same according to the present invention may have a structure in which the driving source electrode, the driving drain electrode, and the polycrystalline semiconductor layer are overlapped with each other, It is possible to prevent a short circuit between the polycrystalline semiconductor layer and the antistatic storage pattern and to prevent the problem of operation failure of the driving transistor by not forming the antistatic storage pattern in the lower part.

The ESD protection pattern and the display device including the ESD protection pattern according to the present invention are designed to prevent ESD from occurring due to a static electricity caused by a surge that instantaneously flows during a process of designing an ESD storage pattern between a substrate and a buffer layer It can be prevented in advance.

In addition, the antistatic storage pattern and the display device including the same according to the present invention design an antistatic storage pattern so as to overlap with a plurality of gate drive wirings, so that the antistatic storage pattern and the gate drive wiring, the buffer layer interposed therebetween, A storage capacitor is formed between the gate insulating films, and surges introduced instantaneously during the process are dispersed to control the static electricity failure.

In addition, the electrostatic discharge storage pattern and the display device including the same according to the present invention may have a structure in which the driving source electrode, the driving drain electrode, and the polycrystalline semiconductor layer are overlapped with each other, It is possible to prevent a short circuit between the polycrystalline semiconductor layer and the antistatic storage pattern and to prevent the problem of operation failure of the driving transistor by not forming the antistatic storage pattern in the lower part.

In addition, the anti-static storage pattern and the display device including the same according to the present invention may have a structure in which the anti-static storage pattern is formed as a mesh-like integral island structure, thereby enlarging the overlapped area between the anti- The capacity can be maximized.

Therefore, the anti-static storage pattern and the display device including the same according to the present invention can realize a narrow bezel, and can improve initial lighting failure and long-term reliability failure due to static electricity.

FIG. 1 is an enlarged plan view of a portion of a GIP driving device formed in a non-display area of a liquid crystal display device of a conventional GIP structure.
FIG. 2 is a sectional view of the process taken along line II-II 'of FIG. 1; FIG.
3 is a photograph showing a state in which a static electricity failure occurs.
4 is a plan view of a display device according to an embodiment of the present invention;
Fig. 5 is an enlarged plan view of a portion A in Fig. 4; Fig.
6 is a cross-sectional view taken along the line VI-VI 'of FIG. 5;
FIG. 7 is a process plan view showing a state in which a gate driving wiring and a driving gate electrode are formed on a gate insulating film in FIG. 5; FIG.
FIG. 8 is a process plan view showing a state where an anti-static storage pattern is formed on a substrate in FIG. 5; FIG.
9 is a sectional view of the process cut along line IX-IX 'of Fig. 7;

The above and other objects, features, and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings, which are not intended to limit the scope of the present invention. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used to denote the same or similar elements.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an anti-static storage pattern according to a preferred embodiment of the present invention and a display device including the same will be described with reference to the accompanying drawings.

4 is a plan view showing a display device according to an embodiment of the present invention.

4, a display device 100 according to an embodiment of the present invention includes a plurality of gate wirings 120 extending in a first direction on a substrate 110, and a plurality of gate wirings 120 extending in a second direction crossing the first direction. And a plurality of switching transistors 135 formed at intersections of the plurality of gate wirings 120 and the plurality of data wirings 130,

At this time, the substrate 110 has a display area AA for realizing an image and a non-display area NAA which is disposed outside the display area AA and does not implement an image. In FIG. 4, the non-display area NAA is disposed at the left edge of the short side of the substrate 110, but the present invention is not limited thereto. That is, the non-display area NAA may be disposed at the short side edge of the substrate 110, or may be disposed at the left and right edges of the substrate 110, and may be disposed at the long side edge of the substrate 110 have.

The plurality of switching transistors 135 are electrically connected to the pixel electrodes 140 disposed in the pixel regions P defined by the plurality of gate wirings 120 and the plurality of data wirings 130, respectively. At this time, the plurality of switching transistors 135 supply data signals from the plurality of data lines 130 to the pixel electrodes 140 in response to the scan signals from the plurality of gate lines 120, ) Of the liquid crystal molecules.

In addition, the display device 100 according to the embodiment of the present invention further includes a data driver 150 and a GIP driver 160.

The data driver 150 is spaced apart from the substrate 110 and supplies a data voltage to the plurality of data lines 130. That is, the data driver 150 converts analog image data from external digital image data into analog image data for one horizontal line every one horizontal period in which a scan signal is supplied to the plurality of gate lines 120, And supplies it to the wiring 130. In other words, the data driver 150 selects a gamma voltage having a predetermined level according to the gradation value of the analog image data, and supplies the selected gamma voltage to the plurality of data lines 130.

The GIP driving element 160 is disposed in the non-display area NAA on the substrate 110. [ The GIP driving device 160 includes a CMOS having a plurality of driving transistors which are inverters for appropriately outputting a signal input to a plurality of gate wirings 120 arranged in a display area AA on the substrate 110 (complementary metal-oxide semiconductor) structure.

This will be described more specifically with reference to the accompanying drawings.

FIG. 5 is an enlarged plan view of part A of FIG. 4, and FIG. 6 is a cross-sectional view taken along the line VI-VI 'of FIG.

5 and 6, a display device 100 according to an embodiment of the present invention includes a GIP driving element 160 disposed in a non-display area NAA on a substrate 110, A plurality of gate drive wirings 170 electrically connected to the plurality of gate drive wirings 160 for supplying a gate voltage to a plurality of gate wirings (120 in FIG. 4), and a plurality of gate drive wirings 170 And further includes a storage pattern 180.

The GIP driving device 160 may include a plurality of gate driving wirings 170 and a plurality of gate driving wirings 170. The GIP driving device 160 may include a plurality of gate driving wirings 170, (complementary metal-oxide semiconductor) structure having a plurality of driving transistors Tr which are inverters.

The plurality of driving transistors Tr includes a plurality of polycrystalline semiconductor layers 161, a gate insulating film 162, a plurality of driving gate electrodes (not shown) arranged on the buffer layer 105 covering the entire upper surface 110a of the substrate 110, An interlayer insulating film 164, a driving source electrode 165, and a driving drain electrode 166.

At this time, the buffer layer 105 may be a single layer of silicon oxide (SiOx) or silicon nitride (SiNx), or may have a multi-layer structure in which silicon oxide and silicon nitride are stacked at least once. The buffer layer 105 is formed for the purpose of improving adhesion with the substrate 110 and blocking the elution of alkaline components and the like flowing out from the substrate 110.

A plurality of polycrystalline semiconductor layers 161 may be arranged to be spaced apart from each other. A plurality of polycrystalline semiconductor layers 161 are formed by depositing amorphous silicon (a-Si) on the buffer layer 105, performing dehydrogenation and crystallization to form a polycrystalline silicon layer, Type semiconductor layer and the p-type semiconductor layer by sequentially performing n + doping and p + doping in the source region and the drain region of the polycrystalline silicon layer by ion implantation. At this time, the number of the polycrystalline semiconductor layers 161 may be equal to the number of the n-type semiconductor layers and the number of the p-type semiconductor layers, but is not limited thereto.

A gate insulating film 162 is disposed on the entire upper surface of the buffer layer 105 to cover the plurality of polycrystalline semiconductor layers 161. As the gate insulating film 162, silicon oxide (SiOx) or silicon nitride (SiNx) may be used.

A plurality of driving gate electrodes 163 are disposed on the gate insulating film 162 and are disposed on top of the plurality of polycrystalline semiconductor layers 161. The plurality of drive gate electrodes 163 protrude from the plurality of gate drive wirings 170. Accordingly, the plurality of drive gate electrodes 163 and the plurality of gate drive wirings 170 are formed of the same material in the same layer.

An interlayer insulating film 164 is disposed on the plurality of gate driving wirings 170 and the plurality of driving gate electrodes 163. [ At this time, the interlayer insulating film 164 may be formed of silicon oxide (SiOx) or silicon nitride (SiNx).

The plurality of drive source electrodes 165 and the plurality of drive drain electrodes 166 are disposed on the interlayer insulating film 164 and include a plurality of contact holes CH penetrating the interlayer insulating film 164 and the gate insulating film 162 To the source region and the drain region of the polycrystalline semiconductor layer 161, respectively. At this time, the plurality of driving gate electrodes 163 may have a dual gate electrode structure in which two driving gate electrodes are arranged in parallel at adjacent positions.

Particularly, the anti-static storage pattern 180 is disposed between the substrate 110 and the buffer layer 105 and overlaps with the plurality of gate drive wirings 170. When the antistatic storage pattern 180 and the plurality of gate drive wirings 170 are designed to overlap with each other, the antistatic storage pattern 180 and the plurality of gate drive wirings 170, A storage capacitor 190 is formed between the buffer layer 105 and the gate insulating film 162 interposed between the gate insulating layer 180 and the plurality of gate drive wirings 170 to disperse a surge flowing instantaneously during the process So that it is possible to prevent an insulation breakdown failure due to a sudden static charge.

This will be described more specifically with reference to the accompanying drawings.

FIG. 7 is a process plan view showing a state in which a gate driving wiring and a driving gate electrode are formed on a gate insulating film in FIG. 5, FIG. 8 is a process plan view showing a state in which an antistatic storage pattern is formed on a substrate in FIG. 9 is a process sectional view taken along line IX-IX 'of Fig. At this time, FIG. 9 also shows the antistatic storage pattern of FIG.

7 through 9, the anti-static storage pattern 180 is disposed between the substrate 110 and the buffer layer 105. That is, the anti-static storage pattern 180 is disposed on the substrate 110 under the buffer layer 105 and has an island structure that is electrically isolated. Although not shown in the drawing, light emitted from a backlight unit (not shown) is applied to the active region (AA in FIG. 4) of the substrate 110 when the display device 100 of FIG. 4 is a liquid crystal display device, An L / S (light shield) pattern (not shown) may be formed to shield incident light from the active layer 135 of FIG. At this time, the anti-static storage pattern 180 may be formed of the same material in the same layer as the L / S pattern. As the material of the antistatic storage pattern 180, at least one selected from the group consisting of Mo, Ti, Al, Au, Ag, Cu, Ni and Cr may be used and may be a single layer or a multilayer structure .

In particular, the antistatic storage pattern 180 is formed to overlap the plurality of gate drive wirings 170. As a result, the plurality of gate drive wirings 170 disposed on the top of the anti-static storage pattern 180 as the first electrode and the plurality of gate drive wirings 170 overlapped with the anti-static storage pattern 180 as the second electrode, A storage capacitor 190 having a buffer layer 105 and a gate insulating film 162 interposed between a plurality of gate drive lines 170 and a plurality of gate drive lines 170 is formed.

When the antistatic storage pattern 180 and the plurality of gate drive wirings 170 are designed to overlap with each other, the antistatic storage pattern 180 and the plurality of gate drive wirings 170, A storage capacitor 190 is formed between the buffer layer 105 and the gate insulating film 162 interposed between the gate insulating layer 180 and the plurality of gate drive wirings 170 to disperse a surge flowing instantaneously during the process It is possible to prevent the occurrence of an insulation breakdown failure due to the introduction of static electricity in advance due to the structural advantage that can be made possible.

Therefore, in the display device according to the embodiment of the present invention, the density of the pattern is increased by designing the area of the non-display area NAA to be reduced, and the thickness of the gate insulating film 162 is increased to 500 It is possible to overlay the antistatic storage pattern 180 and the plurality of gate drive wirings 170 by overlapping design even if the withstand voltage between the polycrystalline semiconductor layer 161 and the drive gate electrode 163 decreases due to the downward designing of the anti- The storage capacitor 190 formed by the first and the second diffusion layers disperses the surge introduced during the process, so that it is possible to prevent the occurrence of the defective electrostatic discharge.

8, the anti-static storage pattern 180 includes a plurality of horizontal portions 180a arranged along the horizontal direction on the substrate 110, and a plurality of horizontal portions 180a extending in the vertical direction intersecting the plurality of horizontal portions 180a And a plurality of vertical portions 180b arranged along the vertical direction. At this time, the plurality of horizontal portions 180a of the anti-static storage pattern 180 and the plurality of vertical portions 180b of the anti-static storage pattern 180 may be designed to be separated from each other, The capacity of the capacitor 190 is limited.

Therefore, in order to maximize the capacity of the storage capacitor 190, it is preferable that the anti-static storage pattern 180 has a structure in which a plurality of horizontal portions 180a and a plurality of vertical portions 180b are integrally connected. It is preferable to design the storage pattern 180 so that the line width of the storage pattern 180 is extended to secure a large area overlapping the plurality of gate drive wirings 170. Particularly, it is preferable that the antistatic storage pattern 180 is formed to have a mesh structure so as not to overlap with the polycrystalline semiconductor layer 161 and the driving gate electrode 163 of the plurality of driving transistors Tr desirable. When the antistatic storage pattern 180 is designed with a net structure in which a plurality of the horizontal portions 180a and the plurality of vertical portions 180b are integrally connected as described above, The capacity of the storage capacitor 190 can be improved and the surge introduced during the process can be effectively dispersed.

Referring again to FIGS. 7 to 9, the antistatic storage pattern 180 is formed to bypass the lower portion of the plurality of driving transistors Tr overlapped with the polycrystalline semiconductor layer 161 and the driving gate electrode 163. That is, the antistatic storage pattern 180 is designed to be avoided by being bypassed so as not to be formed in the lower portion overlapping the driving transistor Tr, particularly, the polycrystalline semiconductor layer 161 of the driving transistor Tr and the driving gate electrode 163 desirable.

In the case where the antistatic story story pattern 180 is formed at the lower portion overlapping the driving transistor Tr, particularly the polycrystalline semiconductor layer 161, a plurality of Due to the exposure of the polycrystalline semiconductor layer 161 and the buffer layer 105 under the polycrystalline semiconductor layer 161 and the antistatic storage pattern 180 by the overexposure in the process of forming the contact hole CH of the polycrystalline semiconductor layer 161, The contact between the source electrode 162 and the driving drain electrode 164 may cause a short circuit between the polycrystalline semiconductor layer 161 and the antistatic storage pattern 180. When the antistatic storage pattern 180 is formed under the drive transistor Tr, particularly the polycrystalline semiconductor layer 161 and the drive gate electrode 163, the antistatic storage pattern 180 and the polycrystalline semiconductor layer 161, The operation of the driving transistor Tr may be defective due to the cap between the first and second transistors 161 and 161.

9, an anti-static storage pattern 180 having an island structure is formed on the upper surface 110a of the substrate 110, and an upper surface 110a of the substrate 110 on which the anti-static storage pattern 180 is formed The buffer layer 105 is formed.

A polycrystalline semiconductor layer 161 and a gate insulating film 162 are sequentially formed on the buffer layer 105 and a gate driving wiring 170 and a driving gate electrode 163 are stacked on the gate insulating film 162.

At this time, the plurality of gate driving wirings 170 are electrically connected to the GIP driving elements (160 in Fig. 5) to supply gate voltages to a plurality of gate wirings (120 in Fig. 4). The plurality of drive gate electrodes 163 are arranged on the upper portion of the plurality of polycrystalline semiconductor layers 161, respectively. At this time, the plurality of drive gate electrodes 163 protrude from the plurality of gate drive wirings 170. Accordingly, the plurality of drive gate electrodes 163 and the plurality of gate drive wirings 170 are formed of the same material in the same layer.

At this time, in the present invention, the density of the pattern is increased by designing the area of the non-display area NAA to be reduced, and the thickness of the gate insulating film 162 is reduced to 500 to 1300 Å in order to improve the doping efficiency The storage capacitor 190 (not shown) formed by overlapping designing the antistatic storage pattern 180 and the plurality of gate drive wirings 170 even if the withstand voltage between the polycrystalline semiconductor layer 161 and the drive gate electrode 163 decreases, ) Disperses the surge which flows during the process, it is possible to prevent the occurrence of the defective electrostatic discharge.

That is, in the present invention, an anti-static storage pattern 180, a buffer layer 105, a polycrystalline semiconductor layer 161, a gate insulating film 162, a gate driving wiring 170, and a driving gate electrode 163 are formed on a substrate 110, The substrate 110 and the transporting rollers R are brought into contact with each other in the process of placing the substrate 110 on the transporting rollers R for transporting the substrate 110 from the process chamber, The storage capacitor 190 formed by overlapping designing between the antistatic storage pattern 180 and the plurality of gate drive wirings 170 disperses a surge introduced during the process, It is possible to prevent the occurrence of a defective electrostatic discharge in advance.

Although the substrate 110 is in contact with a glass lifting device (not shown) for lifting the substrate 110 to transport the substrate 110 from the process chamber so that the glass lifting device acts as a whole, Since the storage capacitor 190 formed by superimposing the pattern 180 and the plurality of gate drive wirings 170 disperses a surge introduced during the process, it is not known that a static electricity failure occurs .

As described above, according to the present invention, the anti-static storage pattern and the display device including the anti-static storage pattern and the gate driving interconnection are formed by designing the anti-static storage pattern to overlap the plurality of gate driving interconnection lines, It is possible to form a storage capacitor between the buffer layer and the gate insulating film interposed therebetween, thereby dispersing a surge that flows instantaneously during the process, thereby controlling the static electricity failure.

In addition, the electrostatic discharge storage pattern and the display device including the same according to an embodiment of the present invention may include a driving source electrode, a driving drain electrode, and a driving gate electrode, It is possible to prevent a short circuit between the polycrystalline semiconductor layer and the antistatic storage pattern and to prevent the problem of operation failure of the driving transistor in advance.

In addition, the anti-static storage pattern and the display device including the same according to the embodiment of the present invention can form the integrated anti-static structure of the anti-static storage pattern in a mesh shape to enlarge the overlapped area between the anti- The capacity of the storage capacitor can be maximized.

In the present invention, a liquid crystal display device having a GIP structure for controlling driving of liquid crystal molecules by a plurality of switching transistors and pixel electrodes has been described as an example, but the present invention is not limited to this, and a plurality of switching transistors and a plurality of pixels It is obvious that the present invention can be similarly applied to an organic light emitting display having a GIP structure for controlling the driving of the organic light emitting layer by the driving transistor and the pixel electrode.

While the present invention has been particularly shown and described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It is therefore to be understood that such changes and modifications are intended to be included within the scope of the present invention unless they depart from the scope of the present invention.

100: display device 110: substrate
120: gate wiring 130: data wiring
135: switching transistor 140: pixel electrode
150: Data driver 160: GIP driving element
170: Gate drive wiring 180: Antistatic storage pattern
AA: display area NAA: non-display area
P: pixel area

Claims (11)

An antistatic storage pattern disposed in a non-display area of the substrate and interposed between the substrate and a buffer layer disposed on the substrate, the storage layer being superimposed on a plurality of gate drive wirings for supplying a gate voltage to a plurality of gate wirings.
The method according to claim 1,
The antistatic storage pattern
A plurality of horizontal portions arranged along the horizontal direction on the substrate,
And a plurality of vertical portions arranged along a vertical direction intersecting the plurality of horizontal portions,
And a plurality of horizontal portions and a plurality of vertical portions integrally connected to each other.
A substrate having a display region and a non-display region disposed outside the display region;
A buffer layer disposed on the substrate;
A plurality of switching transistors arranged in a display region on the substrate and arranged at intersections of a plurality of gate wirings and a plurality of data wirings; a plurality of pixel electrodes respectively connected to the plurality of switching transistors;
A data driver arranged to be spaced apart from the substrate and supplying a data voltage to the plurality of data lines;
A GIP driving element arranged in a non-display area on the substrate;
A plurality of gate driving wirings electrically connected to the GIP driving device and supplying a gate voltage to the plurality of gate wirings; And
An antistatic storage pattern disposed between the substrate and the buffer layer and arranged to overlap the plurality of gate drive wirings;
.
The method of claim 3,
The antistatic storage pattern
And an island structure disposed on the substrate below the buffer layer and electrically isolated.
The method of claim 3,
The antistatic storage pattern
A plurality of horizontal portions arranged along the horizontal direction on the substrate,
And a plurality of vertical portions arranged along a vertical direction intersecting the plurality of horizontal portions,
And a plurality of horizontal portions and a plurality of vertical portions integrally connected to each other.
The method of claim 3,
The GIP driving element
A display device comprising a thin film transistor of a CMOS structure having a plurality of driving transistors.
The method according to claim 6,
The plurality of drive transistors
A plurality of polycrystalline semiconductor layers disposed on the buffer layer,
A gate insulating film covering the plurality of polycrystalline semiconductor layers,
A plurality of driving gate electrodes which are disposed on the gate insulating film and which are disposed on top of the plurality of polycrystalline semiconductor layers and protruded from the plurality of gate driving wirings;
An interlayer insulating film disposed on the plurality of gate driving wirings and the plurality of driving gate electrodes,
And a plurality of driving source electrodes and a plurality of driving drain electrodes arranged on the interlayer insulating film and connected to the plurality of polycrystalline semiconductor layers.
8. The method of claim 7,
The plurality of drive gate electrodes
Wherein the two drive gate electrodes are arranged in parallel at adjacent positions.
8. The method of claim 7,
The antistatic storage pattern
And a lower portion overlapping the polycrystalline semiconductor layer and the driving gate electrode of the driving transistor.
8. The method of claim 7,
Wherein the antistatic storage pattern is a first electrode,
The plurality of gate drive wirings disposed on top of the antistatic storage pattern as a second electrode,
And a storage capacitor having the buffer layer and the gate insulating film interposed between the antistatic storage pattern and the plurality of gate drive wirings as a dielectric layer.
8. The method of claim 7,
The gate insulating film
And a thickness of 500 to 1300 ANGSTROM.

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