KR20160080907A - Solid state drive(ssd) including flash memory controller of multiple, and the flash memory controller for perfroming decompression method - Google Patents

Abstract

To a decompression method performed by a flash memory controller and a solid state drive including a plurality of flash memory controllers.
The decompression method performed by the controller is to receive page information related to data stored in the flash memory, distinguish logical pages to be subjected to a read request among the physical pages, and transmit the separated logical pages to the device controller.

Description

TECHNICAL FIELD [0001] The present invention relates to a solid state drive including a plurality of flash memory controllers, and a decompression method performed by the flash memory controller. More particularly, the present invention relates to a solid state drive including a plurality of flash memory controllers,

The following description relates to a decompression method performed by a solid state drive including a plurality of flash memory controllers and a flash memory controller, and a method of performing a decompression function of a logical page using a plurality of flash memory controllers.

Solid state drives (SSD) are general NAND flash based storage devices, and have a multi-channel structure for the performance of a storage device. As a result, the solid state drive improves the read / write performance of the storage device by making the read / write on several channels at the same time.

In recent years, compression-based solid state drives using compression algorithms in storage devices have been attracting attention for improving the lifetime and performance of storage devices. In other words, in a compression-based solid state drive, compression and decompression processes are performed by a specific CPU or compressed H / W.

Specifically, unlike a write request that compresses data arriving sequentially from a host, a read request in a compression-based solid state drive leads to simultaneous read and decompression of data requested in multiple channels, A bottleneck phenomenon occurs due to the decompression process being processed. That is, the read request in the compression-based solid state drive has a problem that the performance is reduced because the decompression process is not processed at the same time even if the page reading of the requested data from several channels is completed at the same time.

As a result, a compression-based solid state drive can not utilize the advantages of parallelism through multiple channels to the maximum, and a bottleneck occurs at the decompression stage for reading, thereby degrading the read / write performance to the characteristic configuration of the storage device .

Therefore, there is a need for a method for solving the bottleneck phenomenon while maximizing the advantages of parallelism through multiple channels.

 The present invention can provide a decompression method for decompressing through a flash memory controller connected to each channel in response to a read request related to data requested from a host.

The decompression method performed by the flash memory controller according to an embodiment includes receiving page information related to the data in response to a read request of data stored in a flash memory from a device controller; Accessing the physical page using an address of a physical page included in the received page information; Identifying a logical page to be a target of the read request in the accessed physical page; And transferring the logical page to the page device controller in consideration of compression of the divided logical page, wherein the flash memory controller is arranged for each of a plurality of channels, and each of the plurality of channels An array of flash memories can be assigned to the flash memory.

According to one embodiment, the accessing step may access the physical page including the compressed data using the address of the physical page to be read by the flash memory controller.

The compressed data according to an embodiment may be compressed by the compression function built in the flash memory controller and stored in the physical page.

The step of classifying according to an embodiment may distinguish the logical page from the physical page corresponding to the index of the logical page included in the page information.

According to an embodiment of the present invention, it is possible to determine whether the logical page is compressed based on a flag indicating whether or not the logical page included in the page information is compressed.

According to one embodiment, when the divided page is compressed, the transferring step decompresses the compressed logical page using the decompression function built in the flash memory controller, and outputs the decompressed logical page to the read buffer of the device controller .

According to an exemplary embodiment, when the divided page is not compressed, the transmitting logical page may be transferred to the read buffer of the page device controller.

The device controller according to an exemplary embodiment may combine the decompressed logical pages received from the flash memory controller and another flash memory controller to transfer the combined data of the logical pages to the host.

The flash memory controller according to an embodiment receives page information related to the data in response to a read request of data stored in the flash memory from the device controller, and uses the address of the physical page included in the received page information, Accesses the page, identifies the logical page to be subjected to the read request in the accessed physical page, decompresses the separated logical page, and delivers the decompressed logical page to the device controller.

The flash memory controller according to the embodiment receives the address of the physical page to be read from the device controller, the index of the logical page to be the target of the read request among the physical pages, and the flag indicating whether the logical page included in the page information is compressed can do.

According to one embodiment, a solid state drive includes a plurality of flash memory arrays corresponding to a plurality of channels; And a plurality of flash memory controllers connected to the plurality of flash memory arrays, wherein each of the plurality of flash memory controllers includes a plurality of flash memory controllers, And transfer the logical page to the read buffer of the page device controller in consideration of whether or not the separated logical page is compressed.

Each of the plurality of flash memory controllers according to an embodiment accesses a physical page including compressed data through an address of a physical page to be read by the flash memory controller, The logical page can be distinguished by using the index of the logical page.

Each of the plurality of flash memory controllers according to an embodiment may consider decompressing the logical page based on a flag indicating whether or not the logical page included in the page information related to the data is compressed.

Each of the plurality of flash memory controllers according to an embodiment may decompress the compressed logical page using the decompression function embedded in the flash memory controller when the divided page is compressed.

 According to an embodiment of the present invention, a decompression method of a flash memory controller can solve a bottleneck caused by hardware by decompressing a flash memory controller connected to each channel in response to a read request.

According to an embodiment of the present invention, a decompression method of a flash memory controller is decompressed through a flash memory controller connected to each channel in response to a read request, thereby maximizing the advantages of parallelization through multiple channels. Performance can be improved.

1 is a diagram illustrating a host and a solid state drive according to one embodiment.
2 is a detailed block diagram of a solid state drive including a plurality of flash memory controllers according to an exemplary embodiment of the present invention.
3 is a diagram illustrating an operation of a flash memory controller according to an embodiment.
4 is a diagram illustrating a structure of a flash memory controller according to an embodiment of the present invention.
5 is a diagram for explaining an operation of transferring data requested by a solid state drive to a host based on the operation of a flash memory controller according to an embodiment.
6 is a flowchart illustrating a decompression method performed by the flash memory controller according to an exemplary embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a host and a solid state drive according to one embodiment.

Referring to FIG. 1, the host 101 may transmit a read request to read data stored in the flash memory of the solid state drive 102. Here, the host 101 is an area where a program such as an application is executed, and can read data from the solid state drive 102. For example, the host 101 may refer to a system that manages files related to programs by a file system, an operation system, or the like.

Then, the solid state drive 102 can transmit data corresponding to the read request transmitted from the host 101 to the host 101. [ Here, the solid state drive 102 may be a storage device having a multi-channel structure based on NAND flash. For example, the solid state drive 102 may refer to a large-capacity storage device using a high-speed semiconductor memory such as a NAND flash as a storage medium.

At this time, the solid state drive 102 may include a device controller 103 and a flash memory controller 104 to transfer data to the host 101. Specifically, the device controller 103 can manage the input / output of data stored in the flash memory. For example, the device controller 103 may be a Flash Translation Layer (FTL) for performing a page mapping operation between a logical page and a physical page.

The device controller 103 may generate page information related to data stored in the flash memory that the host 101 wants to read in response to the read request transmitted from the host 101. [ In other words, the device controller 103 can receive a logical block address (LBA) related to data to be read in response to a read request from the host 101. [ The logical block address is information for identifying the address of the requested data and converted into a logical page number (LPN), which may be information for referring to a page mapping table (PMT).

The device controller 103 can generate page information based on the logical block number transmitted from the host 101 through the page mapping table. That is, the device controller 103 can generate page information including an address of a physical page to be read by the device controller 103, an index of the logical page, and a flag indicating whether or not the logical page is compressed.

The device controller 103 can transmit the generated page information to the flash memory controller 104. [ The flash memory controller 104 is disposed for each of a plurality of channels, and an array of flash memory may be allocated for each of the plurality of channels. The structure of the flash memory controller 104 will be described in detail with reference to FIG.

The flash memory controller 104 can access the physical page using the address of the physical page received from the device controller 103. [ Then, the flash memory controller 104 can identify the logical page to be the target of the read request in the accessed physical page. The flash memory controller 104 may transfer the logical page to the device controller in consideration of whether or not the logical page is compressed.

Here, if the divided page is compressed, the flash memory controller 104 decompresses the compressed logical page using the decompression function built in the flash memory controller, and then outputs the decompressed logical page to the read buffer of the device controller . In addition, if the divided page is not compressed, the flash memory controller 104 can transfer the separated logical page to the read buffer of the device controller.

The device controller 103 may then combine the decompressed logical pages received from the flash memory controller and another flash memory controller. Then, the solid state drive 102 can transfer the data of the logical pages combined in the device controller 103 to the host.

By using the flash memory controller 104 disposed in each of the plurality of channels, the solid state drive 102 can improve the speed for reading data as it processes data in response to a read request. In addition, the solid state drive 102 may use the flash memory controller 104 disposed in each of the plurality of channels to decompress a logical page for a read request for a plurality of channels, The problem of the phenomenon can be solved.

2 is a detailed block diagram of a solid state drive including a plurality of flash memory controllers according to an exemplary embodiment of the present invention.

2, the solid state drive 201 may include a device controller 202 and a flash memory controller 203.

The device controller 202 may generate page information for transfer to the flash memory controller 203 in response to a read request for data requested from the host. Here, the page information can provide the flash memory controller 203 with information for more easily identifying the logical page to be subjected to the read request. Then, the device controller 202 can transmit the generated page information to the flash memory controller 203. [

Here, the device controller 202 can transfer page information to one flash memory controller or a plurality of flash memory controllers based on the position of a physical page where data requested to be read from the host is stored.

Specifically, the data requested from the host can be divided and stored in a plurality of physical pages according to the size or type of data. In other words, the data requested from the host may be allocated a plurality of physical tables to store data. For example, the logical block addresses "0 to 64" requested from the host are converted into logical page numbers " 0 to 8 ", and the physical page numbers "1 & "512", "1024", and "2048" may be allocated. One or more compressed data or uncompressed data corresponding to the logical page number may be stored corresponding to the assigned physical page number.

The data requested to be read from the host may be divided and stored in a plurality of physical pages according to the above-described data storage method. Thus, the host can communicate a read request for data stored in a plurality of channels to the solid state drive 201. [

In response to this, the device controller 202 of the solid state drive 201 can identify a plurality of physical pages in which read requested data is stored by using the page mapping table, and the page information corresponding to each identified physical page Lt; / RTI > The device controller 202 may transmit page information corresponding to the channel including the identified physical page to the flash memory controller connected to the channel.

Then, the flash memory controller 203 connected to each channel can distinguish the logical page to be the target of the read request from the physical page based on the transmitted page information. Specifically, the flash memory controller 203 is arranged for each of a plurality of channels, and an array 204 of flash memory can be allocated for each of the plurality of channels. The plurality of channels includes an array 204 of a plurality of flash memories for storing valid data for each of them, and the flash memory of each channel may include a physical page unit. A physical page may include a logical page stored on a page basis.

As a result, the solid state drive 201 may include a plurality of channels to improve performance associated with writing or reading of the storage device. The flash memory controller 203 may be disposed in correspondence with each of the plurality of channels included in the solid state drive 201 on a one-to-one basis. For example, the flash memory controller 203 may exist in six so that the flash memory controller 203 can be arranged in a one-to-one correspondence with the six channels included in the solid state drive 201.

The flash memory controller 203 can access the physical page to be read by using the address of the physical page included in the page information. In other words, the address of the physical page may be an address for accessing the flash memory as a physical page corresponding to the physical page number actually stored in the flash memory.

Thereafter, the flash memory controller 203 can use the index of the logical page to distinguish the logical page to be the target of the read request from the accessed physical page. The index of the logical page may be information for identifying a logical page targeted for a read request among a plurality of logical pages stored in the address of the physical page. The flash memory controller 203 can distinguish the logical page from the physical page. At this time, the logical page may indicate a compressed state or an uncompressed state depending on the situation. The compression of the logical page may be identified through a flag included in the page information.

That is, the flash memory controller 203 identifies the logical page to be the target of the read request based on the page information including the address of the physical page, the index of the logical page, and the flag transmitted from the device controller 202, It is possible to judge whether or not the compression is performed. As a result, the page information can be information for quickly and accurately detecting the logical page in distinguishing the logical page through the flash memory controller 203. In addition, the flash memory controller 203 can perform decompression according to whether the logical page is compressed or not.

In other words, the flash memory controller 203 can identify the logical page in the physical page included in each channel corresponding to the read request transmitted from the host, and perform the decompression function according to whether or not the separated logical page is compressed . Accordingly, the flash memory controller 203 can solve the bottleneck occurring in the compression-based solid state drive and improve the performance of the read / write function through parallelization of the channel.

In addition, the flash memory controller 203 can decompress the logical page in the physical page, considering the compression, and adaptively decompress the logical page according to the situation, so that the flash memory controller 203 can process the data more quickly.

3 is a diagram illustrating an operation of a flash memory controller according to an embodiment.

Referring to FIG. 3, the device controller can generate page information using the page mapping table as described above with reference to FIG. Specifically, the page mapping table may be expressed as shown in Table 1, and may include information about physical pages allocated to logical pages.

LPN FLAG IDX PPN_address 100 0 One 64 (ch: 0, chip: 0, blk: 1, page: 0) 101 0 2 64 (ch: 0, chip: 0, blk: 1, page: 0) 102 0 3 64 (ch: 0, chip: 0, blk: 1, page: 0) 103 One One 8192 (ch: 1, chip: 0, blk: 1, page: 0)

Specifically, referring to Table 1, the page mapping table can indicate information about a physical page allocated to a logical page using a logical page number and a physical page address. In other words, the page mapping table may be a table that maps the relationship with the physical page address allocated to store the logical page based on each logical page number. Also, the physical page address is an address for identifying the physical pages included in the solid state drive, which can be converted by the device controller into an address of a physical page managed by each flash memory controller.

The device controller can generate the page information in order to more accurately distinguish the logical page from the physical page in which the compressed data is stored according to the read request. For example, assuming that a read request for a logical page number 100 has been transmitted, the device controller determines, based on the page mapping table corresponding to the logical page number 100, the address 64 of the physical page, the index (1) and the flag (0).

The flash memory controller 301 can receive page information including the address of the physical page, the index of the logical page, and the flag from the device controller. The flash memory controller 301 can access the physical page using the address 302 of the physical page included in the received page information. That is, the flash memory controller 301 can access the physical page where the actual data is stored.

Thereafter, the flash memory controller 301 can identify the logical page to be the target of the read request among the logical pages sequentially stored in the accessed physical page. Here, the flash memory controller 301 can decompress the logical page through the function of dividing the logical page identified by the index of the logical page in the physical page into the flash memory controller 301 and decompressing it by the built-in decompression function. The flash memory controller 301 can identify the start position of the logical page stored in the physical page by using the index of the logical page. Then, the flash memory controller 301 can check whether or not the logical page classified through the index of the logical page is compressed.

The flash memory controller 301 can decompress the separated logical page and transfer it to the read buffer of the device controller.

The flash memory controller 301 can compress data through a built-in compression function corresponding to a write request requested from the host, as well as a function of decompressing the compressed logical page. The flash memory controller 301 can store the compressed data in the physical page through the built-in compression function. At this time, the flash memory controller 301 may sequentially compress and store a plurality of data requested to be written from the host.

4 is a diagram illustrating a structure of a flash memory controller according to an embodiment of the present invention.

Referring to FIG. 4, the solid state drive proposed in the present invention may include a host interface controller, CPUs, an on-chip SRAM, a DRAM controller, and a flash memory controller 401 connected to an array of flash memory have. The solid state drive may execute firmware that performs a page mapping operation in cooperation with the flash memory controller 401. Here, the firmware may mean the device controller described above.

The flash memory controller 401 may include components of a DMA, an embedded processor, a scratchpad SRAM, a bus bridge, a decompression processor, and a NAND flash interface.

The scratchpad SRAM can temporarily store data according to the write request from the host. In other words, the scratchpad SRAM may be the location where the raw data is stored before processing begins.

The embedded processor can perform the function of distinguishing the logical page from the physical page through the index information transmitted from the device controller.

The decompression processor can perform decompression of the logical page identified in the physical page in response to the read request from the host. In other words, the decompression processor can perform decompression corresponding to the compressed logical page corresponding to the read request in the physical page accessed by the address of the physical page.

5 is a diagram for explaining an operation of transferring data requested by a solid state drive to a host based on the operation of a flash memory controller according to an embodiment.

Referring to FIG. 5, the flash memory controller 501 can identify a logical page from a channel 502 connected to the flash memory controller 501. The flash memory controller 501 can identify the logical page to be the target of the read request in the physical page using the page information. The flash memory controller 501 can perform a decompression operation according to whether or not the separated logical page is compressed.

The flash memory controller 501 can decompress the compressed logical page using the decompression function embedded in the flash memory controller when the separated page is compressed. The flash memory controller 501 can then deliver the decompressed logical page to the read buffer of the device controller 504. [

Here, the device controller 504 can receive a result of decompression of the logical page separated from the channel connected to the flash memory controller 501 and another flash memory controller, respectively.

The solid state drive 504 can then check whether the host 505 has received all the logical pages for the data requested to be read from the flash memory controller 501 and another flash memory controller. When all the logical pages for the data requested to be read from the host 505 are received, the device controller 504 can combine the logical pages stored in the read buffer and deliver the combined data to the host 505. [

6 is a flowchart illustrating a decompression method performed by the flash memory controller according to an exemplary embodiment.

In step 601, the flash memory controller may receive page information related to the data in response to a read request of data stored in the flash memory from the device controller. The flash memory controller receives the page information including the address of the physical page to be read by the device controller, the index of the logical page to be the target of the read request among the physical pages, and the flag indicating whether the logical page included in the page information is compressed .

In step 602, the flash memory controller can access the physical page using the address of the physical page included in the page information received from the device controller. The flash memory controller can access the physical page containing the compressed data using the address of the physical page that the flash memory controller should read.

In step 603, the flash memory controller can identify the logical page to be the target of the read request in the accessed physical page. The flash memory controller can identify the logical page among the physical pages corresponding to the index of the logical page included in the page information. In addition, the flash memory controller can determine whether the logical page is compressed based on a flag indicating whether or not the logical page included in the page information is compressed.

In step 604, if the divided page is compressed, the flash memory controller decompresses the compressed logical page using the decompression function embedded in the flash memory controller, and transfers the decompressed logical page to the read buffer of the device controller . In addition, if the divided page is not compressed, the flash memory controller can transfer the separated logical page to the read buffer of the device controller.

As a result, the solid state drive proposes a method of simultaneously reading data stored in a plurality of channels by decompressing the page through a flash memory controller connected to each channel in a page read request for data requested from a plurality of channels simultaneously can do.

Here, the flash memory controller is arranged for each of a plurality of channels, and an array of flash memory can be allocated for each of the plurality of channels.

The methods according to embodiments of the present invention may be implemented in the form of program instructions that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination. The program instructions recorded on the medium may be those specially designed and constructed for the present invention or may be available to those skilled in the art of computer software.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. This is possible.

Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined by the equivalents of the claims, as well as the claims.

101: Host
102: Solid state drive
103: Device controller
104: Flash memory controller

Claims (14)

In a decompression method performed by a flash memory controller,
Receiving page information related to the data corresponding to a read request of data stored in the flash memory from the device controller;
Accessing the physical page using an address of a physical page included in the received page information;
Identifying a logical page to be a target of the read request in the accessed physical page; And
Transferring the logical page to the device controller in consideration of whether or not the separated logical page is compressed
Lt; / RTI >
The flash memory controller includes:
Wherein the plurality of channels are arranged for each of a plurality of channels, and an array of flash memory is allocated for each of the plurality of channels. The method according to claim 1,
Wherein the step of accessing comprises:
Wherein the flash memory controller accesses a physical page including compressed data using an address of a physical page to be read. 3. The method of claim 2,
The compressed data may include:
And the compressed data is compressed by the decompression function embedded in the flash memory controller and stored in the physical page. The method according to claim 1,
Wherein the distinguishing step comprises:
Wherein the logical page is divided among the physical pages corresponding to the index of the logical page included in the page information. The method according to claim 1,
Wherein the distinguishing step comprises:
And determining whether the logical page is compressed based on a flag indicating whether or not the logical page included in the page information is compressed. 6. The method of claim 5,
The method of claim 1,
And decompressing the compressed logical page using the decompression function built in the flash memory controller when the divided page is compressed and delivering the decompressed logical page to the read buffer of the device controller. 6. The method of claim 5,
The method of claim 1,
And if the divided page is not compressed, transfers the separated logical page to the read buffer of the device controller. The method according to claim 1,
Wherein the device controller comprises:
And combining the decompressed logical pages received from the flash memory controller and another flash memory controller to transfer the combined data of the logical pages to the host. Receiving page information related to the data corresponding to a read request of data stored in the flash memory from the device controller,
Accesses the physical page using the address of the physical page included in the received page information,
A logical page to be subjected to the read request is distinguished from the accessed physical page,
Decompressing the separated logical page and delivering the decompressed logical page to the device controller. 10. The method of claim 9,
The flash memory controller includes:
An address of a physical page to be read from the device controller, an index of a logical page to be a target of a read request among the physical pages, and a flag indicating whether or not a logical page included in the page information is compressed. Arrays of flash memories corresponding to a plurality of channels; And
A plurality of flash memory controllers coupled to the plurality of flash memory arrays,
/ RTI >
Wherein each of the plurality of flash memory controllers comprises:
A solid state in which a logical page to be a target of a read request is distinguished from a physical page in response to a read request of data stored in a flash memory, and the logical page is transferred to the read buffer of the device controller, drive. 12. The method of claim 11,
Wherein each of the plurality of flash memory controllers comprises:
The flash memory controller accesses a physical page including compressed data through an address of a physical page to be read,
And a solid state drive which distinguishes the logical page by using an index of a logical page targeted for a read request in the accessed physical page. 12. The method of claim 11,
Wherein each of the plurality of flash memory controllers comprises:
A solid state drive that considers compression of a logical page based on a flag indicating whether or not a logical page included in page information related to the data is compressed, 12. The method of claim 11,
Wherein each of the plurality of flash memory controllers comprises:
And a solid state drive that decompresses the compressed logical page using the decompression function embedded in the flash memory controller when the divided page is compressed.

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