KR20160076533A - Methods and apparatus for tagging classes using supervised learning - Google Patents

Abstract

Certain aspects of the present disclosure provide methods and apparatus for generating tags (static or static) for input / output classes of a neural network model using map learning. The method includes augmenting the neural network model with a plurality of neurons and training the augmented network using spike timing dependent plasticity (STDP) to determine one or more tags.

Description

[0001] METHODS AND APPARATUS FOR TAGGING CLASSES USING SUPERVISED LEARNING [0002]

Cross-reference to related application (s)

The present application claims the benefit of U.S. Patent Application No. 14 / 065,089, filed October 28, 2013, which is incorporated herein by reference in its entirety.

Certain aspects of the disclosure generally relate to neural networks, and more particularly, to tagging classes using map learning.

An artificial neural network is a mathematical or computational model (i.e. neuron models) composed of interconnected groups of artificial neurons. Artificial neural networks may be derived (or at least loosely based) from the structure and / or function of biological neural networks such as those found in the human brain. Since neural networks can infer functions from observations, such networks are particularly useful in applications where the complexity of tasks or data makes it impractical to manually design these functions.

One type of artificial neural network is a spiking neural network that integrates the concept of time into its neural and synaptic states as well as its behavioral model and thereby provides a level of realism in this type of neural simulation . Spiking neural networks are based on the concept that neurons fire only when the membrane potential reaches a threshold. When a neuron fires, the neuron generates a spike that travels to the other neurons, which, in turn, raises or lowers the membrane potentials based on the received spike.

Non-lexical learning algorithms correctly separate data into distinct classes in multiple applications, but may not provide consistent indexes for separate classes. Instead, a class index representing a particular data type may be randomly assigned to different classes. This random assignment may not be desirable in many applications, particularly when the classification output is used as input to one or more downstream modules. Without class indexes that consistently represent the same class, it may not be possible to build a reliable interface between the modules that implement the unvisited learning algorithm and the downstream modules.

Certain aspects of the disclosure suggest methods for tagging classes. The method generally includes identifying a first network comprising one or more indexed classes of artificial neurons, and determining one or more tags for one or more classes of artificial neurons irrespective of their indexing .

Certain aspects of the present disclosure propose an apparatus for tagging classes. The apparatus generally includes means for identifying a first network comprising one or more indexed classes of artificial neurons and means for determining one or more tags for one or more classes of artificial neurons irrespective of their indexing .

Certain aspects of the present disclosure propose an apparatus for tagging classes. The apparatus generally includes at least one processor configured to identify a first network comprising one or more indexed classes of artificial neurons and to determine one or more tags for one or more classes of artificial neurons irrespective of their indexing, And a memory coupled with the at least one processor.

Certain aspects of the present disclosure propose a program product for tagging classes. The program product typically includes instructions for identifying a first network comprising one or more indexed classes of artificial neurons and for determining one or more tags for one or more classes of artificial neurons, Readable medium.

BRIEF DESCRIPTION OF THE DRAWINGS In order that the above-recited features of the present disclosure may be understood in detail, the foregoing brief summary may be made with reference to the embodiments, some of which are shown in the accompanying drawings. It is to be noted, however, that the appended drawings illustrate only certain typical aspects of the present disclosure, and therefore, should not be viewed as limiting its scope, and that the description may admit to other equally effective aspects.
Figure 1 illustrates an exemplary network of neurons according to certain aspects of the present disclosure.
Figure 2 illustrates an example of a processing unit (neuron) of a math network (neural or neural network), according to certain aspects of the present disclosure.
FIG. 3 illustrates an example of a spike-timing dependent plasticity (STDP) curve according to certain aspects of the present disclosure.
Figure 4 illustrates an example of a positive regime and a negative regime for defining the behavior of a neuron model, in accordance with certain aspects of the present disclosure.
Figure 5 illustrates an exemplary high-level block diagram of a system that utilizes neural network blocks, in accordance with certain aspects of the present disclosure.
Figure 6 illustrates an exemplary stimulus processing model in accordance with certain aspects of the present disclosure.
Figure 7 illustrates an exemplary method for tagging classes according to certain aspects of the present disclosure.
Figure 8 illustrates exemplary operations for tagging classes of nodes, in accordance with certain aspects of the present disclosure.
8A illustrates exemplary components that are capable of performing the operations depicted in FIG.
Figures 9A-9C illustrate a proposed tagging method in accordance with certain aspects of the present disclosure.
Figure 10 illustrates an exemplary plasticity rule according to certain aspects of the present disclosure.
11 illustrates an exemplary application of the proposed method in generating input action tags for a motor, according to certain aspects of the present disclosure.
Figure 12 illustrates an exemplary application of a proposed tagging method in generating class boundaries, in accordance with certain aspects of the present disclosure.
Figures 13A-13C illustrate another exemplary application of a proposed tagging method for convergent classes, in accordance with certain aspects of the present disclosure.
Figures 14A-14C illustrate another exemplary application of the proposed tagging method in a neural network with an over-complete representation, in accordance with certain aspects of the present disclosure.
Figure 15 illustrates an exemplary method for adding a new class to a neural network, in accordance with certain aspects of the present disclosure.
Figure 16 illustrates an exemplary model that utilizes supervisory signals, in accordance with certain aspects of the present disclosure.
Figure 17 illustrates exemplary timing of application of management signals, in accordance with certain aspects of the present disclosure.
18 illustrates an exemplary effect of an application of management signals in accordance with certain aspects of the present disclosure.
Figures 19, 20A and 20B illustrate exemplary rules for adjusting management signals, in accordance with certain aspects of the present disclosure.
Figure 21 illustrates an exemplary implementation for designing a neural network using a general purpose processor, in accordance with certain aspects of the present disclosure.
22 illustrates an exemplary implementation for designing a neural network in which memory may be interfaced with discrete distributed processing units, in accordance with certain aspects of the present disclosure.
Figure 23 illustrates an exemplary implementation for designing a neural network based on distributed memories and distributed processing units, in accordance with certain aspects of the present disclosure.
24 illustrates an exemplary implementation of a neural network according to certain aspects of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS Various aspects of the disclosure are described more fully hereinafter with reference to the accompanying drawings. This disclosure, however, may be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout this disclosure. Instead, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Based on the teachings herein, one of ordinary skill in the art will recognize that, whether implemented independently or in combination with any other aspects of the disclosure, the scope of the present disclosure is intended to cover any aspect of the disclosure disclosed herein something to do. For example, a device may be implemented or a method may be practiced using any number of aspects set forth herein. Additionally, the scope of the present disclosure is intended to cover such apparatus or methods as practiced using the structures and functions in addition to or instead of the various aspects of the present disclosure described herein, or other structures, functions . It is to be understood that any aspect of the disclosure disclosed herein may be implemented by one or more elements of the claims.

The word "exemplary" is used herein to mean "serving as an example, illustration, or illustration. &Quot; Any aspect described herein as "exemplary " is not necessarily to be construed as preferred or advantageous over other aspects.

While certain aspects are described herein, many variations and permutations of these aspects are within the scope of this disclosure. While certain benefits and advantages of the preferred embodiments are mentioned, the scope of the present disclosure is not intended to be limited to any particular advantage, use, or purpose. Instead, aspects of the present disclosure are intended to be broadly applicable to different techniques, system configurations, networks, and protocols, some of which are illustrated by way of example in the drawings and in the following description of the preferred embodiments . The description and drawings are merely illustrative of the present disclosure rather than limiting, and the scope of the present disclosure is defined by the appended claims and their equivalents.

Illustrative Neural  system, training  And operation

FIG. 1 illustrates an exemplary neural system 100 having multiple levels of neurons according to certain aspects of the present disclosure. Neural system 100 may include a level 102 of neurons connected to a different level 106 of neurons via network 104 of synaptic connections (i.e., feed-forward connections). For simplicity, even though only two levels of neurons are shown in FIG. 1, fewer or more levels of neurons may be present in a typical neural system. It should be noted that some of the neurons may connect to other neurons in the same layer via side connections. Moreover, some of the neurons may reconnect to the neurons of the previous layer through feedback connections.

As shown in FIG. 1, each neuron in level 102 may receive an input signal 108 that may be generated by a plurality of neurons at a previous level (not shown in FIG. 1). Signal 108 may represent the input current of a level 102 neuron. This current may be accumulated on the neuron membrane to charge the membrane potential. When the membrane potential reaches its threshold value, the neuron may ignite and produce an output spike to be sent to the next level of neurons (e.g., level 106). Such behavior can be emulated or simulated in hardware and / or software, including analog and digital implementations.

In biological neurons, the output spike produced when a neuron fires is referred to as the action potential. This electrical signal is a relatively fast, transient, all-or nothing nerve impulse with an amplitude of approximately 100 mV and a duration of approximately 1 ms. In certain embodiments of a neural system having a series of connected neurons (e.g., transmission of spikes from one level of neurons to another level in FIG. 1), all of the action potentials have essentially the same amplitude and duration , So the in-signal information is represented only by the frequency and number of spikes, or the time of spikes, and not by the amplitude. The information conveyed by the action potential is determined by the time of the spike for spikes, spiked neurons, and other spikes or spikes.

The transmission of spikes from one level of neurons to another level may be achieved via a network of synaptic connections (or simply "synapses") 104, as shown in FIG. Synapses 104 receive output signals (i.e., spikes) from level 102 neurons (pre-synaptic neurons for synapses 104) and convert the signals to adjustable synapses the weights ^{_{(w 1 (i, i +}} 1), ..., w P (i, i + 1)) ( where, P is the total ordination of the synapse connections between neurons in the levels 102 and 106) You can also scale accordingly. In addition, the scaled signals may be combined as an input signal of each neuron at level 106 (post-synaptic neurons for synapses 104). All neurons of level 106 may generate output spikes 110 based on the corresponding combined input signal. The output spikes 110 may then be transmitted to different levels of neurons using another network of synaptic connections (not shown in FIG. 1).

Biological synapses may be classified as electrical or chemical synapses. Although electrical synapses are primarily used to transmit excitatory signals, chemical synapses can mediate excitatory or inhibitory (hyperpolarizing) activities in post-synaptic neurons, and can also function to amplify neuronal signals. Excitable signals typically depolarize the membrane potential (i. E., Increase the membrane potential relative to the hibernation potential). When sufficient excitatory signals are received within a certain time period to depolarize the membrane potential beyond the threshold, action potentials occur in post-synaptic neurons. In contrast, inhibitory signals generally depolarize (i.e., reduce) the membrane potential. The inhibitory signals, if strong enough, can cancel out the sum of the excitatory signals and prevent the membrane potential from reaching the threshold. In addition to counteracting synaptic excitement, synaptic inhibition can provide powerful control over spontaneously active neurons. A spontaneously active neuron refers to a neuron that spikes without additional input, e.g., due to its dynamics or feedback. By suppressing the spontaneous production of action potentials in these neurons, synaptic inhibition can shape the pattern of utterance in neurons, commonly referred to as sculpturing. The various synapses 104 may act as any combination of excitatory or inhibitory synapses, depending on the desired behavior.

The neural system 100 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, , A software module executed by a processor, or any combination thereof. The neural system 100 may be utilized in a wide range of applications such as image and pattern recognition, machine learning, motor control, and the like. Each neuron in neural system 100 may be implemented as a neuron circuit. The neuron membrane charged to a threshold that initiates an output spike may be implemented, for example, as a capacitor that integrates the flowing current.

In an aspect, the capacitor may be removed as a current integration device of the neuron circuit, and a smaller memristor element may be used instead. This approach may be applied not only to the neuron circuits but also to various other applications in which the bulk capacitor is utilized as current integrators. Additionally, each of the synapses 104 may be implemented based on a memristor element, wherein the synaptic weight changes may be associated with changes in the memristor resistance. Using nanometer feature-sized memristors, the area of the neuron circuits and synapses may be substantially reduced, which may make the implementation of a very high density neural system hardware implementation real.

The function of the neural processor to emulate the neural system 100 may depend on the weights of the synapse connections, which may control the strengths of connections between neurons. Synapse weights may be stored in non-volatile memory to preserve processor functionality after power-down. In an aspect, the synaptic weight memory may be implemented on an external chip separate from the main neural processor chip. The synapse weight memory may be packaged separately from the neural processor chip as a replaceable memory card. This may provide various functions to the neural processor, where the particular function may be based on synapse weights stored on a memory card currently attached to the neural processor.

Figure 2 illustrates an example 200 of a processing unit (e.g., a neuron or neuron circuit) 202 of an operational network (e.g., a neural or neural network), in accordance with certain aspects of the present disclosure. For example, neuron 202 may correspond to any of the neurons of levels 102 and 106 from FIG. The neuron 202 may receive multiple input signals 2041-204N (x1-xN), which may be generated by signals outside the neural system, or by other neurons of the same neural system Signals, or both. The input signal may be a real or a complex or a current or voltage. The input signal may include a numerical value with a fixed-point or floating-point representation. These input signals may be passed to the neuron 202 through synaptic connections scaling the signals according to adjustable synaptic weights 2061-206N (w1-wN), where N is the number of input connections of the neuron 202 It may be a total number.

Neuron 202 may combine the scaled input signals and use the combined scaled inputs to generate output signal 208 (i. E., Signal y). The output signal 208 may be a real or a complex value current or voltage. The output signal may include a numerical value with a fixed-point or floating-point representation. The output signal 208 may then be transmitted as an input signal to other neurons of the same neural system, or as an input signal to the same neuron 202, or as an output of a neural system.

The processing unit (neuron) 202 may be emulated by an electrical circuit, and its input and output connections may be emulated by wires having synaptic circuits. The processing unit 202, its input and output connections, may also be emulated by software code. The processing unit 202 may also be emulated by electrical circuitry, but its input and output connections may be emulated by software code. In an aspect, the processing unit 202 in the computational network may include analog electrical circuitry. In another aspect, the processing unit 202 may comprise digital electrical circuitry. In another aspect, the processing unit 202 may comprise a mixed signal electrical circuit with both analog and digital components. The computing network may include processing units in any of the above-described forms. Computational networks (such as neural or neural networks) using such processing units may be utilized in a wide range of applications such as image and pattern recognition, machine learning, motor nerve control, and the like.

During the training of the neural network, synaptic weights (e.g., weights w ₁ ^{(i, i + 1)} , ..., w _P ^{(i, i + 1)} The weights 2061-206N from FIG. 2) are initialized to random values, and may be increased or decreased in accordance with the learning rule. Some examples of learning rules are spike-timing dependent plasticity (STDP) learning rules, Hebb rules, Oja rules, and BCM (Bienenstock-Copper-Munro) rules. Very often, the weights may be set to one of two values (i.e., a bimodal distribution of weights). This effect can be exploited to reduce the number of bits per synapse weight, to increase the rate at which synapse weights are read from and written to the memory storing synapse weights, and the power consumption of the synapse memory.

Synaptic type

In hardware and software models of neural networks, the processing of synaptic related functions may be based on synapse type. Synaptic types include non-plastic synapses (no changes in weight and delay), plastic synapses (weights may change), structural delayed plastic synapses (weights and delays may change), completely plastic Synapses (weight, delay, and degree of connectivity may vary), and variations thereof (e.g., delay may vary but no change in weight or degree of connectivity). The advantage of this is that processing can be subdivided. For example, non-plastic synapses may not require that the plasticity functions be performed (or wait for those functions to complete). Similarly, the delay and weighted plasticity may be subdivided into operations that may or may not operate separately or sequentially, or in parallel. Different types of synapses may have different look-up tables or formulas and parameters for each of the different types of plasticity applied. Thus, the methods will access the related tables for the type of synapse.

There are additional implications of the fact that spike-timing-dependent structural plasticity may be performed independently of synaptic plasticity. Structural plasticity means that even if there is no change in the weight magnitude (e.g., the weight has reached the minimum or maximum value, or the maximum value has been reached) because structural plasticity (i.e., the amount of delay variation) may be a direct function of the pre- Or for some other reason). Alternatively, it may be set as a function of the weight variation, or based on conditions relating to weights or limits of weight variations. For example, the synapse delay may change only when a weight change occurs or when the weights reach zero, but may not change when the weights reach a maximum. However, it may be advantageous to have independent functions such that these processes can be parallelized to reduce the number and overlap of memory accesses.

Determination of synaptic plasticity

Neuroplasticity (or simply "plasticity") is the capacity of neurons and neural networks in the brain to alter their synaptic connections and behavior in response to new information, sensory stimuli, development, impairment, or dysfunction. Plasticity is important in neural science and neural networks as well as learning and memory in biology. The plasticity of various forms such as synaptic plasticity, spike-timing dependent plasticity (STDP), non-synaptic plasticity, activity dependent plasticity, structural plasticity, and everlasting plasticity (according to Hebbian theory, for example)

STDP is a learning process that adjusts the strength of synaptic connections between neurons. The connection strengths are adjusted based on the relative timing of the output of a particular neuron and the received input spikes (i.e., action potentials). Under the STDP process, long term enhancement (LTP) may occur if the input spike to a particular neuron, on average, tends to occur just before the output spike of that neuron. Then, the specific input is made somewhat stronger. On the other hand, if the input spike tends to occur on the average immediately after the output spike, the long-term suppression LTD may occur. Thereafter, the particular input is made somewhat weaker and is thus termed "spike-timing dependent plasticity ". As a result, inputs that may be the cause of neuron excitability after synapse are much more likely to contribute in the future, but inputs that are not causative of post-synaptic spikes are less likely to contribute in the future. The process continues until a subset of the initial set of connections is maintained, while all remaining effects are reduced to zero or nearly zero.

Since a neuron generally produces an output spike when many of its inputs occur within a short period of time (i. E., Sufficiently cumulative to cause an output), a subset of the normally remaining input tends to be temporally correlated Lt; / RTI > Additionally, since the inputs that occur before the output spike are enhanced, the inputs that provide the indication of the earliest sufficiently cumulative correlation will eventually become the final input to the neuron.

The STDP learning rule determines the synaptic weight of a synapse that connects a _pre- synaptic neuron to a _post- synapse neuron as the time difference between the spike time (t _pre ) of the synaptic _pre- neuron and the post-synaptic spike time (t _post ) _post- t _pre ). A typical formulation of STDP is that if the time difference is positive (when the synaptic neurons fire before the post-synaptic neurons) they increase the synapse weight (i.e., enhance the synapse) and if the time difference is negative (Ie, suppressing the synapse) when the posterior neuron fires before the pre-synaptic neuron.

For the STDP process, a change in synapse weights over time may typically be achieved using exponential decay, as given below,

Where k ₊ and k _- are time constants for the positive and negative time differences, respectively, where alpha ₊ and alpha _- are the corresponding scaling magnitudes, and mu is an offset that may be applied to the positive time difference and / or the negative time difference.

Figure 3 shows an exemplary graphical diagram 300 of synaptic weight changes as a function of the relative timing of synaptic and post-synaptic spikes according to STDP. If the pre-synaptic neurons fire prior to post-synaptic neurons, the corresponding synapse weights may be increased, as shown in portion 302 of graph 300. This weighting increase can be referred to as LTP of the synapse. It can be observed from graph portion 302 that the amount of LTP may decrease approximately exponentially as a function of the difference between pre-synaptic and post-synaptic spike times. The reverse order of utterance may decrease the synaptic weights, resulting in LTD of synapses, as shown in portion 304 of graph 300.

As shown in graph 300 in FIG. 3, the negative offset () may be applied to the LTP (causal) portion 302 of the STDP graph. The intersection point 306 of the x-axis (y = 0) may be configured to coincide with the maximum time lag to account for the causal inputs from layer i-1. In the case of a frame-based input (i.e., if the input is in the form of a frame of a particular duration including spikes or pulses), the offset value may be computed to reflect the frame boundary. The first input spike (pulse) in the frame may be considered to be attenuated over time, such as when modeled directly by post-synaptic potential or in terms of effects on neural conditions. If the second input spike (pulse) in the frame is considered to be correlated or related to a particular time frame, the associated times before and after the frame may be adjusted such that the values at their associated times may differ (e.g., May be separated at that time frame boundary by offsetting one or more portions of the STDP curve that are negative for the larger one and less than one frame for the larger one, and may be treated differently in the plasticity terms. For example, the negative offset () may be set to offset the LTP such that the curve goes below zero in pre-post-time times where the curve is actually greater than the frame time and is therefore part of LTD instead of LTP.

Neuron models and operation

There are some general principles for designing useful spiking neuron models. A good neuron model may have abundant potential behavior in terms of two computational regimes: coincident detection and functional computation. Moreover, a good neuron model will have two elements to allow temporal coding: the arrival times of the inputs affect the output time and the coincidence detection can have a narrow time window. Finally, to be computationally interesting, a good neuron model has a closed-form solution at successive times and has stable behavior including close attractors and saddle points It is possible. That is, useful neuron models can be used both to model rich and realistic, biologically consistent behaviors as well as to design and reverse engineer neural circuits and are practical models.

Neuron models may rely on events such as input arrivals, output spikes, or other events both internally and externally. To obtain a rich behavioral repertoire, a state machine may be desired that can represent complex behaviors. If the occurrence of the event itself distinct from the input contribution (if any) can affect the state machine or bind the dynamics that follow it, then the future state of the system is not only a function of state and input, And input.

In an aspect, the neuron n may be modeled as a spiking leaky-integrate-and-fire neuron having a membrane voltage v _n (t) governed by the following dynamics:

Where wm and _n are synaptic weights for synapses that connect the synaptic preneurons m to post-synaptic neurons n and y _m (t) are the synaptic weights for the neurons (n) (M) which may be delayed by dendritic or axonal delay according to [Delta] tm _{, n} up to the arrival of the neuron (m).

It should be noted that there is a delay from the time when sufficient input to the post-synaptic neuron is established to the time when the neuron actually fires after the synapse. For a dynamic spiking neuron model, such as the simple model of Izhikevich, the time delay may be caused by the difference between the depolarization threshold (v _t ) and the peak spike voltage (v _peak ). For example, in a simple model, neuronal cell dynamics can be governed by a pair of differential equations for voltage and recovery,

Where v is the membrane potential, u is the membrane recovery parameter, k is the parameter describing the time scale of the membrane potential (v), alpha is the parameter describing the time scale of the recovery variable (u), b is the membrane Is a parameter that describes the sensitivity of the recovery variable (u) to sub-threshold variations of the potential (v), v _r is the membrane dwell potential, I is the synapse current, and C is the capacitance of the membrane . According to this model, neurons are defined to spike when v> v _peak .

Hunzinger  Cold model

The Hunzinger Cold neuron model is the minimum dual-regime spiking linear model of dynamics that can reproduce a rich variety of neuronal behaviors. The one-dimensional or two-dimensional linear dynamics of the model may have two regimes, where the time constant (and coupling) may depend on its regime. In the regime below the threshold, the negative time constant by convention represents a leaking channel dynamics that normally operates to return the cell to rest in a biologically consistent linear fashion. The time constant in the supra-threshold regime that is positive by convention reflects the leakage-prevention channel dynamics that generally drives the cell to spike while causing latency in spike occurrences.

As shown in FIG. 4, the dynamics of the model may be divided into two (or more) regimes. These regimes include a negative regime 402 (also referred to interchangeably as the Leakage Integral Emission (LIF) regime so as not to be confused with the Leakage Integrative Emission (LIF) neuron model) and a positive regime 404 (Also referred to interchangeably as an anti-leakage integral speech (ALIF) regime, so as not to be confused with the ALIF neuron model). In the negative regime 402, the condition tends to go to rest (v < _- >) in the event of a future event. In this negative regime, the model generally represents the behavior under time input detection characteristics and other thresholds. In the positive regime 404, the state tends to go towards the spiking event v _S. In this positive regime, the model exhibits computational properties, such as causing latency to spike depending on subsequent input events. Formulation of dynamics in terms of events and separation of dynamics into these two regimes are fundamental characteristics of the model.

The linear dual-regime two-dimensional dynamics (for states v and u) may be defined by convention as follows,

Where q _p and r are linear transformation variables for coupling.

The symbol p is a convention for replacing the symbol p with the sign "-" or "+" for the negative and positive regimes, respectively, when discussing or expressing the relationship to a specific regime. Used in the specification.

The model condition is defined by the membrane potential (voltage) (v) and the recovery current (u). In the basic form, the regime is essentially determined by the model state. Although there are subtle but important aspects of an accurate and general definition, it is now assumed that the model is in the positive regime 404 if the voltage v is greater than the threshold v ₊ , otherwise it is considered to be in the negative regime 402 do.

The regime-dependent time constants include the negative regime time constant τ _- , and the positive regime time constant τ ₊ . The recovery current time constant < RTI ID = 0.0 &_gt; (tau) < / _RTI > For the sake of convenience, the negative regime time constant τ _- is typically specified as a negative quantity to reflect the decay, so that the same expression for voltage evolution, such as τ _u , exponent and τ ₊ May be used as for the positive one positive regime.

The dynamics of the two state elements may be coupled by transformations that offsets the states from their null-clines in events,

, Where δ, ε, β and ν _- , ν ₊ are parameters. Two values for _ρ ν are the base for the reference voltage for the two regimes. The parameter (v < _- >) is the base voltage for the negative regime, and the membrane potential will generally decay from negative regime towards v _- . The parameter (v ₊ ) is the base voltage for the positive regime, and the membrane potential will generally tend to be spaced from v _& lt _{; + &} gt _; in the positive regime.

Board for ν and u - Klein are given respectively by the negative of the conversion parameter _(ρ q and r). The parameter [delta] is a scale factor controlling the slope of the u-null-cline. The parameter? Is usually set equal to -ν _- . The parameter β is a resistance value that controls the slope of ν null-clines in both regimes. The τ _ρ time constant parameters control not only the exponential attenuations but also the null-cline gradients separately in each regime.

The model is defined to spike when the voltage (v) reaches the value v _S. Subsequently, the state is typically reset to a reset event (which technically is one and may be the same as a spike event): < RTI ID = 0.0 >

및 △u 는 파라미터들이다. 리셋 전압 (

) 은 통상적으로 ν_- 로 설정된다.Lt; / RTI >

And [Delta] u are parameters. Reset voltage

) Is typically set to v _- .

By virtue of the principle of momentary coupling, a closed-form solution is possible for the time required to reach a particular state as well as for a state (and a state with a single exponential term). The closed state solutions are as follows.

Thus, the model state may only be updated at events such as at the input (synaptic spike) or at the output (post-synaptic spike). Actions may also be performed at any particular time (either input or output).

Moreover, due to the momentary coupling principle, the time of post-synaptic spikes may be expected, so that the time to reach a particular state may be predetermined without repeated techniques or numerical methods (e.g., Euler numerical methods) . Given a previous voltage state (v _o ), the time delay until the voltage state (v _f ) is reached is given by

If a spike is defined as occurring at a time when the voltage state (v) reaches? _S , a closed state is established for the amount of time, or relative delay, until a spike occurs when the voltage is measured from the time in a given state The solution of the form is as follows,

(14)

(14)

는 통상적으로, 파라미터 (ν₊) 로 설정되지만, 다른 변경들이 가능할 수도 있다.here,

Is normally set to the parameter (v ₊ ), but other changes may be possible.

The above definitions of model dynamics depend on whether the model is in the positive regime or in the negative regime. As noted, the coupling and regime p may be computed at events. For purposes of state propagation, regime and coupling (conversion) variables may be defined based on the state at the end (pre) event. For purposes of subsequently anticipating the spike output time, the regime and coupling variables may be defined based on the state at the next (current) event.

There are several possible implementations of the Cold model, and are running simulations, emulations, or models in time. This includes, for example, event-update, step-event update, and step-update modes. An event update is an update in which states are updated based on events (at a particular instant in time) or "event updates ". A step update is an update when the model is updated with intervals (e.g., 1 ms). It does not necessarily require iterative methods or numerical methods. The event-based implementation is also possible at a limited time resolution in a step-based simulator, by just updating the model in steps or between steps, or when an event occurs by "step-event" update.

Neural coding

A useful neural network model, such as a model of artificial neurons 102, 106 of FIG. 1, may be used to generate information (e.g., information) through any of a variety of suitable neural coding schemes such as coincidence coding, temporal coding, Lt; / RTI > For coincidence coding, the information is encoded into the coincidence (or time proximity) of the action potentials (spiking activity) of the neuron population. In temporal coding, neurons encode information through the correct timing of action potentials (i.e., spikes), whether in absolute time or relative time. Thus, the information may be encoded at the relative timing of the spikes in the population of neurons. In contrast, rate coding involves coding neural information at a rate of speech or a population speech rate.

If the neuron model can perform temporal coding, the neuron model can also perform rate coding (because the rate is only a function of timing or spike spacing). To provide temporal coding, a good neuron model would have the following two elements: (1) the arrival times of the inputs affect the output time; And (2) coincidence detection may have a narrow time window. Connection delays provide a means for extending coincidence detection to time pattern decoding, as the elements may be timing aligned by reasonably delaying the elements of the time pattern.

Reach time

For a good neuron model, the arrival time of the input will affect the time of the output. The synaptic input can be either a Dirac delta function or a shaped post-synaptic potential (PSP), an excitation (EPSP) or an inhibition (IPSP), a reaching time which may be referred to as the input time The time or step of the function or the start or peak of another input function). Neuron output (i. E., Spike) has a time of occurrence that may be referred to as the output time (e. G., Anywhere in the cell body, at the point along the axon, or at the end of the axon). The output time may be the time of the peak of the spike, the start of the spikes, or any other time associated with the output waveform. A very important principle is that the output time depends on the input time.

People may, at first glance, think that all neuron models follow this principle, but this is not generally true. For example, rate-based models do not have this feature. Many spiking models also do not generally follow. The Leakage Integral Ignition (LIF) model, if there are extra inputs (beyond the threshold), does not fire any more quickly. Moreover, models that may be followed when modeled at very high timing resolution will often not follow when the timing resolution is limited to, for example, 1 ms steps.

Inputs

The input to the neuron model may include delta delta functions such as inputs as currents or conductance-based inputs. In the latter case, the contribution to the neuronal state may be continuous or state-dependent.

For particular aspects, the neural system 100 may be used in a system that assigns tags to each of the output classes utilizing map learning as described herein. These tags may be allocated either statically (once) or dynamically (e.g., while tag assignments change from time to time).

Exemplary methods and apparatus for tagging classes using map learning

Non-lexical learning algorithms correctly separate data into distinct classes in multiple applications, but may not provide consistent indexes for separate classes. Instead, a class index representing a particular data type may be randomly assigned to different classes. This random assignment may not be desirable in many applications, particularly when the classification output is used as input to one or more downstream modules. Without class indexes that consistently represent the same class, it may not be possible to build a reliable interface between the modules that implement the unvisited learning algorithm and the downstream modules.

Certain aspects of the present disclosure provide a method for tagging classes using map learning and spike timing dependent plasticity (STDP). The proposed method may apply tags (static or dynamic) to any sequence of classes regardless of their indexing.

The methods presented herein are based on an all-to-all approach between N output neurons (where N may represent the number of desired classes) and arbitrarily indexed class neurons and output neurons, Any model may be augmented with a neural network of plastic connections. This all-to-all neural network is then trained using map learning so that each output neuron always represents the same class. Map training is performed by transmitting a known sequence of classes to the network and by forcing spiking and / or non-spiking activity in output neurons.

There will be a match of spikes between this pair of neurons and the other pair of neurons because an arbitrarily ordered class neuron will spike at the time of presentation of that class and the output neurons associated with this class have been forced to spike . This match will cause the synaptic weight of the connection between these pairs of neurons to increase with the STDP curve. By configuring such curves to increase the weights that match the neurons in unison and reduce the weights that ignite the neurons non-coherently, over time, only connections that will last will be between pairs of neurons representing the same class will be. Since the management spiking signal is transmitted only with the desired output neuron, the same indexing of the output class neurons will be achieved regardless of the indexing of the original class neuron. In some cases, spiking at output neurons associated with classes other than those presented as input may be suppressed. Multiple output layer neurons carrying different labels may be associated with the output of the classifier.

Figure 5 illustrates an exemplary high-level block diagram of a system utilizing a neural network, in accordance with certain aspects of the present disclosure. As shown, the temporal coding model 502 is connected to a foraging circuit 504 via a neural block interface 506. [ The temporal coding model 502 may separate the data into different classes (e. G., Red, blue, and green classes) using a non-geographic learning algorithm. The neural network interface needs to know the exact specification / tag of each output class of the temporal coding model 502 to correctly connect to the input nodes of the poling circuit 504. [

Figure 6 illustrates an exemplary stimulus processing model in accordance with certain aspects of the present disclosure. As shown, the stimulus processing model 610 may process input stimuli and generate one or more outputs / output classes. For example, the stimulus processing model may process sensory input 602 and generate output class 1 602, class 2 604, class 3 606. The input stimulus may be randomly assigned to one or more of the output classes 602, 604, and / or 606. As a result, neurons representing the input stimulus 602 may be randomly located in the output layer of the stimulus processing model 610. The downstream neural blocks may need to assume a class of specific neurons or neurons to fire on a particular input stimulus (e.g., a red ball). Thus, the performance of the stimulus processing model may need to be observed. The stimulus processing model 610 may include a time coded block 506, and / or any other neural network block that may be used to process and / or classify data.

Certain aspects of the present disclosure provide a method for tagging classes generated by a non-learning learning algorithm (e.g., temporal coding block 506) into meaningful tags. The tags generated by the proposed method are consistent regardless of the class index output from the non - graphics learning algorithm. For certain aspects, the tagging methods presented herein may use a single layer neural network combined with map learning and spike timing dependent plasticity (STDP). Although most of the examples presented herein assume a single layer neural network, it should be noted that the teachings herein may be applied to any neural network having any number of layers, all of which are within the scope of this disclosure .

Figure 7 illustrates an exemplary block diagram of a proposed method for tagging classes, in accordance with certain aspects of the present disclosure. As shown, the output nodes (and / or the output classes of nodes) of the neural network model 710 may be connected to the augmented model 720. In this example, each node may represent an artificial neuron. Each of the outputs of the augmented model 720 may correspond to an assignment (e.g., a tag). For example, the output 722 may correspond to a red color, the output 724 may correspond to a green color, and the output class 724 may correspond to a blue color. Additionally, each of the outputs of the neural network model 710 may correspond to one of the red, green, or blue colors at random. For example, the output node 712 may correspond to green, the output node 714 may correspond to the blue color, and the output node 716 may correspond to the red color. The proposed solution enables static mapping between the stimulus class and one or more output neurons (nodes) representing the stimulus class. Although certain aspects are described herein with reference to tags, the techniques described herein may also be used to achieve dynamic mapping between a stimulus class and one or more output neurons (e.g., to capture changes in a system environment) And may be used to dynamically assign tags.

FIG. 8 illustrates exemplary operations 800 for tagging classes of artificial neurons, in accordance with certain aspects of the present disclosure. At 802, a first network comprising one or more indexed classes of artificial neurons may be identified. At 804, one or more tags may be determined for one or more classes of artificial neurons regardless of their indexing. As an example, the first network may be augmented with a second network, which may include one or more artificial neurons, wherein each artificial neuron in the second network corresponds to a tag. Each of one or more classes of artificial neurons may be connected to both artificial neurons in the second network with one or more plastic connections. The one or more fictitious connections may be trained using a guidance learning algorithm such that each artificial neuron of the second network presents a particular class of the first network regardless of its indexing.

Figures 9A-9C illustrate steps that may be taken for the proposed tagging method according to certain aspects of the present disclosure. 9A illustrates a neural network model 710 that is augmented with another neural network model (e.g., model enhancement 720). The nodes in the output layer nodes (e.g., artificial neurons) of the neural network model 710 are connected to all nodes of the enhanced model 720 via plasticity synapses. Plasticity synapses may change in strength in response to the use or nonuse of a connection between nodes. In this example, the augmented model 720 has only one layer of nodes, but in general, the augmented model may have any number of layers and any number of nodes.

FIG. 9B illustrates an exemplary timing diagram for generating spikes in a neural network model 710 and generating management spikes in an augmented model 720, in accordance with certain aspects of the present disclosure. As shown, at time t ₀ , a stimulus 902 may be presented to the neural network model 710. At time t ₁ , there may be spikes in the output layer of neural network model 710 in response to stimulus 902. For example, the output node 716 of the neural network model 710 may represent a spike at time t ₁ . At time t ₂ , a management spike signal may be generated at one of the outputs of the augmented model 720. For example, management spikes may be generated at the output node 722 of the augmented model 720. Next, the weights of the plastic connections between the nodes in the two networks 710 and 720 are determined based on the spikes at times t ₁ and t ₂ . For example, for the neurons (such as in the spiking at time t ₁ in the original model (710) node 716, the model 720 is augmented showing the stimulation from (for example, node Z) node R ( 722) is enhanced (for example, +? (Z? R), where? Is a positive number indicating the change in the strength of the connectivity of the connection). Thus, the synapse weights between nodes 716 and 722 are increased. Additionally, if other nodes (e.g., X and / or Y) in the output layer of the original model 710 have been spiked earlier, then the plasticity rule may be applied to node R 722 in the enhanced model Weaken the association (e.g., -δ (X → R) and -δ (Y → R)). Spiking at output neurons associated with classes other than those presented as inputs may be suppressed, as illustrated by "X" in output nodes G and B.

Figure 9c shows the final connections between nodes in the neural network model 710 and node R 722 of the augmented model 720 after presenting the stimulus 902 to the models and applying the plasticity rule. In this figure, tag R is the same as tag R since the weight of the plastic connection between node Z 716 and node R 722 is higher than the weight of the other connections between node R 722 and the output of original model 710, Lt; RTI ID = 0.0 > 716 < / RTI >

10 illustrates an exemplary plasticity rule that may be used in the proposed tagging method according to certain aspects of the present disclosure. As shown in the figure, the weights of the plastic connections between the two nodes may be modified based on the time each of the nodes exhibits a spike.

It should be noted that the proposed technique is not specific to the sensory stimulus classification and can be applied to tag the classes of inputs / outputs of any neural network block. For example, the proposed method can be applied to generate tags for actions from neural network blocks that transmit motor neural control commands to the motor neuron, as shown in FIG.

Figure 11 illustrates an exemplary application of the proposed method in generating input action tags for the motor nerve, in accordance with certain aspects of the present disclosure. As shown, a device (e.g., robot 1112) may be connected to motor neurons (M _I 1108 and M _r 1110) that modulate motor neuron activity. Motor neurons (M _I 1108 and M _r 1110) may be connected to arrays of externally stimulated neurons 1104 and 1106, respectively. Each of the motor nerves may be connected to both neurons of one of the arrays through non-plastic connections. For example, motor neuron M _I 1108 may be connected to both neurons of array 1104. Each of the arrays of neurons 1104 and / or 1106 may cause different motions in the robot.

Next, the action tags (e.g., forward (F) 1114 and / or backward (B) 1116) are coupled to both neurons in each of arrays 1104 and 1106 via plasticity synapses . The directed action classifier 1118 may send a management spike to one of the action tags (e.g., B 1116) to determine action tags for movements in the device. External stimulus signal 1122 may also be transmitted to the arrays of neurons at the appropriate time. Based on the direction of motion of the device in response to stimulus and management signals, input action tags may be generated for the forward and / or backward motion of the device. In some cases, the timing at which particular tags are generated may depend on the specific motions of the device. For example, if a device (e.g., a robot) moves very precisely backwards or forwards, the action tag neuron may be immediately stimulated. On the other hand, if the device moves less accurately, the action tag neuron may be stimulated with some delay. This timing effect, along with the plasticity rules, may allow grade learning.

For certain aspects, the proposed tagging method may be used to generate boundaries between classes of nodes. Figure 12 illustrates an exemplary application of a proposed tagging method in generating class boundaries, in accordance with certain aspects of the present disclosure. As shown, the neural network model may have two desired outputs (e.g., blue and / or red). In this example, the purple stimulus 1202 (which is a combination of blue and red colors) may be either red or blue (e.g., depending on the purple tint with more blue and / or more red dyes) . For example, P1 may contain more red color than blue, P2 may contain the same amount of red and blue color, and P3 may contain more blue color than red color. The desired classifications are shown in columns 1204. The red and blue class boundaries 1206 may be controlled using the proposed tagging method.

Figures 13A-13C illustrate another exemplary application for the proposed tagging method (e.g., for convergent classes), in accordance with certain aspects of the present disclosure. 13A illustrates a stimulus processing model that may be trained to generate a plurality of classes (e.g., six classes including red, blue, green, and three purple classes P1, P2, and P3) (1302). The proposed tagging method may be used to reduce the number of output classes. For example, the proposed tagging method may be used to reduce the output classes in Figure 13A into three classes (red, green, and blue). First, the network may be augmented as shown in FIG. 13B. All of the neurons in the output layer of the stimulus processing model may be connected to all nodes in the enhanced model via plasticity synapses. Next, the network may be trained to generate the desired boundaries 1304, as shown in FIG. 13C. It should be noted that the augmented network may be trained simultaneously with the stimulus processing model 1302 (e. G., A non-illustrated network).

14A-14C illustrate another exemplary application of a proposed tagging method in a neural network with an over-complete representation, in accordance with certain aspects of the present disclosure. As shown in FIG. 14A, the neural network model may be trained to generate a plurality of desired classes (e.g., three different classes such as red, blue, and green). Each of the classes may be represented as a population of neurons in the output layer, as shown in Fig. 14A. For example, three neurons may be represented by blue, two neurons may be represented by red, and two neurons may be represented by green. 14B illustrates how an over-complete representation can cause a subset of the populations to encode the distance to the class average. For example, the purple stimulus (P1) may be represented over a subset of blue and red neuron populations (e.g., two red neurons and one blue neuron).

As shown in Fig. 14C, the over-complete representation may cause each of the purple stimuli (e.g., p1, p2, p3) to be represented by a mixture of neurons from the blue and red populations. The augmented network may be trained to generate the desired classification 1402. [

Certain aspects of the present disclosure may add new classes to the output classes of the neural network model using the proposed tagging method. As an example, a new class may be added to the neural network model as shown in FIG. In this example, the initial classification includes three output classes (e.g., red, green, and blue). The new class may be added to the outputs by defining additional output neurons and training the augmented network.

One alternative to the proposed tagging method is to train a neural block that implements a non-localization learning algorithm and then manually associate the outputs of the model to downstream blocks. This approach can quickly become cumbersome. This can be automated, for example, by testing the output of the model for a particular stimulus (e.g., a red ball) and evaluating the speech in the output layer of the model. However, this approach may not be simple if multiple neurons at the output layer exhibit stimulation (e.g., population encoding is used). The ability to evaluate output neurons and map them to stimulus classes can be complicated by itself. In contrast, the proposed method generates a mapping function using map training. Therefore, the proposed tagging method is robust to population encoding.

It should be noted that the methods presented herein may also be used to generate tags for a particular time pattern in the network. For example, in a debugger, an invalid state (which may, for example, have a certain time pattern) may be tagged using the proposed method. In general, the proposed tagging method may be used to identify a particular network pattern using STDP. In general, it should be noted that the augmented network 720 as shown in Fig. 7 may be connected to the output layer, the input layer and / or any intermediate layer of the stimulus processing network 710. [ The combination of the two networks may then be managed to generate the desired tags.

For certain aspects, there may be a one-to-many relationship between the tags generated by the augmented network 720 and the neural network model 710. For example, a tag may be generated as a "car ", a more generic tag may be generated (e.g., a vehicle) and / or a more specific tag may be generated (e.g., Honda).

Exemplary Alternative Solutions

According to certain aspects, the model discussed above may be augmented by sending management spikes directly to the output layer, as shown in FIG. In this example, the application of management spikes may enable static mapping between stimulus classes and output neurons representing the stimulus classes. According to certain aspects, a set of neurons carrying an administrative signal (inhibitory or excitatory) may be connected to the output layer. As shown in FIG. 16, management synapses may be connected to all output layer neurons. Output layer neurons required to map to a particular label may be connected to positive weighted synapses (excitatory) while other output layer neurons may be connected to negative weighted synapses (inhibitory).

Figure 17 illustrates exemplary timing of application of management signals, in accordance with certain aspects of the present disclosure. As shown, once the stimulus is presented (at t0), a management signal is sent to the network (at t1). The management neuron generates a positive management signal and (optionally) negative management signals for the output layer neurons (and tl '). These management inputs do not cause spikes in the output layer neurons alone, but optionally (at time t2) generate a positive bias for speech for the desired output layer neuron while optionally generating a negative bias for the utterance of other neurons. The amount of positive and / or negative bias can be controlled through synapse weights.

The effect of such management is shown in Fig. As shown, the positive bias can bring the desired output layer neurons (neurons X in the example shown) closer to the firing threshold. Similarly, an optional negative bias may bring the other output layer neurons (Y and Z) further below the threshold. While this management "subthreshold" bias does not cause the spike itself, when receiving a network input, it helps to overcome the effects of randomization in the class-to-output layer neuron mapping, It may also help to ensure that only X keeps Y and Z below the ignition threshold while crossing the ignition threshold.

As shown in Figs. 19 and 20, the STDP rules described above may also be applied to adjust the weights of management synapses. As shown in FIG. 20A, the positive management bias may be reduced when an accurate output is observed. On the other hand, the negative management may be increased or otherwise decreased for incorrect output, as shown in FIG. 20B. As discussed above, the STDP rules may cause management to be turned off once the network learns. In some cases, the duration for applying the management input (e.g., t1 to t1 'shown in FIG. 18) may be adjusted based on network performance.

FIG. 21 illustrates an exemplary implementation 2100 of the above-described method for tagging classes in a neural system using general purpose processor 2102, in accordance with certain aspects of this disclosure. (Neural signals), synapse weights, and system parameters associated with the computational network (neural network) may be stored in the memory block 2104 while the associated instructions executing in the general purpose processor 2102 may be stored in the program memory 2106. < / RTI > In one aspect of the present disclosure, the instructions loaded into the general purpose processor 2102 identify a first network comprising one or more indexed classes of nodes; And code for determining one or more tags for one or more classes of nodes regardless of their indexing.

22 depicts a block diagram of a memory 2202 in accordance with certain aspects of the present disclosure with separate (distributed) processing units (neural processors) 2206 of an arithmetic network (neural network) Figure 22 illustrates an exemplary implementation 2200 of the above method for tagging classes in a neural system that may be interfaced. (Neural signals), synaptic weights, and system parameters associated with the computational network (neural network) may be stored in the memory 2202 and the connection (s) of the interconnect network 2204 from the memory 2202, (Neural processor) 2206 via the processing unit (s) In one aspect of the present disclosure, processing unit 2206 identifies a first network comprising one or more indexed classes of nodes and determines one or more tags for one or more classes of nodes, regardless of their indexing .

23 illustrates an example of the above-described method for tagging classes in a neural system based on distributed weighted memories 2302 and distributed processing units (neural processors) 2304, according to certain aspects of the present disclosure 0.0 > 2300 < / RTI > 23, one memory bank 2302 may be directly interfaced with a one processing unit 2304 of a computational network (neural network), where the memory bank 2302 is connected to its processing unit ) 2304, neural signals, synaptic weights, and system parameters. In one aspect of the present disclosure, the processing unit 2304 identifies a first network comprising one or more indexed classes of nodes, and determines one or more tags for one or more classes of nodes, regardless of their indexing .

24 illustrates an exemplary implementation of a neural network 2400 in accordance with certain aspects of the present disclosure. As shown in FIG. 24, the neural network 2400 may include a plurality of local processing units 2402 that may perform various operations of the methods described above. Each processing unit 2402 may include a local state memory 2404 and a local parameter memory 2406 that store the parameters of the neural network. In addition, the processing unit 2402 may include a memory 2408 having a local (neuron) model program, a memory 2410 having a local learning program, and a local connection memory 2412. 24, each local processing unit 2402 includes a unit 2414 for configuration processing, which may provide a configuration for the local memories of the local processing unit, and a local processing unit 2402 ) Routing connection processing elements 2416 that provide routing between the routing access processing elements 2416 and the routing access processing elements 2416. [

According to certain aspects of the present disclosure, operations 800 shown in FIG. 8 may be performed in hardware, for example, by one or more processing units 2402 from FIG.

The various operations of the above-described methods may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and / or software component (s) and / or module (s), including, but not limited to, circuitry, an application specific integrated circuit (ASIC) In general, when the operations depicted in the Figures are present, they may have corresponding relative means-plus-function components with similar numbering. For example, operations 800 shown in Figure 8 correspond to components 800A shown in Figure 8A.

As one example, the means for identifying, determining, enhancing, connecting, and / or training may be a processing element such as a general purpose processor or a special purpose processor such as a digital signal processor (DSP), an ASIC or the like.

As used herein, a phrase referring to "at least one of a list of items" refers to any combination of the items, including single members. As an example, "at least one of a, b, or c" is intended to cover a, b, c, a-b, a-c, b-c, and a-b-c.

The various operations of the above-described methods may be performed by any suitable means capable of performing the operations, such as various hardware and / or software component (s), circuits, and / or module (s). In general, any of the operations shown in the drawings may be performed by corresponding functional means capable of performing the operations.

The various illustrative logical blocks, modules, and circuits described in connection with the disclosure may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array signal (FPGA) Logic devices (PLDs), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but, in the alternative, the processor may be any commercially available processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. For example, means for identifying, determining, reasoning, and updating means may be any suitable processing element such as a processor or the like.

The steps of a method or algorithm described in connection with the present disclosure may be embodied directly in hardware, in a software module executed by a processor, or in a combination of both. The software module may reside in any form of storage medium known in the art. Some examples of storage media that may be used include random access memory (RAM), read only memory (ROM), flash memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, A software module may comprise a single instruction or multiple instructions and may be distributed across several different code segments, between different programs, and across multiple storage media. The storage medium may be coupled to the processor such that the processor can read information from, and write information to, the storage medium. Alternatively, the storage medium may be integral to the processor.

The methods disclosed herein include one or more steps or actions for achieving the described method. The method steps and / or actions may be interchanged without departing from the scope of the claims. That is, the order and / or use of certain steps and / or actions may be modified without departing from the scope of the claims, unless a specific order of steps or actions is specified.

The functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored or transmitted on one or more instructions or code as computer readable media. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. The storage medium may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, Or any other medium that can be used to store or store data and be accessed by a computer. Also, any connection is properly termed a computer readable medium. For example, software may be transmitted from a web site, server, or other remote source using wireless technologies such as coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or infrared (IR) Wireless technologies such as coaxial cable, fiber optic cable, twisted pair cable, DSL, or infrared, radio, and microwave are included in the definition of the medium. As used herein, a disk and a disc include a compact disk (CD), a laser disk, an optical disk, a digital versatile disk (DVD), a floppy disk and a Blu-ray® disk, Disks typically reproduce data magnetically, while discs use lasers to optically reproduce data. Thus, in some aspects, the computer-readable medium may comprise a non-transitory computer readable medium (e.g., a type of medium). Additionally, for other aspects, the computer-readable medium may comprise a temporary computer-readable medium (e.g., a signal). Combinations of the above should also be included within the scope of computer readable media.

Accordingly, certain aspects may include a computer program product for performing the operations set forth herein. For example, such a computer program product may include a computer-readable medium having stored (and / or encoded) instructions for execution by one or more processors to perform the operations described herein Do. In certain aspects, the computer program product may comprise a packaging material.

The software or commands may also be transmitted on a transmission medium. If software is transmitted from a web site, server, or other remote source using, for example, wireless technologies such as coaxial cable, fiber optic cable, twisted pair cable, digital subscriber line (DSL), or infrared, wireless, and microwave, Wireless technologies such as cable, fiber optic cable, twisted pair, DSL, or infrared, radio, and microwave are included in the definition of the transmission medium.

In addition, modules and / or other suitable means for performing the methods and techniques described herein may be recognized and / or used by a user terminal and / or base station, if applicable, downloaded and / Should be. For example, such a device may be coupled to a server to facilitate transmission of means for performing the methods described herein. Alternatively, the various methods described herein may be provided through storage means (e.g., a RAM, ROM, a compact disc (CD) or a physical storage medium such as a floppy disc, etc.) The user terminal and / or the base station may obtain various methods. Moreover, any other suitable technique for providing the devices and methods described herein may be utilized.

It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes, and variations may be made in the arrangement, operation and details of the above-described methods and apparatus without departing from the scope of the claims.

While the foregoing is directed to aspects of the present disclosure, other aspects and further aspects of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims (34)

Identifying a first network comprising one or more indexed classes of artificial neurons; And
Determining one or more tags for one or more classes of artificial neurons independently of its indexing. The method according to claim 1,
Wherein determining the one or more tags for one or more classes of artificial neurons comprises:
Augmenting the first network into a second network comprising one or more artificial neurons, wherein each neuron in the second network corresponds to a tag; augmenting the first network;
Connecting each of the one or more classes of neurons to all of the neurons in the second network with one or more fictitious connections; And
Training each of the neurons in the second network using the map learning algorithm to train the one or more fictitious connections so that the neurons in the second network exhibit a particular class of the first network regardless of its index. 3. The method of claim 2,
Wherein the second network comprises a single layer of artificial neurons. 3. The method of claim 2,
Wherein the map learning algorithm utilizes spike timing dependent plasticity (STDP). 3. The method of claim 2,
Wherein training one or more of the fictitious connections comprises:
Transmitting a known sequence of classes to the first network;
Enforcing one or more artificial neurons of the second network to spike for each particular class;
Inhibiting spikes at one or more artificial neurons of the second network to one or more other classes; And
Adjusting the weights of the one or more fictitious connections based on spikes in the first network and the second network. 3. The method of claim 2,
Wherein an augmented network is connected to the output layer of the first network. The method according to claim 1,
Wherein one or more classes of artificial neurons are determined using a non-learning algorithm. The method according to claim 1,
Wherein one of the indexed classes comprises a specific time pattern. The method according to claim 1,
Each of the indexed classes of artificial neurons corresponding to one or more tags. The method according to claim 1,
Wherein the one or more tags are used to connect the first network to the device. The method according to claim 1,
Wherein the one or more tags are used to determine boundaries between different classes of artificial neurons. The method according to claim 1,
Wherein the one or more tags are used to fuse one or more of the classes of artificial neurons. The method according to claim 1,
Wherein determining the one or more tags for one or more classes of artificial neurons comprises:
Augmenting the first network into a second network comprising one or more artificial neurons, wherein each neuron in the second network corresponds to a tag; augmenting the first network;
Connecting each of the one or more classes of neurons to all of the neurons in the second network with one or more fictitious connections; And
Providing management bias signals to one or more classes of the neurons via the plastic connections to impose a desired mapping between classes and output layer neurons. 14. The method of claim 13,
Wherein providing the management bias signals comprises:
Providing positive management signals below an ignition threshold to generate a bias for an ignition for a desired output layer neuron. 15. The method of claim 14,
Wherein providing the management bias signals comprises:
Further comprising providing negative management signals to generate a bias to prevent speech to unwanted output layer neurons. 14. The method of claim 13,
Further comprising adjusting the weights of the management signals such that the level of the management bias is adjusted according to the difference between the desired network output and the actual network output at the output layer neurons. Means for identifying a first network comprising one or more indexed classes of artificial neurons; And
Means for determining one or more tags for one or more classes of artificial neurons independent of their indexing. 18. The method of claim 17,
Wherein the means for determining the one or more tags for one or more classes of artificial neurons comprises:
Means for augmenting the first network into a second network comprising one or more artificial neurons, each neuron in the second network corresponding to a tag; means for augmenting the first network;
Means for connecting each of the one or more classes of neurons to all of the neurons in the second network with one or more fictitious connections; And
Wherein each neuron in the second network trains the one or more fictitious connections using a guidance learning algorithm to indicate a particular class of the first network independent of its index. 19. The method of claim 18,
Wherein the second network comprises a single layer of artificial neurons. 19. The method of claim 18,
Wherein the map learning algorithm utilizes spike timing dependent plasticity (STDP). 19. The method of claim 18,
Wherein the means for training the one or more plastic connections comprises:
Means for transmitting a known sequence of classes to the first network;
Enforcing one or more artificial neurons of the second network to spike for each particular class;
Means for inhibiting spikes in one or more artificial neurons of the second network for one or more other classes; And
And means for adjusting a weight of the one or more fictitious connections based on spikes in the first network and the second network. 19. The method of claim 18,
And an enhanced network is connected to the output layer of the first network. 18. The method of claim 17,
Wherein one or more classes of artificial neurons are determined using a non-learning learning algorithm. 18. The method of claim 17,
Wherein one of the indexed classes comprises a specific time pattern. 18. The method of claim 17,
Each of the indexed classes of artificial neurons corresponding to one or more tags. 18. The method of claim 17,
Wherein the one or more tags are used to connect the first network to the device. 18. The method of claim 17,
Wherein the one or more tags are used to determine boundaries between different classes of artificial neurons. 18. The method of claim 17,
Wherein the one or more tags are used to fuse one or more of the classes of artificial neurons. 18. The method of claim 17,
Wherein the means for determining the one or more tags for one or more classes of artificial neurons comprises:
Means for augmenting the first network into a second network comprising one or more artificial neurons, each neuron in the second network corresponding to a tag; means for augmenting the first network;
Means for connecting each of the one or more classes of neurons to all of the neurons in the second network with one or more fictitious connections; And
And means for providing management bias signals to one or more classes of the neurons via the plastic connections to impose a desired mapping between classes and output layer neurons. 30. The method of claim 29,
Wherein the means for providing the management bias signals comprises:
And means for providing positive management signals below an ignition threshold to generate a bias for an ignition for a desired output layer neuron. 31. The method of claim 30,
Wherein the means for providing the management bias signals comprises:
Further comprising means for providing negative management signals to generate a bias to prevent speech to undesired output layer neurons. 30. The method of claim 29,
And means for adjusting weights of the management signals such that the level of the management bias is adjusted in accordance with the difference between the desired network output and the actual network output at the output layer neurons. At least one processor configured to identify a first network comprising one or more indexed classes of artificial neurons and to determine one or more tags for one or more classes of artificial neurons irrespective of their indexing; And
And a memory coupled to the at least one processor. 23. A program product comprising a computer readable medium having stored thereon instructions,
The instructions,
Identify a first network comprising one or more indexed classes of artificial neurons; And
And determine one or more tags for one or more classes of artificial neurons irrespective of its indexing.

Images