KR20160060382A - Stacked semiconductor package - Google Patents

Abstract

A stacked semiconductor package comprises a first semiconductor chip, and a connection pad formed around the first semiconductor chip. The stacked semiconductor package comprises: a substrate on which the first semiconductor chip is mounted; a stack post electrically connected to the connection pad wherein at least two balls are stacked on the stack post; and a second semiconductor chip electrically connected to the stack post and stacked on the first semiconductor chip. Therefore, the stacked package can be manufactured by a simple process.

Description

[0001] STACKED SEMICONDUCTOR PACKAGE [0002]

The present invention relates to a stacked semiconductor package, and more particularly to a stacked semiconductor package using solder balls.

In recent years, semiconductor chip packages have been incorporating various new technologies to package such chips in line with the trend of thinning and miniaturization of semiconductor chips.

One of them is a stacked package technology in which semiconductor chips are stacked in a plurality of layers. In general, when a package using a plurality of semiconductor chips is formed in a planar manner, the area of the semiconductor package is increased, and external connection terminals such as a BGA are required to be formed. Therefore, not only the overall thickness of the product is large, There has been a disadvantage in that it is necessary to use electric wiring of many paths in signal exchange.

However, when the semiconductor chips are stacked and packaged, only one portion of the external connection terminal needs to be formed in the stacked package. Therefore, even if the thickness of the semiconductor chip itself increases, the thickness of the entire packaging can be rather reduced, By stacking the chips between the chips to exchange signals, data processing can be performed more quickly and reliably.

A stacked semiconductor package has many advantages. However, in order to realize such a stacked semiconductor packaging, an electrical connection path between the substrate on which the semiconductor chip is mounted and the upper chip must be formed. It is a reality that a method of forming such an electrical connection path is not easy.

Accordingly, it is an object of the present invention to provide a stacked semiconductor package which forms a laminated post using a solder ball.

 According to another aspect of the present invention, there is provided a stacked semiconductor package including a first semiconductor chip, a connection pad formed around the first semiconductor chip, And a second semiconductor chip electrically connected to the connection pad, the second semiconductor chip being electrically connected to the lamination posts, and stacked on the first semiconductor chip, the lamination posts being formed by stacking at least two balls.

In one embodiment, the first semiconductor chip may be a flip chip.

In one embodiment, the laminated posts may be formed by stacking at least three balls.

In one embodiment, the laminated posts may include an upper laminated ball and a lower laminated ball.

In one embodiment, a lower laminated ball of the laminated posts is formed first on a pad of the substrate, and an upper laminated ball of the laminated posts is formed below the second semiconductor chip, The upper laminated ball and the lower laminated ball are stacked.

In one embodiment, the lower laminated ball and the upper laminated ball of the laminated posts are stacked on the pad of the substrate and formed first.

In one embodiment, the laminated posts may include an upper laminated ball, at least one connected laminated ball, and a lower laminated ball.

According to the present invention described above, a semiconductor laminated package can be manufactured by a simple and easy method by forming at least two balls in a laminated shape and electrically connecting upper and lower portions.

Further, by controlling the number of balls forming the posts according to the size of the ball or the size and shape of the semiconductor chip, it is possible to form the laminated posts in accordance with the characteristics of the semiconductor package.

1 is a cross-sectional view showing a laminated semiconductor package according to an embodiment of the present invention.
2 is a cross-sectional view illustrating a method of forming a laminated semiconductor package according to the embodiment of FIG.
3 is a cross-sectional view illustrating a method of forming a laminated semiconductor package according to the embodiment of FIG.
4 is a cross-sectional view showing a laminated semiconductor package according to another embodiment of the present invention.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It is to be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but on the contrary, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

Like reference numerals are used for like elements in describing each drawing. In the accompanying drawings, the dimensions of the structures are enlarged to illustrate the present invention in order to clarify the present invention.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component. The singular expressions include plural expressions unless the context clearly dictates otherwise.

In this application, the terms "comprises", "having", and the like are used to specify that a feature, a number, a step, an operation, an element, a part or a combination thereof is described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in more detail with reference to the accompanying drawings.

1 is a cross-sectional view showing a laminated semiconductor package according to an embodiment of the present invention.

1, a laminated semiconductor package 1000 according to an embodiment of the present invention includes a first semiconductor chip 110 and a connection pad 230 formed around the first semiconductor chip 110 A laminate post 400 electrically connected to the connection pad 230 and formed by stacking at least two balls 410 and 420, And a second semiconductor chip 310 electrically connected to the laminated posts 400 and stacked on the first semiconductor chip 110.

The first semiconductor chip 110 may include a flip chip. The first semiconductor chip 110 is electrically connected to the substrate 210 through a plurality of bumps 130. The substrate 210 includes a rewiring pattern, which is also electrically connected to the connection pad 230. The connection pad 230 may be part of a rewiring pattern formed in the substrate 210. Accordingly, the connection pads 230 are electrically connected to the first semiconductor chip 110, and an object electrically connected to the connection pad 230 can be electrically connected to the first semiconductor chip 110 .

The second semiconductor chip 310 is located on the first semiconductor chip 110. The second semiconductor chip 310 may be a package including a semiconductor chip as well as a semiconductor chip. The second semiconductor chip 310 is formed on the first semiconductor chip 110 and the package including the first semiconductor chip 110 and the second semiconductor chip 310 is electrically connected through the electrical connection therebetween. .

A laminated post (400) electrically connected to the connection pad (230) is formed on a side surface of the first semiconductor chip (110). The laminated posts 400 are formed by stacking at least two balls 410 and 420. The balls 410 and 420 may be composed of an upper laminated ball 410 and a lower laminated ball 420. The upper laminated ball 410 is electrically connected to the pad 320 of the second semiconductor chip 310 to connect the second semiconductor chip 310 and the lower laminated ball 420 is electrically connected to the substrate 210 And is electrically connected to the substrate 210 and the first semiconductor chip 110. The first semiconductor chip 110 is electrically connected to the connection pad 230 of the first semiconductor chip 110. [

The upper laminated ball 410 and the lower laminated ball 420 may be formed of a solder ball, or may be formed in a ball shape as another conductive material. In addition, the upper laminated ball 410 and the lower laminated ball 420 may include solder in a part to be partially connected and other metal in a part corresponding to the body of the ball. When the upper laminated ball 410 or the lower laminated ball 420 partially or wholly includes solder, the upper and lower laminated balls 410 and 420 are disposed and then reflowed through the reflow process or the like. 410 and 420 can be further strengthened.

The laminated posts 400 including the balls 410 and 420 are disposed on the side surfaces of the first semiconductor chip 110 and the first semiconductor chip 110, 310 are electrically connected to each other. Conventionally, TMV (Through Mold Via) or LDP (Laser Drilling Process) method, which forms a mold on a side surface, forms a via in a molding and then fills a conductive material or the like and forms an electrical connection between the upper and lower sides of the package, When a plurality of balls 410 and 420 are used as in the embodiment, electrical connection between the top and bottom of the package can be obtained through a simpler process, thereby simplifying the process and reducing the cost.

2 is a cross-sectional view illustrating a method of forming a laminated semiconductor package according to the embodiment of FIG.

2, the upper laminated ball 410 and the lower laminated ball 420 are separately formed in the laminated post 400, and the second semiconductor chip 310 located on the upper part is formed on the substrate 210 The laminated posts 400 are formed.

The upper laminated ball 410 is first formed on the pad 320 of the second semiconductor chip 310 and the lower laminated ball 420 is formed on the connection pad 230 of the substrate 210. [ As shown in FIG. Although the upper laminated ball 410 and the lower laminated ball 420 are shown one by one in the present embodiment, the upper laminated ball 410 and the lower laminated ball 420 may be formed of several layers depending on the size of the ball and the height required in the package. The balls may be formed in succession. In some cases, the upper laminated ball may be formed of a single ball, and the lower laminated ball may be formed by stacking two balls.

The first semiconductor chip 310 is mounted on the substrate 210, and the upper laminated ball 410 and the lower laminated ball 420 are laminated. When the upper and lower laminated balls 410 and 420 include solder, the upper laminated ball 410 and the lower laminated ball 420 may be more firmly coupled through a separate reflow process or the like.

3 is a cross-sectional view illustrating a method of forming a laminated semiconductor package according to the embodiment of FIG.

Referring to FIG. 3, the laminated posts 400 are formed on the connection pads 230 on the substrate 210 together with the upper laminated balls 410 and the lower laminated balls 420. The second semiconductor chip 310 located on the upper side is electrically connected to the laminated posts 400 while being mounted on the substrate 210.

In the present embodiment, the upper laminated ball 410 is formed on the connection pad 230 of the substrate 210 together with the lower laminated ball 420. Although the upper laminated ball 410 and the lower laminated ball 420 are shown one by one in the present embodiment, the upper laminated ball 410 and the lower laminated ball 420 may be formed of several layers depending on the size of the ball and the height required in the package. The balls may be formed in succession. In some cases, three or more laminated balls may be formed by stacking two balls.

The upper laminated ball 410 and the lower laminated ball 420 are already laminated to each other to form a laminated post 400. The laminated posts 400 are formed on the connection pads 230 of the substrate 210 and are electrically connected to the pads 320 of the second semiconductor chip 310.

4 is a cross-sectional view showing a laminated semiconductor package according to another embodiment of the present invention.

4, substantially the same as the configuration of the laminated semiconductor package 1000 of the embodiment of FIG. 1, except that the laminated posts 500 of the laminated semiconductor package 2000 of this embodiment are formed of three or more laminated balls Therefore, the same reference numerals are used for the same constituent elements, and redundant explanations are omitted.

The laminated posts 500 include an upper laminated ball 510, a lower laminated ball 520, and an extended laminated ball 530. The size of the ball may not be constant. For example, the upper laminated ball 510 and the lower laminated ball 520, each having a large diameter and directly connected to the respective pads, may be a smaller-sized ball. The size of the balls is gradually increased in the order of the upper laminated ball 510, the extended laminated ball 530 and the lower laminated ball 520 in order to stabilize the structure of the package, Shape.

When the laminated posts 500 are first formed as in the embodiment of FIG. 3 and the second semiconductor chip 310 is mounted, the structural stability of the laminated posts 500 may be required. In this case, the size of the upper laminated ball 510, the extended laminated ball 530 and the lower laminated ball 520 of the laminated post 500 may be gradually increased to achieve structural stability.

As described above, according to the embodiment of the present invention, it is possible to fabricate a semiconductor laminated package by a simple and easy method by forming at least two balls in a laminated shape and electrically connecting the upper and lower balls.

Further, by controlling the number of balls forming the posts according to the size of the ball or the size and shape of the semiconductor chip, it is possible to form the laminated posts in accordance with the characteristics of the semiconductor package.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. You will understand.

1000: Laminated semiconductor package
110: first semiconductor chip 210: substrate
310: second semiconductor chip 400: laminated post
2000: Laminated semiconductor package
500: laminated post

Claims (7)

A first semiconductor chip;
And a connection pad formed on the periphery of the first semiconductor chip, the substrate mounting the first semiconductor chip;
A laminated post electrically connected to the connection pad and formed by stacking at least two balls; And
And a second semiconductor chip electrically connected to the laminated posts and stacked on the first semiconductor chip. The method according to claim 1,
Wherein the first semiconductor chip is a flip chip. The method according to claim 1,
Wherein the laminated posts are formed by stacking at least three balls. The method according to claim 1,
Wherein the laminated posts comprise an upper laminated ball and a lower laminated ball. 5. The method of claim 4,
Wherein a lower laminated ball of the laminated posts is first formed on a pad of the substrate, and an upper laminated ball of the laminated posts is formed under the second semiconductor chip, and in the step of mounting the second semiconductor chip, Wherein the balls and the lower stacked balls are stacked. 5. The method of claim 4,
Wherein the lower stacked balls and the upper stacked balls of the stacked posts are stacked and formed on the pad of the substrate. The method according to claim 1,
Wherein the laminated posts comprise an upper laminated ball, at least one connected laminated ball, and a lower laminated ball.

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