KR20150088114A - Clock and data recovery method and apparatus thereof - Google Patents

Abstract

Embodiments of the present invention relate to a method and apparatus for recovering clock and data from a digital input signal and an apparatus for recovering clock and data from a digital input signal in accordance with an embodiment of the present invention includes: A clock recovery unit for recovering a clock having a frequency of M times the frequency of the digital input signal using a frequency division ratio M that varies according to a transmission rate; And a data recovery unit for dividing the recovered clock received from the clock recovery unit by 1 / M to recover data from the digital input signal. According to embodiments of the present invention, even if a digital input signal having a transmission rate lower than the maximum recoverable clock frequency is received, the clock and data can be recovered therefrom.

Description

[0001] CLOCK AND DATA RECOVERY METHOD AND APPARATUS THEREOF [0002]

Embodiments of the present invention are directed to a method and apparatus for recovering clock and data from a digital input signal.

The clock and data restoration circuit restores the clock synchronized with the received digital input signal from the digital input signal and restores the digital data using the restored clock. Clock and data restoration circuits are widely used for LAN, wired / wireless communication, optical communication, disk drive data transmission, display data transmission, and chip-to-chip data transmission for high-speed data transmission.

In the conventional clock and data recovery circuit, the frequency of the recovered clock is equal to or smaller than the transmission speed of the received digital input signal. For example, when using a full rate phase detector, the recovered clock frequency is equal to the transmission rate of the received digital input signal. When a half rate phase detector is used, the frequency of the recovered clock is equal to half of the transmission rate of the received digital input signal.

For example, if the transmission rate of the received digital input signal is 1 Gbps, a clock with a frequency of 1 GHz is restored when a full rate phase detector is used, and a clock with a frequency of 500 MHz is used when a half rate phase detector is used Restored. Therefore, assuming that the frequency range of the clock that can be recovered by the clock and data recovery circuit is limited from 1 GHz to 4 GHz, the transfer rate of the recoverable digital input signal when using the full rate phase detector is from 1 Gbps to 4 Gbps When using a half rate phase detector, the recoverable digital input signal is limited to a transmission rate of 2 Gbps to 8 Gbps.

That is, since the transmission speed of the digital input signal is determined by the frequency range of the recoverable clock and the frequency range of the recoverable clock is limited, it is difficult for the clock and data recovery circuit to have the wide band characteristic.

Thus, embodiments of the present invention provide a clock and data recovery scheme with wideband characteristics.

For this purpose, an apparatus for recovering clock and data from a digital input signal according to an embodiment of the present invention includes a frequency divider for dividing a frequency of M A clock recovery unit for recovering a clock having a frequency of double; And a data recovery unit for dividing the recovered clock received from the clock recovery unit by 1 / M to recover data from the digital input signal.

Meanwhile, a method for recovering clock and data from a digital input signal according to an embodiment of the present invention includes: dividing the frequency of the digital input signal by M times Recovering a clock having a frequency of < RTI ID = 0.0 > And restoring data from the digital input signal by dividing the recovered clock by 1 / M.

According to embodiments of the present invention, a clock and data recovery circuit having wide band characteristics can be implemented. According to embodiments of the present invention, even if a digital input signal having a transmission rate lower than the maximum recoverable clock frequency is received, the clock and data can be recovered therefrom.

1 is a block diagram illustrating a clock and data recovery apparatus according to an embodiment of the present invention;
2 is a block diagram illustrating a phase detector in accordance with one embodiment of the present invention.
3 is a diagram showing a relationship between input / output signals and recovered digital data in a phase detector according to an embodiment of the present invention,
FIG. 4 is an exemplary diagram showing a measured waveform of recovered clock and digital data according to an embodiment of the present invention;
5 is a flowchart illustrating a clock and data restoring process according to an embodiment of the present invention.

In the following description of the embodiments of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

As described above, the data transfer rate is limited according to the frequency range of the recoverable clock in the clock and data recovery circuit. Therefore, according to the conventional method, there is a problem that a clock and a data restoration circuit must be applied according to a data transmission speed or a data transmission speed according to a frequency range of a recoverable clock in a clock and data restoration circuit.

Various embodiments of the present invention provide a clock and data recovery circuit having broadband characteristics.

To this end, in various embodiments of the present invention, the clock is restored by using the division ratio M that varies according to the transmission rate of the digital input signal, and the restored clock is divided (1 / M) to restore the data. In other words, in various embodiments of the present invention, The clock is restored so as to have a frequency M times higher than the transmission speed of the input signal.

Accordingly, the clock and data recovery apparatus according to various embodiments of the present invention can recover the clock from the digital input signal, even if the transmission rate of the digital input signal has any range smaller than the recoverable maximum clock frequency. At the time of digital data restoration, the original data can be restored by dividing (1 / M) the M-times recovered clock.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram illustrating a clock and data recovery apparatus according to an embodiment of the present invention.

1, a clock and data recovery apparatus according to an embodiment of the present invention includes a clock recovery unit including a first loop 100, a second loop 200, and a loop selector 300, And a restoration unit (400).

The clock recovery unit may recover the clock based on the reference clock and the digital input signal. In an embodiment of the present invention, the clock recovery unit may recover a clock having a frequency M times as high as the frequency of the digital input signal, using a frequency division ratio M that varies according to the digital input signal. The clock recovery unit includes a first loop 100 for frequency fixing, a second loop 200 for clock recovery, and a loop selection unit 200 for selecting the first loop 100 or the second loop 200 according to whether the frequency is fixed or not. (300). ≪ / RTI >

The first loop 100 can fix the frequency of the feedback clock based on the frequency difference of the clocks divided by the division ratio M of at least one of the reference clock and the feedback clock.

For example, the first loop 100 may receive an M divided reference clock and an unfocused feedback clock, and may fix the frequency of the feedback clock based on their frequency difference. Alternatively, the first loop 100 may receive an unbuffered reference clock and a 1 / M divided feedback clock, and may fix the frequency of the feedback clock based on their frequency difference.

The second loop 200 shares a feedback loop with the first loop 100 and receives a digital input signal and a feedback clock as inputs and generates a frequency M times as high as the frequency of the digital input signal Lt; / RTI >

The loop selector 300 can select either the first loop 100 or the second loop 200 according to whether the frequency is fixed or not. For example, when the frequency is not fixed, the loop selector 300 may select the first loop 100 to perform frequency locking. When the frequency is fixed, the second loop 200 may be selected to restore the clock having the M times frequency.

As described above, the clock and data restoring apparatus according to the embodiment of the present invention can use the division ratio M that varies according to the transmission rate of the digital input signal, even if a digital input signal having a certain transmission rate is received, It is possible to recover a clock having a frequency of M times the frequency of the digital input signal.

Hereinafter, the configurations of the first loop 100, the second loop 200, and the loop selector 300 will be described in more detail.

In one embodiment of the present invention, the first loop 100 includes a first divider 112, a second divider 114, a frequency-phase detector 120, a first charge pump 130, An oscillator 140, a loop filter 150, and a voltage-controlled oscillator 160.

The first divider 112 and the second divider 114 are used to divide the input clock according to the variable division ratio M. [ The first divider 112 may be used to M divide the reference clock and the second divider 114 may be used to divide the feedback clock by 1 / M. At least one of the first divider 112 and the second divider 114 may be omitted.

The frequency-phase detector 120 may detect the frequency difference of the input clocks to generate a first control signal, and output the generated first control signal to the first charge pump 130. The clocks input to the frequency-to-phase detector 120 may be a non-divided reference clock and a 1 / M frequency-divided clock in the second divider 114. [ Alternatively, the clocks input to the frequency-to-phase detector 120 may be divided into M reference clocks divided in the first divider 112 and clocks restored in the second loop 200 (divided in the second divider 114) Lt; / RTI > recovery clock).

The first charge pump 130 may generate a first charge / discharge current signal in response to a first control signal received from the frequency-phase detector 120.

The multiplexer 140 may or may not deliver the first charge / discharge current signal to the loop filter 150 based on the loop selection signal. The multiplexer 140 selects either the first loop 100 or the second loop 200 based on the loop selection signal received from the frequency lock detector 340, 100), the multiplexer 140 can deliver the first charge / discharge current signal to the loop filter 150. [0035]

The loop filter 150 is charged / discharged according to the first charge / discharge current signal, and generates a first control voltage corresponding to the first charge / discharge current signal and transfers the first control voltage to the voltage adjustment oscillator 160.

The voltage-controlled oscillator 160 generates a frequency-locked feedback clock in response to the first control voltage received from the loop filter 150.

The first loop 100 has a frequency obtained by dividing the frequency of the recovered clock by the division ratio of the second divider 114 and a frequency obtained by dividing the frequency of the reference clock by the division ratio of the first divider 112 Respectively. In other words, the first loop 100 initializes the frequency of the recovered clock to a desired frequency according to the frequency of the reference clock, the frequency division ratio of the first frequency divider 112, and the frequency division ratio of the second frequency divider 114 It plays a role.

In one embodiment of the present invention, the second loop 200 includes at least one of a phase detector 220, a second charge pump 230, a multiplexer 140, a loop filter 150 and a voltage regulating oscillator 160 One can be included. In one embodiment, the second loop 200 shares a feedback loop with the first loop 100 and includes a multiplexer 140, a loop filter 150, and a voltage regulation oscillator 160 in the shared feedback line. Can be located.

The phase detector 220 receives as input the digital input signal and the clock recovered by M times in the first loop 100, and detects the phase difference therebetween. Then, the second control signal may be generated based on the detected phase difference, and the generated second control signal may be output to the second charge pump 230.

The second charge pump 230 may generate a second charge / discharge current signal in response to a second control signal received from the phase detector 220.

The multiplexer 140 may or may not deliver the second charge / discharge current signal to the loop filter 150 based on the loop selection signal. As described above, the multiplexer 140 selects either the first loop 100 or the second loop 200 based on the loop selection signal received from the frequency lock detector 340, The multiplexer 140 may deliver the second charge / discharge current signal to the loop filter 150. The second charge /

The loop filter 150 is charged / discharged according to the second charge / discharge current signal and generates a second control voltage corresponding to the second charge / discharge current signal and transfers the second control voltage to the voltage adjustment oscillator 160.

The voltage adjustment oscillator 160 restores the clock having the M times frequency in response to the second control voltage received from the loop filter 150.

The frequency of the recovered clock in the second loop 200 may vary according to the type of the phase detector 220. [ For example, if the phase detector 220 is a full rate phase detector, the frequency of the recovered clock is equal to the transmission rate of the digital input signal, and if the phase detector 220 is a half rate phase detector, Equal to half the transmission rate of the input signal.

In the embodiments of the present invention, when the frequency of the recovered clock is a multiple of the transmission rate of the digital input signal, the phase detector 220 included in the second loop 200 detects the transmission speed of the digital input signal, And detects only the phase difference between the digital input signal and the recovered clock.

Thus, the frequency of the clock recovered in the second loop 200 may not be determined solely by the transmission rate of the digital input signal and the phase detector 220 used, but may be a multiple thereof.

In other words, in the embodiments of the present invention, by increasing the frequency division ratio of the first frequency divider 112 by M times or decreasing the frequency division ratio of the second frequency divider 114 by 1 / M times, , A frequency of M times the frequency of the digital input signal is used.

In one embodiment of the present invention, the loop selector 300 detects whether the frequency is fixed and generates a loop selection signal for selecting the first loop 100 or the second loop 200 based on whether the frequency is fixed or not And a multiplexer 140 for selecting the first loop 100 or the second loop 200 based on the loop selection signal received from the frequency lock detector 340 and the frequency lock detector 340 .

The frequency lock detector 340 may compare the frequency of the recovered clock and the reference clock, and may select the first loop 100 or the second loop 200 based on the comparison result. At this time, at least one of the clocks input to the frequency lock detector 340 may be divided according to a variable division ratio. For example, the frequency lock detector 340 may detect a frequency lock by inputting a reference clock divided by M by the first divider 112 and a restored clock received from the voltage adjustment oscillator 160 . Alternatively, the frequency lock detector 340 receives the reference clock (the signal not divided by the first divider 112) and the restored clock divided by 1 / M by the second divider 114, Or not.

As described above, the clock recovery unit according to an embodiment of the present invention restores a clock having a frequency of M times the frequency of the digital input signal. Therefore, at the time of digital data restoration, it is necessary to divide the clock recovered by M times by 1 / M.

To this end, the data recovery unit 400 according to the embodiment of the present invention divides the restored clock received from the clock recovery unit 1 / M and restores the digital data using the 1 / M frequency-divided clock. The data restoring unit 400 includes a third divider 410 for dividing the restored clock received from the clock recovery unit 1 / M and a data restoring circuit 410 for restoring data using the 1 / (420). The data restoration circuit 420 may be implemented by various conventional methods. For example, the data restoration circuit 420 may be implemented as a D flip-flop.

Meanwhile, although not shown in the figure, the control unit may further include a controller for determining the division ratio M based on a transmission rate of the digital input signal. That is, if a digital input signal is received, the control unit may measure the transmission rate of the digital input signal and determine the division ratio M based on the measured transmission rate. Then, the first to third frequency dividers 112, 114, and 410 are controlled according to the determined division ratio M so that a clock having a frequency of M times the digital input signal can be restored. At this time, the control unit increases the division ratio M as the transmission rate of the digital input signal decreases, and decreases the division ratio M as the transmission rate of the digital input signal increases.

According to embodiments of the present invention described above, it is possible to implement a clock and data recovery apparatus having a wide band characteristic.

For example, due to the characteristics of the voltage-controlled oscillator 160, it is assumed that the frequency range of the recoverable clock is 1 GHz to 4 GHz. Assuming that the phase detector 220 is a full rat phase detector, the transmission speed range of the digital input signal that can be recovered by the clock and data recovery circuit when the division ratio M = 1 is 1 Gbps to 4 Gbps.

If the division ratio of the first divider 112 is set to 4 (or the division ratio of the second divider 114 is set to 1/4) and the division ratio of the third divider 410 is set to 1/4 . In this case, the transmission speed range of the recoverable digital input signal in the clock and data recovery circuit according to the embodiments of the present invention is 250 Mbps to 1 Gbps.

If the division ratio of the first divider 112 is 16 (or the dividing ratio of the second divider 114 is 1/16) and the division ratio of the third divider 410 is 1/16 . In this case, the transmission speed range of the recoverable digital input signal in the clock and data recovery circuit according to the embodiments of the present invention is 62.5 Mbps to 250 Mbps.

That is, the clock and data recovery circuit according to the embodiments of the present invention can cover the transmission rate of the digital input signal widely by adjusting the division ratio M.

Hereinafter, with reference to FIG. 2 and FIG. 3, a description will be made of a data restoration result based on input / output signals in the phase detector 220 according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a phase detector 220 according to an embodiment of the present invention. FIG. 3 is a diagram illustrating a relationship between input / output signals in the phase detector 220 and recovered digital data. to be.

In Figure 2, as an example, a full rate phase detector is shown. The phase detector 220 may include an inverter 222, a first D flip flop 224a, a second D flip flop 224b, a first XOR circuit 226a and a second XOR circuit 226b .

In this configuration, a diagram when the division ratio M is set to 1 is shown in Fig. 3 (a). Referring to FIG. 3A, it can be seen that the transmission speed of the received digital input signal and the frequency of the recovered clock are the same, and the digital data is correctly restored from the digital input signal.

On the other hand, FIG. 3 (b) shows a diagram when the division ratio M is set to 2, that is, when the division ratio of the third division is 1/2. Referring to FIG. 3 (b), the clock having a frequency twice as high as the transmission speed of the received digital input signal is restored, but the digital data is restored properly.

However, as can be seen from the second up signal and the second down signal, since the gain of the phase detector 220 is reduced to 1/2, it is necessary to compensate the gain. To this end, various conventional methods for gain compensation can be applied. As an example, a method of doubling the gain of the second charge pump 230 may be applied. To this end, the control unit may adjust the gain of the second charge pump 230 in proportion to the division ratio.

On the other hand, FIG. 3 (c) shows a diagram when the division ratio M is set to 4, that is, when the division ratio of the third division is 1/4. Referring to (c) of FIG. 3, it can be seen that the clock having a frequency four times that of the received digital input signal is restored but the digital data is restored properly.

However, as is apparent from the second up signal and the second down signal, since the gain of the phase detector 220 is reduced to 1/4, it is necessary to compensate the gain.

4 is an exemplary diagram showing measured waveforms of recovered clock and digital data according to an embodiment of the present invention.

4 (a) shows the measured waveform when the division ratio M is set to 1, that is, when the division ratio of the third divider is 1. The used phase detector is assumed to be a full rate phase detector. Referring to FIG. 4A, the frequency of the recovered clock is 1 GHz, and the transmission speed of the restored digital data is 1 Gbps, indicating that the restoration has been properly performed.

4 (b) shows the measured waveform when the division ratio M is set to 2, that is, when the division ratio of the third divider 410 is 1/2. The used phase detector is assumed to be a full rate phase detector. Referring to FIG. 4B, it can be seen that the frequency of the recovered clock is 1 GHz, and the transmission speed of the recovered digital data is 500 Mbps.

5 is a flowchart illustrating a clock and data restoring process according to an embodiment of the present invention.

In step 501, the clock and data recovery apparatus proceeds to step 503 when a digital input signal is received.

In step 503, the clock and data recovery apparatus determines the division ratio M based on the transmission rate of the digital input signal, and then proceeds to step 505. [ As described above, the division ratio M can be determined so that a clock having a frequency M times as large as the frequency of the digital input signal is restored. In one embodiment, the division ratio M may be a natural number.

In step 505, the clock and data recovery apparatus divides at least one of the reference clock and the feedback clock according to the determined division ratio M.

In step 507, the clock and data recovery apparatus fixes the frequency of the feedback clock based on the frequency difference of the clocks in which at least one of the reference clock and the feedback clock is divided. For example, the clock and data recovery apparatus can divide the reference clock by M, or divide the feedback clock by 1 / M, and fix the frequency of the feedback clock based on the frequency difference therebetween.

In step 509, the clock and data recovery apparatus restores a clock having a frequency M times as high as the frequency of the digital input signal, based on the phase difference between the digital input signal and the feedback clock. As described above, the second loop 200 of the clock and data recovery apparatus detects only the phase difference without detecting the frequency difference. That is, the clock and data recovery apparatus can recover the clock having the M times frequency by using a kind of harmonic lock phenomenon.

In step 511, the clock and data recovery apparatus divides the restored clock by 1 / M to restore the data from the digital input signal.

At least one of the steps (501) to (511) may be omitted, and two or more steps may be performed simultaneously or at different times.

The embodiments of the invention described above may be implemented in any of a variety of ways. For example, embodiments of the present invention may be implemented using hardware, software, or a combination thereof. When implemented in software, it may be implemented as software running on one or more processors using various operating systems or platforms. Additionally, such software may be written using any of a number of suitable programming languages, and may also be compiled into machine code or intermediate code executable in a framework or virtual machine.

Also, when embodiments of the present invention are implemented on one or more processors, one or more programs for carrying out the methods of implementing the various embodiments of the invention discussed above may be stored on a processor readable medium (e.g., memory, A floppy disk, a hard disk, a compact disk, an optical disk, a magnetic tape, or the like).

Claims (18)

An apparatus for recovering clock and data from a digital input signal,
A clock recovery unit for recovering a clock having a frequency of M times the frequency of the digital input signal using a division ratio M that varies according to a transmission speed of the digital input signal; And
A data restoring unit for dividing the restored clock received from the clock recovery unit by 1 / M and restoring data from the digital input signal,
And a clock and data recovery unit.
The apparatus of claim 1, wherein the clock recovery unit comprises:
At least one of a reference clock and a feedback clock fixing a frequency of the feedback clock based on a frequency difference of clocks divided according to the division ratio; And
A second loop sharing a feedback loop with the first loop and restoring a clock having the M times frequency based on a phase difference between the digital input signal and the feedback clock;
And a clock and data recovery unit.
3. The method of claim 2,
And a loop selection unit for selecting the first or second loop based on whether the frequency is fixed or not,
Wherein the clock and data recovery device further comprises:
4. The apparatus of claim 3,
A frequency lock detector for detecting whether the frequency is fixed and generating a loop selection signal for selecting the first or second loop based on whether the frequency is fixed; And
A multiplexer for selecting the first or second loop according to the loop selection signal,
And a clock and data recovery unit.
4. The apparatus of claim 3,
Selects the first loop when the frequency fixing is not performed, and selects the second loop when the frequency fixing is performed
Clock and data recovery equipment.
3. The apparatus of claim 2, wherein the first loop comprises:
A first divider that divides the reference clock by M and a second divider that divides the feedback clock by 1 / M
Clock and data recovery equipment.
7. The apparatus of claim 6,
A third frequency divider for dividing the recovered clock by 1 / M; And
A data restoring circuit for restoring data using the 1 / M divided clock;
And a clock and data recovery unit.
8. The data recovery circuit according to claim 7,
It is implemented as a D flip-flop.
Clock and data recovery equipment.
3. The apparatus of claim 2, wherein the first loop comprises:
A frequency-phase detector for detecting a frequency difference between input clocks and outputting a first control signal;
A first charge pump generating a first charge / discharge current signal in response to the first control signal;
A multiplexer for transferring the first charge / discharge current signal based on a loop selection signal;
A loop filter charged / discharged according to the first charge / discharge current signal to generate a first control voltage; And
A voltage-controlled oscillator for generating the frequency-locked feedback clock in response to the first control voltage;
And a clock and data recovery unit.
3. The apparatus of claim 2, wherein the second loop comprises:
A phase detector for detecting a phase difference between the digital input signal and the M times recovered clock and outputting a second control signal;
A second charge pump for generating a second charge / discharge current signal in response to the second control signal;
A multiplexer for transferring the second charge / discharge current signal based on the loop selection signal;
A loop filter charged / discharged according to the second charge / discharge current signal to generate a second control voltage; And
A voltage regulating oscillator for recovering a clock having the M times frequency in response to the second control voltage;
And a clock and data recovery unit.
11. The method of claim 10, wherein the gain of the second charge pump
M is proportional to M
Clock and data recovery equipment.
The method according to claim 1,
A controller for determining the division ratio based on a transmission rate of the digital input signal,
Wherein the clock and data recovery device further comprises:
The method according to claim 1,
As the transmission rate of the digital input signal decreases, the M increases
Clock and data recovery equipment.
CLAIMS 1. A method for recovering a clock and data from a digital input signal,
Restoring a clock having a frequency M times as high as the frequency of the digital input signal using a division ratio M that varies according to a transmission speed of the digital input signal; And
Dividing the recovered clock by 1 / M and restoring data from the digital input signal
And a clock signal.
15. The method of claim 14, wherein restoring the clock comprises:
Fixing a frequency of the feedback clock based on a frequency difference of at least one of a reference clock and a feedback clock divided by the frequency division ratio; And
And restoring a clock having the M times frequency based on a phase difference between the digital input signal and the feedback clock
And a clock signal.
16. The method of claim 15, wherein the step of fixing the frequency of the feedback clock comprises:
Dividing the reference clock by M or dividing the feedback clock by 1 / M
Clock and data recovery methods.
15. The method of claim 14,
Determining the division ratio based on a transmission rate of the digital input signal
Further comprising the steps of:
15. The method of claim 14,
As the transmission rate of the digital input signal decreases, the M increases
Clock and data recovery methods.

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