KR20150053020A - Semiconductor device with air gap and method for fabricating the same - Google Patents

Abstract

The present invention provides a semiconductor device capable of reducing the parasitic capacitance between neighboring conductive structures and a method of manufacturing the same, and a method of manufacturing a semiconductor device according to the present invention includes a step of forming a first contact plug on a substrate and a bit on the first contact plug, Forming a bit line structure comprising a line; Forming a multi-layer spacer including a first spacer, a sacrificial spacer and a second spacer on top and sidewalls of the bit line structure; Forming a separation layer on the multi-layer spacer, the isolation layer including a contact hole exposing sidewalls of the first contact plug and the bit line; A first plug adjacent to the first contact plug in the contact hole, a second plug adjacent to the bit line on the first plug, and a third spacer surrounding the side wall of the second plug in contact with the second spacer, Forming a second contact plug to form a second contact plug; Partially removing the multi-layer spacer so that the sacrificial spacer is exposed; And removing the sacrificial spacers to form an extended air gap between the first contact plug and the first plug and between the bit line and the second plug.

Description

FIELD OF THE INVENTION The present invention relates to a semiconductor device having an air gap,

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having an air gap and a manufacturing method thereof.

In general, a semiconductor device has a dielectric material formed between neighboring conductive structures. As the semiconductor device is highly integrated, the distance between the conductive structures is gradually getting closer. As a result, the parasitic capacitance is increasing. As the parasitic capacitance increases, the performance of the semiconductor device decreases.

To reduce the parasitic capacitance, there is a method of lowering the dielectric constant of the insulating material. However, since the insulating material still has a high permittivity, there is a limitation in reducing the parasitic capacitance.

Embodiments of the present invention provide a semiconductor device capable of reducing parasitic capacitance between neighboring conductive structures and a method of manufacturing the same.

A semiconductor device according to an embodiment of the present invention includes a plurality of bit line structures including a first contact plug on a substrate and a bit line on the first contact plug; A spacer structure including an air gap formed in the sidewalls of the first contact plug and the bit line; An isolation layer formed between the bit line structures and having an open portion; A second contact plug formed in the open portion; And a memory element on the second contact plug.

A method for fabricating a semiconductor device according to an embodiment of the present invention includes: forming a bit line structure including a first contact plug and a bit line on the first contact plug on a substrate; Forming a multi-layer spacer including a first spacer, a sacrificial spacer and a second spacer on top and sidewalls of the bit line structure; Forming a separation layer on the multi-layer spacer, the isolation layer including a contact hole exposing sidewalls of the first contact plug and the bit line; A first plug adjacent to the first contact plug in the contact hole, a second plug adjacent to the bit line on the first plug, and a third spacer surrounding the side wall of the second plug in contact with the second spacer, Forming a second contact plug to form a second contact plug; Partially removing the multi-layer spacer so that the sacrificial spacer is exposed; And removing the sacrificial spacers to form an extended air gap between the first contact plug and the first plug and between the bit line and the second plug.

This technique has the effect of reducing the parasitic capacitance by forming an air gap between the conductive structures.

The present technology can increase the ohmic contact layer formation area, thereby improving the contact resistance.

The technique can improve the resistance of the contact plug by increasing the volume of the metal plug occupying the contact plug.

The technique reduces the parasitic capacitance by forming an air gap between the bit line and the storage node contact plug while at the same time forming an air gap between the bit line contact plug and the storage node contact plug. Thus, the operating speed of the memory cell can be improved.

1A is a cross-sectional view showing a semiconductor device according to an embodiment.
1B is a plan view taken along the line A-A 'in FIG. 1A.
1C is a plan view taken along the line B-B 'in FIG. 1A.
2A to 2M are views showing an example of a method of forming a semiconductor device according to an embodiment.
3 is a diagram showing a memory cell to which the present embodiment is applied.
4A is a plan view taken along the line A-A 'in FIG.
4B is a plan view taken along the line B-B 'in FIG.
5A to 5O are views showing an example of a method of manufacturing a memory cell.
6A to 6D are views showing a method of forming an air gap of a memory cell.
7 is a schematic view showing a memory card;
8 is a block diagram showing an electronic system.

Hereinafter, the most preferred embodiment of the present invention will be described. In the drawings, the thickness and the spacing are expressed for convenience of explanation, and can be exaggerated relative to the actual physical thickness. In describing the present invention, known configurations irrespective of the gist of the present invention may be omitted. It should be noted that, in the case of adding the reference numerals to the constituent elements of the drawings, the same constituent elements have the same number as much as possible even if they are displayed on different drawings.

1A is a cross-sectional view showing a semiconductor device according to an embodiment. 1B is a plan view taken along the line A-A 'in FIG. 1A. 1C is a plan view taken along the line B-B 'in FIG. 1A.

Referring to FIG. 1A, a plurality of conductive structures are formed on a substrate 101. The conductive structure includes a first conductive structure and a second conductive structure. The first conductive structure includes a first conductive pattern 103, a second conductive pattern 104, and a hard mask pattern 105. The second conductive structure includes a third conductive pattern 106, a fourth conductive pattern 107, and a fifth conductive pattern 108. A dielectric structure having air gaps (109, 110) is formed between the first conductive structure and the second conductive structure. The insulating structure includes a first spacer 115, a second spacer 116, and a third spacer 117. Air gaps 109 and 110 are formed between the first spacer 115 and the second spacer 116. The second conductive structure is formed in the insulating layer including the first insulating layer 102 and the second insulating layer 114. A second conductive structure is formed in the open portion 118 of the insulating layer. The air gap 109 is capped by a capping structure 112. In addition, the air gap 110 is capped by the second spacer 116. The capping structure 112 covers the sixth conductive pattern 111 while grasping the recessed portion 113.

Referring to FIG. 1B, an insulating structure including a first spacer 115 and air gaps 109 and 110 is formed between the first conductive pattern 103 and the third conductive pattern 106.

1C, a first spacer 115, a second spacer 116, air gaps 109 and 110, and a third spacer 117 (between the second conductive pattern 104 and the fifth conductive pattern 108) ) Is formed. The third spacer 117 may be of a surrounding type surrounding the side wall of the fifth conductive pattern 108.

The details will be described with reference to FIG. 1A.

The substrate 101 may include a silicon substrate, a silicon germanium substrate, or an SOI (Silicon On Insulator) substrate.

In the first conductive structure, the first conductive pattern 103 may include a silicon-containing material or a metal-containing material. The first conductive pattern 103 may include polysilicon. The second conductive pattern 104 may comprise tungsten.

The height of the third conductive pattern 106 in the second conductive structure has the same height as the first conductive pattern 103 or has a higher height. The third conductive pattern 106 comprises a silicon-containing material. The third conductive pattern 106 may comprise polysilicon. The fifth conductive pattern 108 comprises a metal-containing material. The fifth conductive pattern 108 may comprise tungsten. The fourth conductive pattern 107 includes a silicide. The fourth conductive pattern 107 may include a metal silicide. For example, the fourth conductive pattern 107 may comprise titanium suicide, cobalt suicide, nickel suicide, or tungsten suicide. In this embodiment, the fourth conductive pattern 107 includes Cobalt silicide. The cobalt suicide includes the cobalt suicide of the " CoSi ₂ phase ".

The sixth conductive pattern 111 includes a metal-containing material. The sixth conductive pattern 111 may include tungsten. The sixth conductive pattern 111 simultaneously overlaps the fifth conductive pattern 108 and a part of the hard mask pattern 105. The recess portion 113 is formed by self-alignment with the sixth conductive pattern 111. [

Air gaps 109 and 110 are formed parallel to both side walls of the first conductive structure. That is, the air gaps 109 and 110 are line type air gaps. The air gaps 109 and 110 are formed on both side walls of the first conductive pattern 103 and extend perpendicularly to both side walls of the second conductive pattern 104. There is no spacer between the air gaps 109, 110 and some sidewalls of the third conductive pattern 106. In other embodiments, the air gaps 109 and 110 may be formed on both sidewalls of the first conductive pattern 103 and surround the sidewalls of the second conductive pattern 104. The air gaps 109 and 110 may have an asymmetric structure having different heights by the sixth conductive pattern 111 and the recessed portion 113.

The first conductive structure may be a bitline structure including a first contact plug. The first conductive pattern 103 may be a first contact plug for connecting a transistor to a bit line, and the second conductive pattern 104 may be a bit line. The second conductive structure may be a second contact plug for connecting a transistor and a memory element. For example, the third conductive pattern 106 becomes a first plug, the fifth conductive pattern 108 becomes a second plug, and the sixth conductive pattern 111 becomes a third plug. The first plug includes a silicon plug, and the second plug and the third plug include a metal plug. The fourth conductive pattern 107 becomes an ohmic contact layer between the first plug and the second plug.

The first spacer 115, the second spacer 116, and the third spacer 117 include nitride. The nitride includes silicon nitride. Accordingly, a spacer structure including 'nitride spacer-air' is formed between the first conductive pattern 103 and the third conductive pattern 106. A spacer structure including a first nitride spacer-air-second nitride spacer-third nitride spacer is formed between the second conductive pattern 104 and the third conductive pattern 108.

Although not shown, another conductive structure may be further formed on the sixth conductive pattern 111. FIG. The other conductive structure may be a part of the memory element electrically connected to the sixth conductive pattern 111. [ The memory element may include a capacitor consisting of a storage node, a dielectric, and a plate node, and the other conductive structure may include a storage node. Memory elements may be implemented in various forms. For example, the memory element may comprise a variable resistance material. The memory element may have a first electrode, a variable resistance material, and a second electrode sequentially stacked, and the first electrode may be electrically connected to the sixth conductive pattern 111. [ Information can be stored using the change of the resistance of the variable resistance material depending on the voltage applied to the first electrode and the second electrode. The variable resistance material may comprise a phase change material or a magnetic tunnel junction.

Although not shown, a transistor including a gate electrode, a source region, and a drain region may be further formed. The first conductive pattern 103 and the third conductive pattern 106 may be connected to a source region or a drain region of the transistor. The transistor may be a planar gate type transistor, a trench gate type transistor, a buried gate type transistor, a recessed gate type transistor, a vertical channel transistor ). The trench gate type transistor, the buried gate type transistor, and the recessed gate type transistor have a structure in which a part of the gate electrode is expanded or buried in the substrate 101.

2A to 2M are views showing an example of a method of forming a semiconductor device according to an embodiment.

As shown in FIG. 2A, a first insulating layer 12 is formed on a substrate 11. The substrate includes a semiconductor substrate. The substrate 11 may include a silicon substrate, a silicon germanium substrate, or a silicon on insulator (SOI) substrate. The first dielectric layer 12 may include silicon oxide, silicon nitride, or a stacked structure of silicon oxide and silicon nitride.

A first opening 13A is formed in the first insulating layer 12. The first open portion 13A is formed by etching the first insulating layer 12 using the first mask pattern 14. The first mask pattern 14 may include a hard mask pattern patterned by a photoresist pattern or a photoresist pattern. The first open portion 13A may have a hole shape when viewed in a plan view. The surface of the substrate 11 is exposed by the first open portion 13A. The first open portion 13A has a diameter D controlled by a constant line width.

As shown in FIG. 2B, the first mask pattern 14 is removed.

A pre-first conductive pattern 15A is formed on the first open portion 13A. The preliminary first conductive pattern 15A is formed by etching the first conductive layer (not shown). The preliminary first conductive pattern 15A is formed by CMP (Chemical Mechanical Polishing) of the first conductive layer. The preliminary first conductive pattern 15A becomes a shape for embedding the first open portion 13A. The preliminary first conductive pattern 15A may include a silicon-containing layer or a metal-containing layer. The preliminary first conductive pattern 15A may include a polysilicon layer.

The second conductive layer 16A is formed on the preliminary first conductive pattern 15A. The second conductive layer 16A includes a metal-containing layer. The second conductive layer 16A may comprise a metal, a metal nitride, a metal silicide, or a combination thereof. The second conductive layer 16A may comprise a tungsten-containing layer. The second conductive layer 16A may include a tungsten layer. At this time, a barrier layer may be further formed between the preliminary first conductive pattern 15A and the second conductive layer 16A. Therefore, the preliminary first conductive pattern 15B and the second conductive layer 16A may include a laminated structure of a polysilicon layer, a titanium-containing layer, and a tungsten layer. The titanium-containing layer may be a barrier layer, and a titanium layer (Ti) and titanium nitride (TiN) may be laminated.

A hard mask layer 17A is formed on the second conductive layer 16A. The hard mask layer 17A may comprise silicon oxide or silicon nitride.

As shown in FIG. 2C, a second mask pattern 18 is formed. The second mask pattern 18 has a line shape. The second mask pattern 18 may include a hard mask pattern patterned by a photoresist pattern or a photoresist pattern. The second mask pattern 18 has a constant line width W. Here, the line width of the second mask pattern 18 is smaller than the diameter D of the first open portion 13A.

A first conductive structure is formed. The hard mask layer 17A, the second conductive layer 16A, and the preliminary first conductive pattern 15A are sequentially etched by using the second mask pattern 18. Then, Thus, a first conductive structure including the first conductive pattern 15, the second conductive pattern 16, and the hard mask pattern 17 is formed. The first conductive pattern 15 is formed in the first open portion 13A. The second conductive pattern 16 and the hard mask pattern 17 have a line shape. The first conductive pattern 15 has a plug type. A part of the first open portion 13A is exposed to the periphery of the first conductive pattern 15. [ This will be abbreviated as a side opening 13. The reason why the side wall open portion 13 is formed is that the line width of the second mask pattern 18 is smaller than the diameter of the first open portion 13A.

As shown in Figure 2D, the second mask pattern 18 is removed. A first spacer layer 19A is formed on the entire surface including the first conductive structure. The first spacer layer 19A comprises an insulating material. The first spacer layer 19A may comprise silicon oxide or silicon nitride. Hereinafter, in the embodiment, the first spacer layer 19A includes silicon nitride. The first spacer layer 19A is conformally formed on the sidewall openings 13 and the first insulating layer 12 without tapping the sidewall openings 13. [

A sacrificial spacer layer 20A is formed on the first spacer layer 19A. The sacrificial spacer layer 20A includes an insulating material. The sacrificial spacer layer 20A includes a material having an etch selectivity to the first spacer layer 19A. The sacrificial spacer layer 20A may comprise silicon oxide or silicon nitride. Hereinafter, in an embodiment, the sacrificial spacer layer 20A comprises silicon oxide. The sacrificial spacer layer 20A implements the sidewall opening 13 on the first spacer layer 19A.

As shown in FIG. 2E, a sacrificial spacer 20 is formed. The sacrificial spacer 20 is formed by etching the sacrificial spacer layer 20A. The sacrificial spacer layer 20A can be etched by the etch-back process. Thereby, a sacrificial spacer 20 is formed on the sidewall of the first conductive structure with the first spacer layer 19A therebetween. The top height of the sacrificial spacer 20 is controlled to be lower than the top surface of the first conductive structure (see 20B '). The sacrificial spacer layer 20A is removed from the surface of the first insulating layer 12.

As shown in FIG. 2F, a second spacer layer 21A is formed on the sacrificial spacer 20. The second spacer layer 21A is formed on the front surface including the sacrificial spacer 20. The second spacer layer 21A includes an insulating material. The second spacer layer 21A may comprise silicon oxide or silicon nitride. Hereinafter, in the embodiment, the second spacer layer 21A includes silicon nitride. The sacrificial spacer 20 is sealed from the outside by the second spacer layer 21A. That is, a multi-spacer layer is formed in which the sacrificial spacer 20 is located between the first spacer layer 19A and the second spacer layer 21A. Since the first spacer layer 19A and the second spacer layer 21A include silicon nitride and the sacrificial spacer 20 includes silicon oxide, a multi-layered structure of 'nitride-oxide-nitride' structure spacer) is formed.

As shown in FIG. 2G, a second insulating layer 22 including a second open portion 23 is formed. The second insulating layer 22 comprises an insulating material. The second insulating layer 22 comprises silicon oxide or silicon nitride. Hereinafter, in the embodiment, the second insulating layer 22 includes silicon nitride.

The second open portion 23 is formed by etching the second insulating layer 22. In another embodiment, after the sacrificial pattern corresponding to the second open portion 23 is formed, the second insulating layer 22 is formed. Thereafter, the second opening 23 may be formed by removing the sacrificial pattern after the second insulating layer 22 is planarized. The second open portion 23 may have a hole shape.

The surface of the substrate 11 under the second open portion 23 is exposed as shown in Fig. 2H. To this end, the second spacer layer 21A and the first spacer layer 19A are selectively removed. In addition, the sacrificial spacer 20 and the first insulating layer 12 are partly etched. Thus, the second open portion 23 expands so as to expose the surface of the substrate 11. The sacrificial spacers 20 can be etched aligned with the edges of the second spacer layer 21A.

By such exposure of the substrate 11, an insulating structure including the first spacer 19 and the sacrificial spacer 20 is formed on the side wall of the first conductive pattern 15. An insulating structure including a first spacer 19, a sacrificial spacer 20, and a second spacer 21 is formed on a sidewall of the second conductive pattern 16. The top part of the sacrificial spacer 20 between the first spacer 19 and the second spacer 21 is sealed from the outside. The bottom part of the sacrificial spacer 20 is exposed by the second open part 23.

2I, a third conductive pattern 24 is formed. The third conductive pattern 24 is recessed inside the second open portion 23. A third conductive layer (not shown) is formed on the second insulating layer 22 while filling the second open portion 23. The third conductive layer is selectively removed to form the third conductive pattern 24 in the second open portion 23. [ An etch-back process of the third conductive layer may be performed to form the third conductive pattern 24. The third conductive pattern 24 may comprise a silicon-containing layer. The third conductive pattern 24 may comprise a polysilicon layer. The polysilicon layer may be doped with impurities. The third conductive pattern 24 is in contact with the surface of the substrate 11. The height of the third conductive pattern 24 can be adjusted as low as possible. This is to minimize the volume occupied by the third conductive pattern 24 in the second conductive structure. Therefore, the resistance of the second conductive structure can be reduced.

As shown in Fig. 2J, a third spacer 27 is formed. The third spacer 27 is formed by vapor deposition and etching of an insulating layer (not shown). The third spacer 27 is conformally formed on the front surface including the third conductive pattern 24. The third spacer 27 may comprise a material of the same material as the first spacer 19 and the second spacer 21. The third spacer 27 may comprise silicon nitride. The third spacer 27 is formed on the sidewall of the second open portion 23 above the third conductive pattern 24. The third spacer 27 may be configured to surround the side wall of the second open portion 23.

The surface of the third conductive pattern 24 can be recessed to a certain depth when the third spacer 27 is formed or after the third spacer 27 is formed. The recessed surface of the third conductive pattern 24 may have a " V " shape. This is to increase the reaction area for forming the subsequent silicide layer.

As described above, by forming the third spacer 27, a multiple spacer structure including the first spacer 19, the sacrificial spacer 20, the second spacer 21, and the third spacer 27 is formed. The first spacers 19, the sacrificial spacers 20 and the second spacers 21 are line-shaped spacers formed parallel to both side walls of the first conductive structure. The third spacer 27 is a surrounding spacer that surrounds the side wall of the second open portion 23.

As shown in FIG. 2K, a fourth conductive pattern 28 is formed on the surface of the third conductive pattern 24. The fourth conductive pattern 28 includes a silicide layer. Deposition and annealing of the fourth conductive layer to form the fourth conductive pattern 28 is performed. Silicidation occurs at the interface between the fourth conductive layer and the third conductive pattern 24 to form a fourth conductive pattern 28 including a metal silicide layer . The fourth conductive pattern 28 may comprise cobalt suicide. In this embodiment, the second conductive pattern 28 may comprise a " CoSi ₂ phase " cobalt suicide.

As described above, when the cobalt silicide of the CoSi ₂ phase is formed as the fourth conductive pattern 28, the contact resistance is improved, and the low resistance cobalt silicide is formed in the small area of the second open portion 23 having the fine line width . The fourth conductive pattern 28 is an ohmic contact layer between the third conductive pattern 24 and the fifth conductive pattern. The remaining fourth conductive layer may be removed after the fourth conductive pattern 28 is formed.

A fifth conductive pattern 29 is formed on the fourth conductive pattern 28. Gapping and planarization of the fifth conductive layer (not shown) may be performed to form the fifth conductive pattern 29. [ The fifth conductive pattern 29 is formed filling the rest of the second open portion 23 on the fourth conductive pattern 28. The fifth conductive pattern 29 may comprise a metal-containing layer. The fifth conductive pattern 29 may comprise a material containing tungsten. The fifth conductive pattern 29 may comprise a tungsten layer or a tungsten compound. The fifth conductive pattern 29 may have the same height as the surface of the second insulating layer 22. The height of the fifth conductive pattern 29 is higher than that of the third conductive pattern 24. Therefore, the volume of the fifth conductive pattern 29 in the conductive structure formed in the second open portion 23 is larger than the volume of the third conductive pattern 24.

The second conductive structure including the third conductive pattern 24, the fourth conductive pattern 28 and the fifth conductive pattern 29 is formed in the second open portion 23 as described above. The third spacer 27 is a surrounding form surrounding the side wall of the fifth conductive pattern 29. A first spacer 19, a sacrificial spacer 20, a second spacer 21 and a third spacer 27 are formed between the second conductive pattern 16 and the fifth conductive pattern 29. A first spacer 19 and a sacrificial spacer 20 are formed between the first conductive pattern 15 and the third conductive pattern 24.

As shown in FIG. 21, a sixth conductive pattern 30 is formed. The sixth conductive pattern 30 is formed by vapor deposition and etching of a sixth conductive layer (not shown). The sixth conductive pattern 30 includes a metal-containing layer. The sixth conductive pattern 30 may comprise a material containing tungsten. The sixth conductive pattern 30 may include a tungsten layer or a tungsten compound. The sixth conductive pattern 30 may include a laminated structure of a metal containing layer.

The sixth conductive pattern 30 partially overlaps with the fifth conductive pattern 29. Therefore, the sixth conductive pattern 30 exposes a part of the fifth conductive pattern 29 and its surrounding structure. That is, a part of the multiple spacers is exposed. A portion of the first spacer 19, the sacrificial spacer 20, the second spacer 21, and the third spacer 27 are exposed by the sixth conductive pattern 30.

The fifth conductive pattern 29 is self-aligned to the edge of the sixth conductive pattern 30 to etch the fifth conductive pattern 29 at a certain depth. At this time, the first spacer 19, the sacrificial spacer 20, the second spacer 21, and the third spacer 27 are etched by being self-aligned to the edge of the sixth conductive pattern 30. In addition, a portion of the second insulating layer 22 and the hard mask pattern 17 are also etched to a certain depth. Thus, the recessed portion 31 is formed. A part of the fifth conductive pattern 29 is covered by the sixth conductive pattern 30 and the other part of the fifth conductive pattern 29 is exposed by the recessed portion 31 as viewed in plan view.

The sacrificial spacer 20 is removed. A strip process is carried out to remove the sacrificial spacer 20. The stripping process includes a cleaning process. The cleaning process uses a wet chemical that can remove the sacrificial spacers 20. The sacrificial spacers 20 under the sixth conductive pattern 30 are also removed by the wet chemical. The stripping process may include post-etch cleaning of the sixth conductive pattern 30, thereby eliminating the need for an additional process to remove the sacrificial spacers 20.

The sacrificial spacers 20 are removed by the stripping process, and the space occupied by the sacrificial spacers 20 remains in the air gaps 32, 33. The air gaps 32 and 33 may be formed in a line structure extending parallel to the side wall of the second conductive pattern 16.

As described above, the air gaps 32 and 33 are formed not only around the first conductive pattern 15 but also around the second conductive pattern 16. Therefore, an insulating structure composed of the first spacer 19 and the air gaps 32 and 33 is formed between the first conductive pattern 15 and the third conductive pattern 24. Since the first spacer 19 includes silicon nitride, an insulating structure of a 'Nitride-Air' structure is formed. An insulating structure composed of a first spacer 19, air gaps 32 and 33, a second spacer 21 and a third spacer 27 is formed between the second conductive pattern 16 and the fifth conductive pattern 29 . Since the first spacer 19, the second spacers 21 and the third spacers 27 include silicon nitride, an insulating structure of 'Nitride-Air-Nitride-Nitride' structure is formed.

The first spacer 19 and the second spacer 21 may have an asymmetric height at the side wall of the first conductive structure. For example, the heights of the portions (A1 ') for exposing the top portion of the air gap 32 and the portions (A2') for capping the top portion of the air gap 33 are different from each other. Referring to A2, the second spacer 21 can be extended to cap the top part of the air gap 33. [

2M, a capping structure 34 is formed. The capping structure 34 comprises an insulating material. The capping structure 34 may include a poor-step coverage material. For example, the capping structure 34 may be formed using Plasma Enhanced Chemical Vapor Deposition (PECVD), thereby capping the top portion of the air gap 32 to be clogged. The capping structure 34 comprises silicon oxide or silicon nitride. The capping structure 34 may comprise silicon nitride by plasma enhanced chemical vapor deposition (PECVD). The capping structure 34 caps the air gap 32 while grabbing the recessed portion 31. In addition, the upper portion of the sixth conductive pattern 30 is covered. As another example, in forming the capping structure 34, the first capping layer may be lined conformationally and then formed by tapping the second capping layer. If the sixth conductive pattern 30 is in the form of a plug, the capping structure 34 may cap the air gap 33. A portion of the air gap 33 is capped by the second spacer 21 under the sixth conductive pattern 30 and an air gap 33 is formed on the outside of the sixth conductive pattern 30 by the capping structure 34. [ Is capped.

As such, the top portion of the air gap 33 is capped by the second spacer 21 and the air gap 32 is capped by the capping structure 34.

The first conductive structure includes a first conductive pattern 15 and a second conductive pattern 16. The second conductive structure includes a third conductive pattern 24, a fourth conductive pattern 28, and a fifth conductive pattern 29. Air gaps (32, 33) are formed between the first conductive structure and the second conductive structure.

According to the first embodiment, the air gap 32, 33 is formed to improve the electrical insulation property of the first conductive structure and the second conductive structure. For example, the parasitic capacitance between the first conductive pattern 15 and the third conductive pattern 24 is reduced. Further, the parasitic capacitance between the second conductive pattern 16 and the fifth conductive pattern 29 is reduced.

In addition, since the air gaps 32 and 33 are formed after the fourth conductive pattern 28 is formed first, the area where the fourth conductive pattern 28 is formed can be widened. Thus, the interface resistance can be improved.

Further, since the volume of the fifth conductive pattern 29, which is a metal-containing material, is larger than the third conductive pattern 24 which is a silicon-containing material, the resistance of the first conductive structure can be improved.

3 is a diagram showing a part of a semiconductor device to which the present embodiment is applied. Figure 3 shows a memory cell.

Referring to FIG. 3, a plurality of active regions 203 are defined in an isolation region 202 in a substrate 201. A gate trench 204 is formed across the active region 203. A gate dielectric (not shown) is formed on the surface of the gate trench 204. A buried gate electrode 205 is partially formed on the gate insulating layer so as to partially fill the gate trench 204. Although not shown, a source region and a drain region are formed on the substrate 201. A sealing layer 206 is formed on the buried gate electrode 205. A bit line structure including a bit line 208 extending in a direction crossing the buried gate electrode 205 is formed.

The bit line structure includes a first contact plug 207, a bit line 208 and a bit line hard mask 209. The bit line 208 is connected to the active region 203 through the first contact plug 207. The first contact plug 207 is connected to the active region 203 through an inter-layer dielectric 222. A first contact hole (refer to '207A' in FIG. 4A) is formed in the interlayer insulating layer 222, and a first contact plug 207 is formed in the first contact hole 207A. The first contact plug 207 is abbreviated as a bit line contact plug.

A second contact plug and a third contact plug 219 connected to the other active region 203 are formed. The second contact plug and the third contact plug 219 are abbreviated as a storage node contact plug. A second contact plug is formed in the second contact hole formed in the separation layer (214). The second contact plug includes a first plug 210, an ohmic contact layer 211, and a second plug 212. The first plug 210 is a silicon plug comprising polysilicon. The second plug 212 and the third contact plug 219 are metal plugs including tungsten. The ohmic contact layer 211 is formed between the first plug 210 and the second plug 212. The ohmic contact layer 211 includes a metal silicide layer. The volume occupied by the first plug (210) in the second contact plug is smaller than that of the second plug (212). As a result, the resistance of the second contact plug is reduced by the metal plug-in second plug 212. The contact resistance is reduced by forming the ohmic contact layer 211 between the first plug 210 and the second plug 212. By forming the third contact plug 219, an overlap margin of the storage node 221 can be ensured.

An air gap 213 is formed between the bit line structure and the second contact plug. The air gap 213 is formed in the sidewall of the first contact plug 207 and extends vertically to be formed in the sidewall of the bit line 208. And may extend parallel along the sidewalls of the bit line 208 at the sidewalls of the bit line 208.

The air gap 213 is capped by the capping layer 220 and the second spacer 216. A portion of the air gap 213 is capped by the second spacer 216 and the remainder of the air gap 213 is capped by the capping layer 220.

A capacitor including the storage node 221 is connected on the third contact plug 219. The storage node 221 includes a pillar type. Although not shown, a dielectric layer and a plate node may be further formed on the storage node 221. The storage node 221 may be in the form of a cylinder in addition to a pillar shape. In other embodiments, variously implemented memory elements may be coupled on the third contact plug 219.

As described above, the memory cell includes a buried gate type transistor including a buried gate electrode 205, a bit line 208, and a capacitor. The transistor and the bit line 208 are electrically connected by the first contact plug 207. The transistor and the capacitor are electrically connected by the second contact plug and the third contact plug 219. The second contact plug is a structure in which the first plug 210, the ohmic contact layer 211, and the second plug 212 are stacked.

An air gap 213 is formed between the second plug 212 of the second contact plug and the bit line 208. Thus, the parasitic capacitance between the bit line 208 and the second contact plug decreases. An air gap 213 is formed between the first plug 210 of the second contact plug and the first contact plug 207. Thus, the parasitic capacitance between the first contact plug 207 and the second contact plug is reduced.

4A is a plan view taken along the line A-A 'in FIG. Referring to FIG. 4A, the diameter of the first contact hole 207A is larger than the line width of the first contact plug 207. FIG. Therefore, a gap is formed in the side wall of the first contact plug 207, and an air gap 213 and a first spacer 215 are formed in the gap. As a result, an insulating structure including a first spacer 215 and an air gap 213 is formed between the first contact plug 207 and the first plug 210.

4B is a plan view taken along the line B-B 'in FIG. Referring to FIG. 4B, isolation between the bit line 208 and the second plug 212, including a first spacer 215, an air gap 213, a second spacer 216 and a third spacer 217, A structure is formed. The third spacer 217 is in the form of a surrounding that surrounds the side wall of the second plug 212. The air gap 213 is in the form of a line extending parallel to the side wall of the bit line 208.

According to the above description, an air gap 213 is formed between the first contact plug 207 and the first plug 210. In addition, an air gap 213 is also formed between the bit line 208 and the second plug 212. A first spacer structure 218A composed of a first spacer 215 and an air gap 213 is formed between the first contact plug 207 and the first plug 210. When the first spacer 215 includes silicon nitride, a first spacer structure 218A of a 'Nitride-Air' structure is formed. A second spacer structure 218B consisting of a first spacer 215, an air gap 213, a second spacer 216 and a third spacer 217 is formed between the bit line 208 and the second plug 212 . When the first spacer 215, the second spacer 216 and the third spacer 217 include silicon nitride, a second spacer structure 218B having a structure of 'Nitride-Air-Nitride-Nitride' is formed.

The heights of the air gaps 213 on both side walls of the bit line 208 may be different. The height asymmetry of the air gap 213 is implemented by the capping layer 220. The upper portion of the air gap 213 is capped by different structures. A portion of the air gap 213 is capped by the second spacer 216. The remainder of the air gap 213 is capped by the capping layer 220. If the first spacers 215, the second spacers 216 and the capping layer 220 comprise silicon nitride, the air gaps 213 are capped by the silicon nitrides.

According to the present embodiment, an air gap 213 is formed between the bit line 208 and the storage node contact plug, and an air gap 213 is formed between the bit line contact plug 207 and the storage node contact plug , And reduces the parasitic capacitance. This improves the operation speed of the memory cell.

On the other hand, as a comparative example of this embodiment, an air gap may be formed only between the bit line and the storage node contact plug. Further, as another comparative example, an air gap may be formed only between the bit line contact plug and the storage node contact plug. However, the comparative examples have a lower effect of reducing the parasitic capacitance than the present embodiment, so that there is a limit in improving the operation speed of the memory cell.

5A to 5O are views showing an example of a method of manufacturing the memory cell shown in FIG.

As shown in Fig. 5A, an element isolation region 44 is formed in the substrate 41. Fig. The substrate 41 may comprise a silicon substrate, a silicon germanium substrate, or an SOI substrate. The substrate 41 includes a memory cell region and a non-memory cell region. The non-memory cell region may include a peripheral circuit region. The peripheral circuit region may be formed of a logic transistor or the like. Hereinafter, an embodiment will be described with respect to a manufacturing method in a memory cell region. The device isolation region 44 may be formed through an STI (Shallow Trench Isolation) process. The element isolation region 44 is formed in an isolation trench 42. The active region 43 is defined by the element isolation region 44. The active region 43 may be an island type having a short axis and a long axis. A plurality of active regions 43 are separated by an element isolation region 44. [ The element isolation region 44 may sequentially form a sidewall oxide, a liner, and a gap fill material. The liner may comprise silicon nitride, silicon oxide. The silicon nitride may comprise Si ₃ N ₄ and the silicon oxide may comprise SiO ₂ . The gap fill material may include silicon oxides such as spin on dielectrics. Also, the gap fill material may include silicon nitride, wherein silicon nitride may be imaged using silicon nitride used as a liner.

A transistor including a buried gate electrode 46 is formed. The buried gate electrode 46 is buried in the substrate 41. [ A buried gate electrode 46 is formed in the gate trench 45. The gate trench 45 may be formed by etching the active region 43 and the isolation region 44. The depth of the gate trench 45 is shallower than the element isolation region 44. [ A gate insulating layer (not shown) may be formed on the surface of the gate trench 45. The gate insulating layer may be formed through thermal oxidation. A buried gate electrode 46 is recessed and formed on the gate insulating layer. A sealing layer 47 is formed on the buried gate electrode 46. The buried gate electrode 46 may be formed by forming a metal-containing layer so as to cover the gate trench 45 and then etched back. The metal-containing layer may include a material mainly composed of a metal such as titanium, tantalum, tungsten, or the like. The metal-containing layer may include at least one selected from the group consisting of tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), and tungsten (W). For example, the buried gate electrode 46 can be formed of TiN / W or TaN / W, which includes titanium nitride, tantalum nitride, or tungsten alone or tungsten (W) on titanium nitride (TiN) or tantalum nitride W and the like. Further, it may include a two-layer structure of WN / W for laminating tungsten (W) on tungsten nitride (WN). In addition, it may include a tungsten layer, and may further include a low resistance metal material. The sealing layer 47 may fill the gate trench 45 on the buried gate electrode 46. The sealing layer 47 may serve to protect the buried gate electrode 46 from subsequent processes. The sealing layer 47 may comprise an insulating material. The sealing layer 47 may comprise silicon nitride. A source region and a drain region (not shown) may be formed in the active region 43 after the formation of the sealing layer 47. [ Thus, a buried gate type transistor including a buried gate electrode 46 is formed.

Next, an interlayer insulating layer 48 is formed. The interlayer insulating layer 48 is etched to form the first contact hole 49. The first contact hole 49 exposes a portion of the active region 43. The first contact hole 49 may be shaped to expose a central portion of the active region 43. The first contact hole 49 has a diameter larger than the width of the short axis of the active region 43. Therefore, part of the element isolation region 44 in the etching process for forming the first contact hole 49 can also be etched. The active region 43 exposed by the first contact hole 49 includes any one of the source region and the drain region of the buried gate type transistor. The first contact hole 49 may be abbreviated as a bit line contact hole.

The exposed active region 43 under the first contact hole 49 is recessed (see reference character R). Thus, the surface of the active area 43 to which the bit line contact plug is to be connected is lower in height than the surface of the active area 43 to which the storage node contact plug is to be connected.

As shown in Fig. 5B, a preliminary first contact plug 50A is formed. A method of forming the preliminary first contact plug 50A will be described below. First, a polysilicon layer filling the first contact hole 49 is formed. Next, the polysilicon layer is planarized so that the surface of the interlayer insulating layer 48 is exposed.

The first conductive layer 51A and the hard mask layer 52A are stacked on the preliminary first contact plug 50A, as shown in Fig. 5C. The first conductive layer 51A includes a metal-containing layer such as tungsten. The hardmask layer 52A comprises silicon nitride.

And forms a bit line structure, as shown in FIG. 5D. For example, the hard mask layer 52A, the first conductive layer 51A and the preliminary first contact plug 50A are etched by a bit line mask (not shown). Thus, the first contact plug 50, the bit line 51 and the bit line hard mask layer 52 are formed.

A first contact plug 50 is formed on the recessed active region 43. That is, in the first contact hole 49. The first contact plug (50) has a line width smaller than the diameter of the first contact hole (49). Therefore, a sidewall contact hole 49A is formed around the first contact plug 50. [ The sidewall contact hole 49A provides a gap between the first contact plug 50 and the interlayer insulating layer 48. The bit line 51 comprises a tungsten-containing material. The bit line 51 may comprise a tungsten layer. The bit line hardmask layer 52 serves to protect the bit line 51. The bit line hardmask layer 52 comprises an insulating material. The bit line hardmask layer 52 may comprise silicon nitride. The first contact plug 50 may be abbreviated as a bit line contact plug. The depth of the first contact hole 49 is minimized to remove residues during etching of the preliminary first contact plug 50A.

As described above, since the first contact plug 50 is formed, a part of the first contact hole 49, that is, the side wall contact hole 49A is opened. This is because the first contact plug 50 is etched smaller than the diameter of the first contact hole 49.

Although not shown, a gate structure may be formed on the substrate 41 of the non-memory cell region in forming the bit line structure.

As shown in FIG. 5E, a first spacer layer 53A is formed on the bit line structure. The first spacer layer 53A is formed on the front surface of the substrate 41 including the bit line structure. The first spacer layer 53A includes an insulating material. The first spacer layer 53A may comprise silicon nitride. The first spacer layer 53A is conformally formed on the sidewall contact hole 49A and the interlayer insulating layer 48. [

A sacrificial spacer layer 54A is formed on the first spacer layer 53A. The sacrificial spacer layer 54A may be formed while tapping the sidewall contact hole 49A. The sacrificial spacer layer 54A comprises silicon oxide.

As described above, in the side wall contact hole 49A between the first contact plug 50 and the interlayer insulating layer 48, a double spacer layer (not shown) including a first spacer layer 53A and a sacrificial spacer layer 54A is formed. Is formed.

As shown in Fig. 5F, a sacrificial spacer 54 is formed. The sacrificial spacer 54 is formed by etching the sacrificial spacer layer 54A. The sacrificial spacer layer 54A can be etched by the etch-back process. Thus, a sacrificial spacer 54 is formed on the sidewall of the bit line structure with the first spacer layer 53A therebetween. The top height of the sacrificial spacers 54 is controlled to be lower than the top surface of the bit line conductive structures (see 54B '). The sacrificial spacer layer 54A is removed from the surface of the interlayer insulating layer 48. [

As shown in Figure 5G, a second spacer layer 55A is formed on the sacrificial spacer 54. [ The second spacer layer 55A is formed on the front surface including the sacrificial spacer 54. [ The second spacer layer 55A includes an insulating material. The second spacer layer 55A may comprise silicon oxide or silicon nitride. Hereinafter, in an embodiment, the second spacer layer 55A comprises silicon nitride. The sacrificial spacer 54 is sealed from the outside by the second spacer layer 55A. That is, a multi-spacer layer is formed in which the sacrificial spacer 54 is located between the first spacer layer 53A and the second spacer layer 55A. The first spacer layer 53A and the second spacer layer 55A comprise silicon nitride and the sacrificial spacer 54 comprises silicon oxide so that a multiple spacer layer of the NON structure is formed.

The thicknesses of the first spacer layer 53A, the sacrificial spacer layer 54 and the second spacer layer 55A are minimized to secure the open margin of the subsequent second contact hole.

As shown in Fig. 5H, a sacrificial layer 56A is formed. The sacrificial layer 56A is imaged between the bit line structures. The sacrificial layer 56A includes silicon oxide. The sacrificial layer 56A may include a spin-on insulating layer (SOD). The sacrificial layer 56A may be planarized to expose the surface of the second spacer layer 55A above the bitline structure.

As shown in FIG. 5I, a pre-isolation part 57 is formed in the sacrifice layer 56A. The preliminary separation portion 57 is formed by etching using a mask pattern (not shown) in a direction crossing the bit line structure.

As shown in FIG. 5J, an isolation layer 58 is formed in the preliminary separation portion 57. The isolation layer 58 may be formed by forming silicon nitride to fill the preliminary isolation portion 57 and then planarizing.

As shown in Fig. 5K, the sacrificial layer 56A is removed. Thus, an open portion, that is, a second contact hole 59 is formed. A second contact hole 59 is formed between the isolation layers 58. An isolation layer 58 is formed between the bit line structures. Accordingly, a second contact hole 59 and a separation layer 58 are formed between the bit line structures. The second contact hole 59 may be abbreviated as a storage node contact hole.

As shown in FIG. 51, the bottom portion of the second contact hole 59 is extended. To this end, the second spacer layer 55A and the first spacer layer 53A are selectively removed. In addition, the bottom portion of the sacrificial spacer 54 and the interlayer insulating layer 48 are partly etched. Therefore, the substrate 41 under the second contact hole 59 is exposed. The second spacer layer 55A and the first spacer layer 53A are removed at the top of the bit line structure. The bottom portion of the second contact hole 59 may have a V-shaped profile (see reference numeral 60 ') due to the etching selectivity difference.

On the side wall of the bit line 51, an insulating structure including a first spacer 53, a sacrificial spacer 54, and a second spacer 55 is formed. An insulating structure including a first spacer 53 and a sacrificial spacer 54 is formed on a sidewall of the first contact plug 50. The bottom portion of the sacrificial spacer 54 is exposed by the second contact hole 59. The intermediate portion and the top portion of the sacrificial spacer 54 are covered by the second spacer 55.

Subsequently, a second contact plug including a first plug, an ohmic contact layer and a second plug is formed.

This is as follows.

As shown in Fig. 5M, a first plug 61 is formed. The first plug 61 is recessed inside the second contact hole 59. The first plug 61 may comprise a silicon-containing layer. The first plug 61 may comprise a polysilicon layer. The polysilicon layer may be doped with impurities. The first plug 61 is in contact with the surface of the substrate 41. The first plug 61 may have a height recessed close to the bottom surface of the bit line 51. The height of the first plug 61 can be adjusted as low as possible. This is to minimize the volume occupied by the first plug 61 in the second contact plug. Therefore, the resistance of the second contact plug can be reduced. The DIP-out process for further extending the bottom portion of the second contact hole 59 may not be performed before the first plug 61 is formed. Accordingly, it is possible to prevent voids from being generated in the first plug 61, and to minimize the volume of the first plug 61. In addition, by omitting the dip-out process, it is possible to prevent a failure with the first plug 61. [ The first plug 61 has a thickness of 100 to 500 ANGSTROM.

As shown in FIG. 5N, a third spacer 62 is formed. The third spacers 62 are formed by deposition and etching of an insulating layer (not shown). The insulating layer used as the third spacer 62 is conformally formed on the front surface including the first plug 61. The third spacer 62 may comprise a material of the same material as the first spacer 53 and the second spacer 55. The third spacer 62 may comprise silicon nitride. By further forming the third spacer 62, the parasitic capacitance is further reduced. That is, the parasitic capacitance can be increased by decreasing the thickness of the first spacer layer 53A, the sacrificial spacer layer 54 and the second spacer layer 55A, but the parasitic capacitance is increased by the third spacer 62 .

The surface of the first plug 61 can be recessed to a certain depth when the third spacer 62 is formed or after the third spacer 62 is formed (see reference numeral 62A '). The recessed surface of the first plug 61 may have a "V" shape. This is to increase the reaction area for forming the subsequent silicide layer.

As described above, by forming the third spacer 62, a multiple spacer structure including the first spacer 53, the sacrificial spacer 54, the second spacer 55, and the third spacer 62 is formed in the bit line structure Is formed on the side wall.

An ohmic contact layer 63 is formed on the surface of the first plug 61, as shown in FIG. The ohmic contact layer 63 includes a silicide layer. The ohmic contact layer 63 is made of CoSi ₂ Phase " cobalt suicide. ≪ / RTI > After the coarse layer is deposited to form the ohmic contact layer 63, annealing may be performed at least twice. Thereafter, the un-reacted cobalt layer can be removed.

A second plug (64) is formed on the ohmic contact layer (63). The second plug 64 is formed on the ohmic contact layer 63 while filling the rest of the second contact hole 59. The second plug 64 may comprise a metal-containing layer. The second plug 64 may comprise a material containing tungsten. The second plug 64 may comprise a tungsten layer or a tungsten compound. The second plug 64 may have the same height as the surface of the separation layer 58.

As described above, the second contact plug including the first plug 61, the ohmic contact layer 63, and the second plug 64 is formed in the second contact hole 59. The third spacer 62 is in the form of a surrounding that surrounds the side wall of the second plug 64. A first spacer 53, a sacrificial spacer 54, a second spacer 55 and a third spacer 52 are formed between the bit line 51 and the second plug 64. A first spacer 53 and a sacrificial spacer 54 are formed between the first contact plug 50 and the first plug 61. The third spacer 52 is in the form of surrounding the upper sidewall of the second contact plug, that is, the sidewall of the second plug 64. The second contact plug including the first plug 61, the ohmic contact layer 63, and the second plug 64 is abbreviated as a 'first storage node contact plug (first SNC plug)'.

And subsequently forms an air gap.

6A to 6D are views showing a method of forming an air gap of a memory cell.

As shown in Fig. 6A, a third contact plug 65 is formed. The third contact plug 65 includes a metal-containing layer. The third contact plug 65 may comprise a material containing tungsten. The third contact plug 65 may comprise a tungsten layer or a tungsten compound. The third contact plug 65 may include a laminated structure of a metal-containing layer. After the tungsten layer is deposited to form the third contact plug 65, the tungsten layer can be etched by the mask pattern 65B.

The third contact plug 65 is abbreviated as a 'second storage node contact plug (Second SNC Plug)'. Therefore, the storage node contact plug according to the present embodiment has a stacked structure of the second contact plug and the third contact plug 65. [

The third contact plug 65 partially overlaps with the second plug 64. Thus, the third plug 65 exposes a part of the second plug 64 and its surrounding structure. That is, the top portion of the multiple spacers is partially exposed. A part of the first spacer 53, the sacrificial spacer 54, the second spacer 55 and the third spacer 52 is exposed by the third plug 65. [

The second plug 64 is etched to a certain depth by being self-aligned with the edge of the third contact plug 65. At this time, the first spacer 53, the sacrificial spacer 54, the second spacer 55, and the third spacer 62 are etched by being self-aligned to the edge of the third plug 64. In addition, portions of isolation layer 58 and bit line hardmask layer 52 are also etched to a certain depth. Thus, the recessed portion 65A is formed. A portion of the second plug 64 is covered by the third plug 65 and another portion of the second plug 64 is exposed by the recessed portion 65A. The etching process for forming the recessed portion 65A can use the mask pattern 65B as an etching barrier. The top portion of the sacrificial spacer 54 is exposed by the recessed portion 65A.

As shown in Fig. 6B, the sacrificial spacer 54 exposed under the recessed portion 65A is removed. The dip-out process is performed to remove the sacrificial spacer 54. The dip-out process includes a cleaning process. The cleaning process uses a wet chemical capable of removing the sacrificial spacers 54. The sacrificial spacers 54 under the third contact plug 65 are also removed by the wet chemical. The stripping process may include post-etch cleaning of the third contact plug 65, thereby eliminating the need for an additional process to remove the sacrificial spacers 54.

The sacrificial spacer 54 is removed by the dip-out process, and the space occupied by the sacrificial spacer 54 remains in the air gap 66. The air gap 66 may be formed in the periphery of the first contact plug 50 and in parallel along the sidewalls of the bit line 51.

As described above, an air gap 66 is formed not only around the first contact plug 50 but also around the bit line 51. Accordingly, a first spacer structure SP1 formed of a first spacer 53 and an air gap 66 is formed between the first contact plug 50 and the first plug 61. Since the first spacer 53 includes silicon nitride, a first spacer structure SP1 having a structure of 'Nitride-Air' is formed. A second spacer structure SP2 composed of a first spacer 53, an air gap 66, a second spacer 55 and a third spacer 62 is formed between the bit line 51 and the second plug 64 . Since the first spacer 53, the second spacer 55 and the third spacer 62 include silicon nitride, a second spacer structure SP2 having a structure of 'Nitride-Air-Nitride-Nitride' is formed. A portion of the air gap 66 in the second spacer structure SP2 is capped by the first spacer 53 and the second spacer 55. [

As shown in Fig. 6C, the capping layer 67 is formed after the mask pattern 65B is removed. The capping layer 67 comprises an insulating material. The capping layer 67 may comprise a material with poor step coverage. For example, the capping layer 67 may be formed using plasma enhanced chemical vapor deposition (PECVD), and thus capping the top portion of the air gap 66 to be clogged. The capping layer 67 comprises silicon oxide or silicon nitride. The capping layer 67 may comprise silicon nitride by plasma enhanced chemical vapor deposition (PECVD). The capping layer 67 caps the top of the air gap 66 while grabbing the recessed portion 65A. And also covers the upper portion of the third contact plug 65. The capping layer 67 may be used as an etch stop layer in subsequent etching processes.

A portion of the air gap 66 is capped by the second spacer 55 and the remaining portion of the air gap 66 is capped by the capping layer 67. [

As shown in FIG. 6D, a memory element is formed on the third contact plug 65. The memory element includes a storage node 68. For example, to form the storage node 68, a mold layer (not shown) is formed on the capping layer 67 and the mold layer and the capping layer 67 are etched to form the third contact plug 65 ) Is formed. Then, the storage node 68 is formed in the open portion, and then the mold layer is stripped. Although not shown, a dielectric layer and a plate node may be formed on the storage node 68. Storage node 68 may be in the form of a pillar, and in other embodiments may have a cylindrical shape. By forming the storage node 68 on the third plug 65, an overlap margin can be ensured.

As described above, the storage node contact plug formed between the substrate 51 and the storage node 68 includes a second contact plug and a third contact plug 65. The second contact plug includes a first plug (61) and a second plug (64). An ohmic contact layer 63 is formed between the first plug 61 and the second plug 64.

According to the embodiment described above, the parasitic capacitance is reduced by forming an air gap 66 between the storage node contact plug and the bit line 51 and between the first contact plug 50 and the storage node contact plug. The parasitic capacitance is reduced, so that the sensing margin can be improved.

Since the air gap 66 is formed parallel to the side wall of the bit line 51, the area of the storage node contact plug can be increased. That is, an air gap is formed to surround the side wall of the storage node contact plug, thereby reducing the contact resistance.

The contact resistance between the first plug 61 and the second plug 64 can be reduced by the ohmic contact layer 63 and the operation speed of the memory cell can be improved by improving the tWR have.

The semiconductor device according to the above-described embodiments may be applied to a dynamic random access memory (DRAM), and the present invention is not limited thereto. For example, a static random access memory (SRAM), a flash memory, a ferroelectric random access memory (FeRAM) (Magnetic Random Access Memory), and a PRAM (Phase Change Random Access Memory).

7 is a schematic view showing a memory card;

Referring to FIG. 7, the memory card 300 may include a controller 310 and a memory 320. Controller 310 and memory 320 may exchange electrical signals. For example, the memory 320 and the controller 310 can exchange data according to a command of the controller 310. [ Accordingly, the memory card 300 can store data in the memory 320 or output data from the memory 320 to the outside. The memory 320 may include a memory cell including an air gap as described above. The memory card 300 may be used as a data storage medium for various portable apparatuses. For example, the memory card 300 may be a memory stick card, a smart media card (SM), a secure digital (SD) card, a mini secure digital card, mini SD), or a multi media card (MMC).

8 is a block diagram showing an electronic system.

8, an electronic system 400 may include a processor 410, an input / output device 430, and a chip 420, which may communicate with each other using a bus 440 . The processor 410 may be responsible for executing the program and controlling the electronic system 400. The input / output device 430 may be used to input or output data of the electronic system 400. The electronic system 400 may be connected to an external device, e.g., a personal computer or network, using the input / output device 430 to exchange data with the external device. The chip 420 may store code and data for operation of the processor 410 and may process some of the operations provided in the process 410. For example, the chip 420 may include a memory cell including the air gap described above. The electronic system 400 may comprise various electronic control devices that require the chip 420 and may include a mobile phone, an MP3 player, navigation, a solid state disk (SSD) ), Household appliances, and the like.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined by the appended claims. Will be clear to those who have knowledge of.

41: substrate 43: active region
44: element isolation region 46: buried gate electrode
47: sealing layer 49: first contact hole
50: first contact plug 51: bit line
53: first spacer 55: second spacer
62: third spacer 59: second contact hole
61: first plug 63: ohmic contact layer
64: second plug 66: air gap
65: third contact plug 67: capping layer
SP1: first spacer structure
SP2: second spacer structure

Claims (20)

A plurality of bit line structures including a first contact plug on the substrate and a bit line on the first contact plug;
A spacer structure including an air gap formed in the sidewalls of the first contact plug and the bit line;
An isolation layer formed between the bit line structures and having an open portion;
A second contact plug formed in the open portion; And
The memory element on the second contact plug
.
The method according to claim 1,
Wherein the spacer structure comprises:
A first spacer structure formed between the first contact plug and the second contact plug; And
A second spacer structure formed between the bit line and the second contact plug
≪ / RTI >
3. The method of claim 2,
Wherein the first spacer structure includes a first nitride spacer formed on both sidewalls of the first contact plug and the air gap is formed between the first nitride spacer and the second contact plug.
3. The method of claim 2,
The second spacer structure comprises:
A first nitride spacer formed on both sidewalls of the bit line; And
And a second nitride spacer formed on a sidewall of the first nitride spacer,
Wherein the air gap is formed between the first nitride spacer and the second nitride spacer.
5. The method of claim 4,
Wherein the first nitride spacer and the second nitride spacer have different heights at opposite sidewalls of the bit line.
6. The method of claim 5,
Wherein the first nitride spacer and the second nitride spacer are asymmetric structures that expose a top portion of the air gap at one side wall of the bit line and cap a top portion of the air gap at another side wall of the bit line.
5. The method of claim 4,
And a third nitride spacer in contact with the second nitride spacer and surrounding an upper sidewall of the second contact plug.
The method according to claim 1,
And a part of the air gap extends in parallel along both side walls of the bit line.
The method according to claim 1,
And the second contact plug includes:
A silicon plug adjacent to the first contact plug;
A first metal plug formed on the silicon plug adjacent the bit line;
An ohmic contact layer formed between the silicon plug and the first metal plug;
≪ / RTI > The method according to claim 1,
And a third contact plug between the second contact plug and the memory element,
And said third contact plug overlaps a portion of said second contact plug, air gap and bit line structure.
Forming a bit line structure on the substrate, the bit line structure including a first contact plug and a bit line on the first contact plug;
Forming a multi-layer spacer including a first spacer, a sacrificial spacer and a second spacer on top and sidewalls of the bit line structure;
Forming a separation layer on the multi-layer spacer, the isolation layer including a contact hole exposing sidewalls of the first contact plug and the bit line;
A first plug adjacent to the first contact plug in the contact hole, a second plug adjacent to the bit line on the first plug, and a third spacer surrounding the side wall of the second plug in contact with the second spacer, Forming a second contact plug to form a second contact plug;
Partially removing the multi-layer spacer so that the sacrificial spacer is exposed; And
Removing the sacrificial spacers to form an extended air gap between the first contact plug and the first plug and between the bit line and the second plug;
≪ / RTI >
12. The method of claim 11,
The step of partially removing the multi-layer spacer to expose the sacrificial spacer comprises:
Forming a third contact plug simultaneously overlying the second contact plug, the multi-layer spacer, and a portion of the bit line structure on the second contact plug; And
Partially etching the multi-layer spacer to be aligned with the third contact plug
≪ / RTI >
13. The method of claim 12,
In the step of forming the air gap,
Wherein a part of the air gap is formed to be capped by the second spacer while being overlapped with the third contact plug, and the remainder of the air gap is formed to be non-overlappingly exposed to the third contact plug.
14. The method of claim 13,
After forming the air gap,
And forming a capping layer to cap the remaining of the air gap and the third contact plug.
15. The method of claim 14,
After forming the capping layer,
Forming a capacitor including a storage node coupled to the third contact plug through the capping layer
≪ / RTI >
12. The method of claim 11,
Wherein the first spacer, the second spacer, and the third spacer comprise silicon nitride, and the sacrificial spacer comprises silicon oxide.
12. The method of claim 11,
Wherein forming the bit line structure comprises:
Forming an interlayer insulating layer on the substrate;
Etching the interlayer insulating layer to form a first contact hole;
Burying the preliminary first contact plug in the first contact hole;
Forming a conductive layer on the preliminary first contact plug; And
Etching the conductive layer and the preliminary first contact plug so as to have a line width smaller than the diameter of the contact hole
≪ / RTI >
12. The method of claim 11,
Prior to forming the bit line structure,
And forming a buried gate type transistor including a gate electrode buried in said substrate.
12. The method of claim 11,
Wherein forming the second contact plug comprises:
Forming the first plug recessed in the contact hole;
Forming the third spacer on the first plug to cover a side wall of the contact hole;
Forming an ohmic contact layer on a surface of the first plug;
Forming the second plug to fill the contact hole on the ohmic contact layer
≪ / RTI >
12. The method of claim 11,
In forming the second contact plug,
Wherein the first plug includes a silicon plug, and the second plug includes a metal plug.

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