KR20150033495A - Semiconductor device - Google Patents

Abstract

A semiconductor device includes a semiconductor layer having a pair of source / drain regions and a channel region and extending in a first direction, a gate extending over the semiconductor layer to cover the channel region, a gate interposed between the channel region and the gate, Dielectric film. Corner insulating spacers extend along the sidewalls of the gate. The corner insulating spacer has a first surface covering at least a portion of the sidewall of the gate from one side of the gate dielectric layer and a second surface covering a portion of the semiconductor layer. An outer insulating spacer over the corner insulating spacer covers the side wall of the gate. The outer insulating spacer has a dielectric constant that is smaller than the dielectric constant of the corner insulating spacer.

Description

Semiconductor device

Technical aspects of the present invention relate to semiconductor devices, and more particularly to semiconductor devices including transistors.

As miniaturization and high integration of integrated circuit devices are required, there is a need to improve the operating speed, power dissipation and economic efficiency related characteristics to improve the overall operational stability of the transistors, Efforts are being made.

SUMMARY OF THE INVENTION The present invention is directed to a semiconductor device having a transistor capable of reducing a fringing capacitance and a parasitic capacitance to improve operation speed and reduce power consumption will be.

A semiconductor device according to an aspect of the present invention includes a pair of source / drain regions, a semiconductor layer having a channel region extending between the pair of source / drain regions and extending in a first direction, A gate extending in a second direction over the semiconductor layer to cover the channel region; a gate dielectric layer interposed between the channel region and the gate; and a gate dielectric layer extending in the second direction along a sidewall of the gate, A corner insulating spacer having a first surface that covers at least a portion of a side wall of the gate from a side of the gate insulating layer and a second surface that covers a portion of the semiconductor layer; Lt; RTI ID = 0.0 > dielectric < / RTI >

In some embodiments, the sidewall of the gate has a first height, and the first surface of the corner insulating spacer may cover the sidewall of the gate to a second height less than the first height.

In some embodiments, the outer insulating spacer may have a surface facing a side wall of the gate.

In some embodiments, the outer insulating spacer may have a third height that is greater than the first height.

In a semiconductor device according to an aspect of the technical idea of the present invention, the semiconductor layer may be a part of a bulk semiconductor substrate. The corner insulating spacer may extend along a sidewall of the gate at a reentrant corner portion formed between the gate and the pair of source / drain regions.

The semiconductor device according to an aspect of the technical idea of the present invention may further include a semiconductor substrate disposed under the gate. The semiconductor layer may include a semiconductor fin projecting from the semiconductor substrate and extending in a first direction.

In some embodiments, the semiconductor device may further include an element isolation film on the semiconductor substrate, the element isolation film being in contact with both side walls of the semiconductor fin and having a top surface level lower than the top surface of the semiconductor fin. The gate is extended in the second direction on the semiconductor fin and the device isolation film, and the corner insulating spacer has a concave corner formed between the gate and the semiconductor fin and the device isolation film. / RTI > may extend from the semiconductor fin along the sidewalls of the gate.

The semiconductor device according to an aspect of the present invention may further include a substrate disposed under the gate, and a buried insulating layer interposed between the substrate and the gate. The semiconductor layer may have a base portion extending in the first direction on the buried insulating layer and in contact with the buried insulating layer.

In some embodiments, the gate extends in the second direction over the semiconductor fin and the buried insulating layer, and the corner insulating spacer is formed between the gate, the semiconductor fin, and the buried insulating layer And may extend from the semiconductor fin along the sidewalls of the gate at a recessed corner.

In some embodiments, the pair of source / drain regions includes a source / drain extension region having a first doping concentration and a deep source / drain region having a second doping concentration higher than the first doping concentration And the corner insulating spacer may cover the source / drain extension region by a width less than the horizontal spacing distance between the gate and the deep source / drain region from the sidewall of the gate.

The corner insulating spacer may have a width in the horizontal direction selected from a side wall of the gate within a range of 1/2 of the horizontal spacing distance between the gate and the deep source / drain region.

According to another aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor layer having a channel region and extending in a first direction; an insulating layer covering at least a part of the semiconductor layer; A gate dielectric layer interposed between the channel region and the gate; a gate dielectric layer extending along the sidewall of the gate from the semiconductor layer and covering at least a portion of the sidewall of the gate; 1. A semiconductor device comprising: a corner insulating spacer having a surface and a second surface that covers a portion of the semiconductor layer; and an outer insulating spacer covering a sidewall of the gate over the corner insulating spacer and having a dielectric constant less than a dielectric constant of the corner insulating spacer .

In some embodiments, the corner insulating spacer may have a width less than a horizontal spacing distance from the side wall of the gate along the first direction to an outer wall of the outer insulating spacer.

In some embodiments, the corner insulating spacer may have a third surface that covers the insulating layer by a width less than a horizontal spacing distance from the sidewall of the gate along the first direction to the outer wall of the outer insulating spacer.

The semiconductor device according to the technical idea of the present invention includes a corner insulating spacer made of an insulating material having a relatively high dielectric constant in an inner portion that has a relatively large influence on the performance of the transistor among the insulating spacer region formed on the sidewall of the gate. Therefore, it is possible to suppress the occurrence of fringing capacitance, to improve the "on" current characteristic and the "off" current characteristic of the transistor, and to prevent the performance of the transistor from deteriorating. In addition, an outer insulating spacer made of an insulating material having a dielectric constant smaller than that of the corner insulating spacer is included in an outer portion of the insulating spacer region, the influence of which is relatively small on the performance of the transistor. Therefore, the parasitic capacitance can be reduced, the operation speed of the transistor can be improved, and the power consumption can be reduced.

1 is a cross-sectional view of a semiconductor device according to embodiments of the present invention.
2 is a cross-sectional view of a semiconductor device according to embodiments of the present invention.
FIGS. 3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to embodiments of the present invention. Referring to FIG.
4A to 4C are views for explaining a main configuration of a semiconductor device according to embodiments of the present invention. FIG. 4A is a partial perspective view of a semiconductor device, FIG. 4B is a cross- 4C is a vertical sectional view taken along the line 4C - 4C 'in Fig. 4A. Fig.
5A to 5K are cross-sectional views illustrating a method of manufacturing a semiconductor device according to embodiments of the present invention.
6 is a perspective view for explaining a main structure of a semiconductor device according to embodiments of the technical idea of the present invention.
FIGS. 7A and 7B are views for explaining a main configuration of a semiconductor device according to embodiments of the present invention. FIG. 7A is a partial perspective view of a semiconductor device, FIG. 7B is a cross- Sectional view along the line.
8A to 8G are cross-sectional views illustrating a method of fabricating a semiconductor device according to embodiments of the present invention.
9 is a perspective view for explaining a main structure of a semiconductor device according to embodiments of the present invention.
10 is a plan view of a memory module according to the technical idea of the present invention.
11 is a schematic block diagram of a display driver IC (DDI) according to embodiments of the present invention and a display device including the DDI.
12 is a circuit diagram of a CMOS inverter according to embodiments of the present invention.
13 is a circuit diagram of a CMOS SRAM device according to embodiments of the present invention.
14 is a circuit diagram of a CMOS NAND circuit according to embodiments of the present invention.
15 is a block diagram illustrating an electronic system according to embodiments of the present invention.
16 is a block diagram of an electronic system according to embodiments of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements in the drawings, and a duplicate description thereof will be omitted.

Embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The present invention is not limited to the following embodiments. Rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

Although the terms first, second, etc. are used herein to describe various elements, regions, layers, regions and / or elements, these elements, components, regions, layers, regions and / It should not be limited by. These terms do not imply any particular order, top, bottom, or top row, and are used only to distinguish one member, region, region, or element from another member, region, region, or element. Thus, a first member, region, region, or element described below may refer to a second member, region, region, or element without departing from the teachings of the present invention. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept belongs, including technical terms and scientific terms. In addition, commonly used, predefined terms are to be interpreted as having a meaning consistent with what they mean in the context of the relevant art, and unless otherwise expressly defined, have an overly formal meaning It will be understood that it will not be interpreted.

If certain embodiments are otherwise feasible, the particular process sequence may be performed differently from the sequence described. For example, two processes that are described in succession may be performed substantially concurrently, or may be performed in the reverse order to that described.

In the accompanying drawings, for example, variations in the shape shown may be expected, depending on manufacturing techniques and / or tolerances. Accordingly, embodiments of the present invention should not be construed as limited to any particular shape of the regions shown herein, but should include variations in shape resulting from, for example, manufacturing processes.

1 is a cross-sectional view of a semiconductor device 100A according to embodiments of the present invention. FIG. 1 illustrates a semiconductor device 100A made of a MOS transistor implemented in a bulk semiconductor substrate 102. FIG.

In the semiconductor substrate 102, an active region 106 is defined by an element isolation film 104. The active region 106 includes a pair of source / drain regions 110 and a channel region 112 extending between the pair of source / drain regions 110.

The semiconductor substrate 102 may comprise silicon (Si), for example crystalline Si, polycrystalline Si, or amorphous Si. In some other embodiments, the substrate 102 may be a semiconductor such as Ge (germanium), or a semiconductor such as SiGe, SiC, GaAs, InAs, ). ≪ / RTI >

A gate 120 is formed on the semiconductor substrate 102 to cover the active region 106 between the pair of source / drain regions 110. The gate 120 has a side wall 120S extending from the main surface 102M of the semiconductor substrate 102 to a predetermined height HAG in a direction perpendicular to the direction of extension of the main surface 102M I have. In the following description, "height" means the shortest distance extending in the direction (Z direction in Fig. 1) perpendicular to the main surface extending direction of the semiconductor substrate 102 unless otherwise defined.

In some embodiments, the gate 120 may be comprised of doped polysilicon, a metal, a conductive metal nitride, a metal suicide, an alloy, or a combination thereof. For example, the gate 120 may include at least one metal selected from Al, Ti, Ta, W, Ru, Nb, Mo, or Hf, or a nitride thereof.

The top surface of the gate 120 is covered by an insulating capping layer 122. In some embodiments, the insulating capping layer 122 may comprise a silicon nitride film, a silicon oxide film, or a combination thereof.

A gate dielectric layer 124 is interposed between the channel region 112 and the gate 120. In some embodiments, the gate dielectric 124 may comprise a silicon oxide film, or a high dielectric constant dielectric film higher than a silicon oxide film.

On both sides of the gate 120, a pair of corner insulating spacers 130 are formed extending along the sidewalls of the gate 120 and the upper surface of the source / drain region 110.

The pair of corner insulating spacers 130 are formed in a concave corner portion C1 formed between the gate 120 and the pair of source / drain regions 110, And extend along side wall 120S.

The pair of corner insulating spacers 130 each have a first surface 130a that covers at least a portion of the gate sidewall 120S from one side of the gate dielectric layer 124 adjacent the sidewall 120S of the gate 120 132 and a second surface 134 covering a portion of the source / drain region 110 from one side of the gate dielectric 124.

The first surface 132 of the pair of corner insulating spacers 130 may directly contact at least a portion of the sidewalls 120S of the gate 120. The second surface 134 may be in direct contact with the remaining portions of the pair of source / drain regions 110.

1, the first surface 132 of the pair of corner insulating spacers 130 has a first height HA1 that is less than the height HAG of the side wall 120S of the gate 120 And can cover the side wall 120S. However, the technical idea of the present invention is not limited thereto. For example, the first surface 132 of the pair of corner insulating spacers 130 may include a plurality of sidewalls 120S in a variety of ways, not exceeding the height HAG of the sidewalls 120S of the gate 120, Can be covered with a height.

A pair of outer insulating spacers 140 are formed on the pair of corner insulating spacers 130. The pair of outer insulating spacers 140 may extend on the semiconductor substrate 102 to a second height HA2 that is greater than the first height HA1. 1, the second height HA2 of the pair of outer insulating spacers 140 reaches the upper surface of the insulating capping layer 122. However, the technical idea of the present invention is not limited thereto. For example, the second height HA2 of the outer insulating spacer 140 is greater than the height HAG of the side wall 120S of the gate 120, that is, the height HAG of the insulating capping layer 122 Can be appropriately selected within the range from the upper surface to the upper surface.

The pair of outer insulating spacers 140 may have a surface that faces the remaining one of the two sidewalls 120S of the gate 120 that is not covered by the corner insulating spacer 130. [ The pair of outer insulating spacers 140 may have a surface that is in direct contact with the remaining portion of the sidewalls 120S of the gate 120 that is not covered by the corner insulating spacer 130. [ In some embodiments, when the sidewall 120S of the gate 120 is completely covered by the corner insulating spacer 130, the outer insulating spacer 140 may be formed above the corner insulating spacer 130, 122).

The pair of outer insulating spacers 140 has a dielectric constant that is smaller than the dielectric constant of the pair of corner insulating spacers 130.

In some embodiments, the pair of corner insulating spacers 130 can be made of a high dielectric constant dielectric film having a dielectric constant higher than that of the silicon oxide film. For example, the pair of corner insulating spacers 130 may have a dielectric constant of about 10 to 25. In some embodiments, the pair of corner insulating spacers 130 are formed of a material selected from the group consisting of hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium oxide nitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide Zirconium oxide (ZrSiO), zirconium oxide (ZrON), zirconium silicon oxide (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium At least one material selected from strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), or lead scandium tantalum oxide (PbScTaO) . However, the material constituting the pair of corner insulating spacers 130 is not limited to those exemplified above.

For example, the pair of corner insulating spacers 130 may be formed of a silicon oxide film. In this case, the pair of outer insulating spacers 140 may be formed of a film having a dielectric constant smaller than that of the silicon oxide film. For example, at least a portion of the pair of outer insulating spacers 140 may comprise an air spacer. In some embodiments, the pair of outer insulating spacers 140 may comprise a silicon oxide spacer, a silicon nitride spacer, an air spacer, or a combination thereof. In some embodiments, the pair of corner insulating spacers 130 may comprise a silicon oxide layer, and the pair of outer insulating spacers 140 may have a multilayer structure including air spacers. For example, the pair of outer insulating spacers 140 may include an air spacer adjacent to the corner insulating spacer 130, a silicon oxide film spaced apart from the corner insulating spacer 130 by the air spacer, Layer structure. In some other embodiments, the pair of corner insulating spacers 130 are comprised of a silicon nitride film, and the pair of outer insulating spacers 140 may be a single layer structure of a silicon oxide film, Layer structure. In some further embodiments, the pair of corner insulating spacers 130 are comprised of a hafnium oxide film, and the pair of outer insulating spacers 140 are formed of a silicon oxide film, a silicon nitride film, an air spacer, Lt; / RTI > According to the technical idea of the present invention, the combination of the material of the pair of corner insulating spacers 130 and the pair of outer insulating spacers 140 is not limited to the above example. The pair of corner insulating spacers 130 may be made of an insulating material having a relatively high dielectric constant and the pair of outer insulating spacers 140 may have various dielectric constants This is possible.

The pair of source / drain regions 110 includes a source / drain extension region 110A having a relatively low impurity doping concentration and a deep source / drain extension region 110A having a higher impurity doping concentration in the source / drain extension region 110A. Region 110B.

The pair of corner insulating spacers 130 may cover the source / drain extension region 110A by a width smaller than a predetermined horizontal separation distance L1 from the side wall 120S of the gate 120, respectively. In this specification, unless otherwise defined, the term "horizontal spacing distance" refers to the direction of extension of the main surface of the semiconductor substrate 102, particularly in the same direction as the direction of the channel formed in the channel region 106 Means the shortest distance.

In some embodiments, the horizontal spacing L1 may be a horizontal spacing distance from the side wall 120S of the gate 120 to the deep source / drain region 110B. That is, the pair of corner insulating spacers 130 are spaced apart from each other by a width smaller than the horizontal spacing distance L1 from the side wall 120S of the gate 120 to the deep source / drain region 110B, (110A). In some other embodiments, the horizontal spacing L1 may be a horizontal distance from the sidewall 120S of the gate 120 to the outer wall of the outer insulating spacer 140. That is, the pair of corner insulating spacers 130 are spaced apart from each other by a width smaller than the horizontal spacing distance L1 from the side wall 120S of the gate 120 to the outer wall of the outer insulating spacer 140, (110A).

In some embodiments, the pair of corner insulating spacers 130 are spaced from the sidewall 120S of the gate 120 by a horizontal spacing L1 between the gate 120 and the deep source / drain region 110B, And a width in the horizontal direction that is selected within a range up to a distance of 1/2 of the width. In some other embodiments, the pair of corner insulating spacers 130 are spaced at a distance of 1/2 of the horizontal spacing L1 from the side wall 120S of the gate 120 to the outer wall of the outer insulating spacer 140 And a width in a horizontal direction that is selected within a range of up to < RTI ID = 0.0 >

The semiconductor device 100A illustrated in FIG. 1 includes an insulating spacer region 111 formed in a concave corner portion C1 formed between a source / drain region 110 formed in a semiconductor substrate 102 and a side wall of a gate 120, A corner insulating spacer 130 made of an insulating material having a relatively high dielectric constant is disposed on the inner side portion which relatively affects the performance of the transistor and thus the distance between the source / drain region 110 and the gate 120 The occurrence of fringing capacitance can be suppressed. Therefore, it is possible to improve the "on" current characteristic and the "off" current characteristic of the transistor and prevent the performance of the transistor from deteriorating. In addition, in the outer portion of the insulating spacer region formed on the concave corner portion C1 on both sides of the gate 120 and having a relatively small influence on the performance of the transistor, a portion having a dielectric constant smaller than that of the corner insulating spacer 130 By forming the outer insulating spacer 140 made of an insulating material, the parasitic capacitance in the semiconductor device 100A can be reduced. Therefore, the operation speed of the transistor including the gate 120 can be improved and power consumption can be reduced.

2 is a cross-sectional view of a semiconductor device 100B according to embodiments of the present invention. In FIG. 2, the same reference numerals as in FIG. 1 denote the same members, and a detailed description thereof will be omitted here.

2, the semiconductor device 110B includes corner insulation spacers 130P on either side of the gate 120 that extend along the sidewalls of the gate 120 and the top surface of the source / drain region 110, respectively do.

The corner insulating spacer 130P includes a first surface 132P covering a side wall 120S of the gate 120 from one side of the gate dielectric 124 adjacent to the side wall 120S of the gate 120, And a second surface 134P that covers a portion of the pair of source / drain regions 110 from one side of the source / drain region 124. The first surface 132P may have a height HA1 'capable of covering the sidewall 120S of the gate 120 up to the height of the upper surface of the gate 120. [ Thus, the first surface 132P may cover substantially all of the sidewalls 120S of the gate 120. The first surface 132P may be in direct contact with the sidewall 120S of the gate 120. The second surface 134P may be in direct contact with a portion of the pair of source / drain regions 110.

A pair of outer insulating spacers 140P covering the pair of corner insulating spacers 130P are spaced apart from the gate 120 with the corner insulating spacer 130P interposed therebetween. The pair of outer insulating spacers 140P may cover at least a portion of both sidewalls of the insulating capping layer 122.

The pair of outer insulating spacers 140P has a dielectric constant that is smaller than the dielectric constant of the pair of corner insulating spacers 130P. More details about the pair of corner insulating spacers 130P and the pair of outer insulating spacers 140P will be described with reference to FIG. 1 by a pair of corner insulating spacers 130 and a pair of outer insulating spacers 140. [ As described above.

The semiconductor device 100B illustrated in FIG. 2 includes an insulating spacer region 102 formed in a concave corner portion C1 formed between a source / drain region 110 formed in a semiconductor substrate 102 and a sidewall of the gate 120, A corner insulating spacer 130P made of an insulating material having a relatively high dielectric constant is disposed on the inner side portion having a relatively large influence on the performance of the transistor, so that the fringing capacitance between the source / drain region 110 and the gate 120 Can be suppressed. Therefore, it is possible to improve the "on" current characteristic and the "off" current characteristic of the transistor and prevent the performance of the transistor from deteriorating. In the outer portion of the insulating spacer region formed on the concave corner portion C1 on both sides of the gate 120 and having a relatively small influence on the performance of the transistor, By forming the outer insulating spacer 140P made of an insulating material, parasitic capacitance can be reduced in the semiconductor device 100B. Therefore, the operation speed of the transistor including the gate 120 can be improved and power consumption can be reduced.

FIGS. 3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to embodiments of the present invention. Referring to FIG. In this example, a process of manufacturing the semiconductor device 100A shown in Fig. 1 will be described as an example. However, within the scope of the technical idea of the present invention, the processes described with reference to Figs. 3A to 3F can also be applied to the manufacturing process of the semiconductor device 100B exemplified in Fig. In Figs. 3A to 3F, the same reference numerals as in Fig. 1 denote the same members, and a detailed description thereof will be omitted here.

Referring to FIG. 3A, an element isolation film 104 defining an active region 106 is formed on a semiconductor substrate 102. As shown in FIG.

The device isolation film 104 may be formed of a silicon oxide film, a silicon nitride film, or a combination thereof.

A dielectric film 124L, a conductive layer 120L, and an insulating layer 122L are formed in this order on the semiconductor substrate 102. [

The dielectric layer 124L may be formed of silicon oxide or a high-k dielectric layer. In some embodiments, the high-k dielectric layer includes at least one of hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium oxide nitride (HfON), hafnium silicon oxide nitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide ), Zirconium oxide (ZrO), zirconium silicon oxide (ZrSiO), zirconium oxide nitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO) And at least one material selected from barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO). In some embodiments, an ALD (atomic layer deposition) process, a CVD (chemical vapor deposition) process, or a thermal oxidation process may be used to form the dielectric layer 124L.

The conductive layer 120L may be formed of a doped polysilicon, a metal, a conductive metal nitride, a metal silicide, an alloy, or a combination thereof. For example, the conductive layer 120L may include a nitride of at least one metal selected from Al, Ti, Ta, W, Ru, Nb, Mo, or Hf. The conductive layer 120L may have a single layer or a multilayer form. In some embodiments, a CVD (chemical vapor deposition) process, a MOCVD (metal organic CVD) process, an ALD (atomic layer deposition) process, or a MOALD (metal organic ALD) process is used to form the conductive layer 120L But is not limited thereto.

The insulating layer 122L may be a silicon nitride layer, a silicon oxide layer, or a combination thereof.

Referring to FIG. 3B, after a mask pattern (not shown) is formed on the insulating layer 122L shown in FIG. 3A, the insulating layer 122L is etched using the mask pattern as an etching mask, The conductive layer 120L and the dielectric layer 124L are sequentially etched using the insulating capping layer 122 as an etch mask to form the gate 120 and the gate dielectric layer 124. [

In some embodiments, the gate 120 may be formed to have a line width WLl of about 10-30 nm. In this case, the gate 120 may have a gate length corresponding to the line width WL1. However, according to the technical idea of the present invention, the line width of the gate 120 is not limited to the above example, but may be formed to have various line widths.

Between the gate 120 and the semiconductor substrate 102 on either side of the gate 120, a concave corner C1 is formed to expose the gate dielectric 124.

Referring to FIG. 3C, impurity ions IIP1 having a first doping concentration are implanted into the semiconductor substrate 102 using the insulating capping layer 122 as an ion implantation mask, Drain extension region 110A having a relatively shallow depth in the source / drain extension region 102 is formed. In some embodiments, the first doping concentration of the impurity ion (IIP1) may be variously determined depending on the design of the semiconductor element 100A.

In some embodiments, the impurity ion (IIP1) implantation process for forming the source / drain extension region 110A is not performed at this stage, but the pair of corner insulation spacers 130 described with reference to FIG. May be performed after the forming process.

In some embodiments, the exposed surface of the semiconductor substrate 102 and the exposed surface of the gate 120 are protected prior to implanting an impurity ion (IIP1) implantation process to form the source / drain extension region 110A And after the source / drain extension region 110A is formed, a step of removing the oxide thin film by a wet etching process can be performed.

Referring to FIG. 3D, a first insulating spacer film (not shown) extending conformally along the laminated structure of the gate 120 and the insulating capping layer 122 and the exposed surface of the semiconductor substrate 102 is formed , The first insulating spacer film is etched back to form a corner insulating spacer 130 on the concave corner portion (C1).

In some embodiments, the corner insulating spacers 130 may have the shape of a pair of corner insulating spacers 130 positioned one on each side of the gate 120. In some other embodiments, the corner insulating spacers 130 may have a ring shape surrounding the gate 120 around the gate 120.

The width CW1 of the corner insulating spacer 130 can be controlled by the thickness of the first insulating spacer film. The height CHA1 of the pair of corner insulating spacers 130 can be controlled by the time during which the etch-back process of the first insulating spacer film is performed. In some embodiments, the corner insulating spacers 130 are selected to have a width CW1 selected within a range of about 1 to 20 nm and a height CHA1 selected within a range of about 3 to 60 nm But is not limited thereto. The height CHA1 of the pair of corner insulating spacers 130 may correspond to the first height HA1 illustrated in FIG.

In some embodiments, the source / drain extension region 110A formation process described with reference to FIG. 3C may not be performed prior to the corner insulation spacer formation process. In this case, the impurity ion (IIP1) implantation process for forming the source / drain extension region 110A as described with reference to FIG. 3C may be performed after the step of forming the pair of corner insulation spacers 130 described with reference to FIG. 3D . In this case, after the impurity ions IIP1 are implanted into the semiconductor substrate 102, the impurity ions IIP1 implanted into the semiconductor substrate 102 are diffused horizontally to the edge of the side wall 120S of the gate 120 . At this time, by controlling the horizontal diffusion distance of the impurity ions IIP1 in the semiconductor substrate 102, the overlap area between the gate 120 and the source / drain extension region 110A can be reduced. Thereby increasing the effective gate length of the MOS transistor and reducing the gate induced drain leakage (GIDL) and the overlap capacitor generated in the MOS transistor.

3E, a laminated structure of the gate 120, the insulating capping layer 122, and the corner insulating spacer 130 and the exposed surface of the semiconductor substrate 102 are formed on the resultant structure in which the corner insulating spacer 130 is formed The second insulating spacer film is etched back so as to cover the corner insulating spacer 130 in the concave corner portion C1 (see FIG. 3C), thereby forming a second insulating spacer film (not shown) Thereby forming an outer insulating spacer 140.

The second insulating spacer film and the outer insulating spacer 140 obtained therefrom are made of a material having a smaller dielectric constant than the constituent material of the corner insulating spacer 130.

In some embodiments, the outer insulating spacers 140 may have the shape of a pair of outer insulating spacers 140 positioned one on each side of the gate 120. In some other embodiments, the outer insulating spacers 140 may have a ring shape surrounding the gate 120 around the gate 120.

The width OW1 of the outer insulating spacer 140 can be controlled by the thickness of the second insulating spacer film. The height OHA1 of the outer insulating spacer 140 can be controlled by the time during which the etch-back process of the second insulating spacer film is performed. By controlling the width OW1 of the outer insulating spacer 140, the ratio of the width of the sidewall spacers, which is determined by the corner insulating spacers 130 and the outer insulating spacers 140, to the corner insulating spacers 130 is determined . The width of the sidewall spacers may correspond to the width OW1 of the outer insulating spacers 140. The height OHA1 of the outer insulating spacer 140 may correspond to the second height HA2 illustrated in FIG.

Referring to FIG. 3F, impurity ions (IIP2) having a second doping concentration higher than the first doping concentration are implanted into the semiconductor substrate 102 using the insulating capping layer 122 and the outer insulating spacer 140 as an ion implantation mask. Drain regions 110B are formed in the semiconductor substrate 102 on both sides of the gate 120. The source / In some embodiments, the second doping concentration of the impurity ion (IIP2) may be variously determined according to the design of the semiconductor element 100A.

The source / drain extension region 110A and the deep source / drain region 110B constitute a source / drain region 110.

In some embodiments, an oxide thin film for protecting the exposed surface of the semiconductor substrate 102 is formed before implanting the impurity ions IIP2 to form the deep source / drain region 110B, After the deep source / drain region 110B is formed, a step of removing the oxidation foil by a wet etching process may be performed.

Thereafter, the resultant structure in which the corner insulating spacer 130, the outer insulating spacer 140, and the pair of source / drain regions 110 are formed may be covered with an interlayer insulating film and a normal contact forming process may be performed.

4A to 4C are diagrams for explaining a main configuration of a semiconductor device 200A according to embodiments of the present invention. FIG. 4A is a partial perspective view of the semiconductor device 200A, FIG. 4B is a cross- 4B is a vertical sectional view along line 4B-4B 'of FIG. 4A, and FIG. 4C is a vertical sectional view along line 4C-4C' of FIG. 4A to 4C illustrate a semiconductor device 200A comprising a finFET manufactured from an SOI wafer.

The semiconductor device 200A is implemented on an SOI wafer 208 that includes a substrate 202, semiconductor fins 204, and a buried insulating layer 206 interposed therebetween. The semiconductor fin 204 extends in one direction (X direction in FIG. 4A) above the buried insulating layer 206. 4A to 4C illustrate the semiconductor device 200A having one semiconductor fin 204, the technical idea of the present invention is not limited thereto. The semiconductor device according to the technical idea of the present invention may include various numbers of semiconductor fins as required in the design. Further, the number of the semiconductor fins 204 may be determined according to other factors, for example, the physical size, operating voltage, current, or the like of the finFET constituting the semiconductor device.

In some embodiments, the substrate 202 may be made of Si. In some embodiments, the semiconductor fin 204 may comprise Si, for example crystalline Si, polycrystalline Si, or amorphous Si. In some other embodiments, the semiconductor fin 204 may comprise a semiconductor such as Ge, or a compound semiconductor such as SiGe, SiC, GaAs, InAs, InP, and the like. The buried insulating layer 206 may be an oxide layer.

The semiconductor fin 204 includes a pair of source / drain regions 210 and a channel region 212 extending between the pair of source / drain regions 210.

A gate 220 is formed on the channel region 212 of the semiconductor fin 204. The gate 220 extends in a direction (Y direction in FIG. 4A) that intersects the extending direction of the semiconductor fin 204 (X direction in FIG. 4A).

The gate 220 constitutes a MOS transistor TR1. The MOS transistor TR1 includes a MOS transistor of a three-dimensional structure in which a channel is formed on the upper surface and both sides of the semiconductor fin 204. [

The portion of the gate 220 positioned above the semiconductor fin 204 may have a thickness equal to or greater than the thickness along the vertical direction of the semiconductor fin 204 (Z direction in FIG. 4A) The technical idea is not limited to this.

The gate 220 has a side wall 220S extending from the buried insulating layer 206 in a vertical direction (Z direction in FIG. 4A) to a predetermined height HBG.

In some embodiments, the gate 220 may be comprised of doped polysilicon, a metal, a conductive metal nitride, a metal suicide, an alloy, or a combination thereof. For example, the gate 220 may include a nitride of at least one metal selected from Al, Ti, Ta, W, Ru, Nb, Mo, or Hf.

The upper surface of the gate 220 is covered by an insulating capping layer 222. In some embodiments, the insulating capping layer 222 may be a silicon nitride film, a silicon oxide film, or a combination thereof.

A gate dielectric layer 224 is interposed between the channel region 212 and the gate 220. The gate dielectric layer 224 may be a silicon oxide layer or a high-k dielectric layer having a dielectric constant higher than that of the silicon oxide layer.

Corner insulating spacers 230 extending along the surfaces of the sidewalls 220S and the buried insulating layer 206 of the gate 220 are formed on both sides of the gate 220, respectively.

The corner insulating spacer 230 includes a gate 220, a pair of source / drain regions 210 formed in the semiconductor fin 204, and a recessed corner C2 formed between the buried insulating layer 206 (See FIG. 5D) of the gate 220 (see FIG.

4B, the corner insulating spacers 230 may include at least a portion of the gate 220 side wall 220S from one side of the gate dielectric layer 224 adjacent the side wall 220S of the gate 220 And a second surface 234 (see FIG. 5E) that covers a portion of the pair of source / drain regions 210. The second surface 234 (see FIG. The first surface 232 of the corner insulating spacer 230 may directly contact at least a portion of the sidewall 220S of the gate 220. [ The second surface 234 may be in direct contact with a portion of the pair of source / drain regions 210.

The first surface 232 of the corner insulating spacer 230 covers the sidewall 220S of the gate 220 to a first height HB1 that is less than the height HBG of the sidewall 220S. However, the technical idea of the present invention is not limited thereto. The first surface 232 of the corner insulating spacer 230 may cover the sidewall 220S at various heights within a range that does not exceed the height HBG of the sidewall 120S of the gate 120 .

A pair of outer insulating spacers 240 are formed on the pair of corner insulating spacers 230. The pair of outer insulating spacers 240 may extend over the buried insulating layer 206 to a second height HB2 that is greater than the first height HB1. 4A to 4C, the second height HB2 of the outer insulating spacer 240 is higher than the height HBG of the sidewall 220S of the gate 220, that is, the upper surface of the gate 220, 222. However, the technical idea of the present invention is not limited to this. For example, the second height HB2 of the outer insulating spacer 140 may be less than the required height HB1 within the range between the first height HB1 of the corner insulating spacer 230 and the height of the top surface of the insulating capping layer 122 And can be selected accordingly.

The outer insulating spacer 240 may have a surface that faces the remaining portion of the sidewall 220S of the gate 220 that is not covered by the corner insulating spacer 230. The outer insulating spacer 240 may have a surface that is in direct contact with the remaining portion of the sidewall 220S of the gate 220 that is not covered by the corner insulating spacer 230. In some embodiments, when the sidewall 220S of the gate 220 is completely covered by the corner insulating spacer 230, the outer insulating spacer 240 may be formed above the corner insulating spacer 230, 222, respectively.

The outer insulating spacer 240 has a dielectric constant that is smaller than the dielectric constant of the corner insulating spacer 230.

For details of the corner insulating spacer 230 and the outer insulating spacer 240, refer to FIG. 1 and described with respect to the corner insulating spacer 130 and the outer insulating spacer 140.

The pair of source / drain regions 210 includes a source / drain extension region 210A having a relatively low impurity doping concentration and a deep source / drain extension region 210A having a higher impurity doping concentration in the source / drain extension region 210A. Region 210B.

The corner insulating spacers 230 each have a width CW2 that is smaller than a horizontal spacing distance L2 from the side wall 220S of the gate 220 to the outer wall of the outer insulating spacer 240 along the side wall of the semiconductor fin 204, (See FIG. 4B). The corner insulating spacer 230 covers the source / drain region 110 formed in the semiconductor fin 204 on the sidewall of the semiconductor fin 204 by the width CW2. The corner insulating spacer 230 covers the embedded insulating layer 206 by the width CW2 within a distance corresponding to the horizontal spacing distance L2 from the side wall 220S of the gate 220. [

In some embodiments, the width CW2 in the horizontal direction of the corner insulating spacer 230 can be selected within a range of 1/2 of the horizontal spacing L2 from the side wall 220S of the gate 220 have.

In some embodiments, the source / drain extension region 210A in the source / drain region 110 may be omitted. In this case, the deep source / drain region 210B may be formed over the region extended from the region illustrated in FIG. 4C to the side wall 220S edge side of the gate 220.

The semiconductor fin 204, the gate 220 and the embedded insulating layer 206 in the insulating spacer region extending along the sidewall 220S of the gate 220 in the semiconductor device 200A illustrated in Figs. 4A to 4C. A corner insulating spacer 230 made of an insulating material having a relatively high dielectric constant is disposed in the inner portion of the concave corner portion C2 (see FIG. Therefore, it is possible to suppress the occurrence of fringing capacitance in the semiconductor device 200A, to improve the "on" current characteristic and the "off" current characteristic of the transistor, and the performance of the transistor to deteriorate . In addition, an outer insulating spacer 240 made of an insulating material having a dielectric constant smaller than that of the corner insulating spacer 230 is formed at an outer portion of the insulating spacer region formed in the concave corner portion C2. Therefore, the parasitic capacitance of the semiconductor device 200A is reduced, so that the operating speed of the transistor can be improved and power consumption can be reduced.

5A to 5K are cross-sectional views illustrating a method of manufacturing a semiconductor device according to embodiments of the present invention. In this example, a process for manufacturing the semiconductor device 200A shown in Figs. 4A to 4C will be described as an example. 5A to 5K, the same reference numerals as in Figs. 4A to 4C denote the same members, and a detailed description thereof will be omitted here.

5A, an SOI wafer 208 including two semiconductor layers and a buried insulating layer 206 therebetween is prepared. Then, an upper semiconductor (not shown) on the buried insulating layer 206 of the two semiconductor layers, The layer is partially removed to leave the semiconductor fin pattern 204X on the buried insulating layer 206. [ The semiconductor layer under the buried insulating layer 206 of the two semiconductor layers may remain as the substrate 202.

The semiconductor fin pattern 204X extends in one direction (X direction in Fig. 5) on the buried insulating layer 206. [ The semiconductor fin pattern 204X has a base portion 204B contacting the buried insulating layer 206. [

Although only one semiconductor fin pattern 204X is shown in FIG. 5A, the technical idea of the present invention is not limited thereto, and various numbers of semiconductor fin patterns 204X may be formed as required in the design .

In some embodiments, the substrate 202 and the semiconductor fin pattern 204X may each be made of silicon.

5B, a dielectric layer 224L covering the exposed surface of the semiconductor fin pattern 204X illustrated in FIG. 5A and the exposed surface of the buried insulating layer 206 is formed, and an upper surface planarized on the dielectric layer 224L is formed Thereby forming the gate-forming conductive layer 220L.

The dielectric layer 224L may be formed of silicon oxide or a high dielectric constant layer. The conductive layer 220L may be formed of doped polysilicon, a metal, a conductive metal nitride, a metal silicide, an alloy, or a combination thereof. For details of the dielectric layer 224L and the conductive layer 220L, reference is made to the description of the dielectric layer 124L and the conductive layer 120L with reference to FIG. 3A.

5C, an insulating capping layer 222 is formed on the conductive layer 220L illustrated in FIG. 5B using a photolithography process, and the insulating capping layer 222 is formed on the conductive layer 220 220L and the dielectric film 224L are etched in order to form the gate 220 and the gate dielectric film 224.

The gate 220 extends in a direction (Y direction in FIG. 5C) intersecting the extending direction of the semiconductor fin pattern 204X. In some embodiments, the gate 220 may be formed to have a line width WL2 of about 10-30 nm, but is not limited thereto.

The conductive layer 220L and the dielectric film 224L are sequentially etched using the insulating capping layer 222 as an etch mask to form a gate 220 and a gate dielectric film 224. [

The gate 220 extends in a direction (Y direction in FIG. 5C) intersecting the extending direction of the semiconductor fin pattern 204X. In some embodiments, the gate 220 may be formed to have a line width WL2 of about 10-30 nm, but is not limited thereto.

On both sides of the gate 220, corner portions C2 are provided between the gate 220, the semiconductor fin pattern 204X and the buried insulating layer 206, respectively. And the gate dielectric film 224 is exposed at the concave corner portion C2.

5D, impurity ions IIP1 of a first doping concentration are injected into the semiconductor fin pattern 204X using the insulating capping layer 222 as an ion implantation mask to form semiconductor pin patterns Drain extension region 210A is formed in the source / drain extension region 204X. The first doping concentration of the impurity ion (IIP1) may be variously determined according to the design of the semiconductor element 200A.

In some embodiments, the process of implanting the impurity ions IIP1 to form the source / drain extension region 210A is not performed in this step, but is performed in a process of forming the corner insulating spacer 230 described with reference to FIG. 5E May be performed later.

In some embodiments, the exposed surface of the semiconductor fin pattern 204X and the exposed surface of the gate 220 are protected prior to implanting an impurity ion (IIP1) implantation process to form the source / drain extension region 210A. And after the source / drain extension region 210A is formed, a step of removing the oxide thin film by a wet etching process can be performed.

The gate 220, the gate dielectric layer 224, the source / drain extension region 210A and the buried insulating layer 206 are exposed at the corners C2 concaved at both sides of the gate 220. [

In some embodiments, the impurity ion (IIP1) implantation process described with reference to FIG. 5D may be omitted, and thus the source / drain extension region 210A may not be formed in the semiconductor fin pattern 204X.

5E, a first insulating spacer film (not shown) extending conformally along the exposed surface of the semiconductor fin pattern 204X and the stacked structure of the gate 220 and the insulating capping layer 222 is formed Thereafter, the first insulating spacer film is etched back to form corner insulating spacers 230 on the concave corner portions C2. In forming the corner insulating spacer 230, the etch-back time of the first insulating spacer film may be controlled so that the first insulating spacer film remains on the upper surface of the semiconductor fin pattern 204X.

5E) of the laminated structure of the gate 220 and the insulating capping layer 222 is set to a height in the vertical direction of the semiconductor fin pattern 204X . Here, the height of the lamination structure of the gate 220 and the insulating capping layer 222 may be sufficiently larger than the vertical height of the semiconductor fin pattern 204X. In this way, while the first insulating spacer film is etched back until the corner insulating spacer 230 having the desired height remains on both side walls of the gate 220, the side wall of the semiconductor fin pattern 204X, The first insulating spacer film can be completely removed over the portion of the sidewall spaced from the gate 220. [ As a result, the side wall of the semiconductor fin pattern 204X can be exposed at the concave corner portion C2.

The corner insulating spacer 230 may be selected to have a width CW2 selected within a range of about 1 to 20 nm and a height CH2 selected within a range of about 3 to 60 nm, It is not. The height CH2 may correspond to the first height HB1 illustrated in Figs. 4A and 4B.

In some embodiments, the source / drain extension region 210A formation process described with reference to FIG. 5D may not be performed prior to the corner insulation spacer 230 formation process. In this case, the impurity ion (IIP1) implantation process for forming the source / drain extension region 210A as described with reference to FIG. 5D can be performed after the corner insulation spacer 230 formation process described with reference to FIG. 5E . In this case, after the impurity ions IIP1 are implanted into the semiconductor fin pattern 204X, the impurity ions IIP1 injected into the semiconductor fin pattern 204X can be diffused to the side wall edge portions of the gate 220. [

5f, the exposed surfaces of the laminated structure of the gate 220, the insulating capping layer 222, and the corner insulating spacer 130 on the resultant structure in which the corner insulating spacer 230 is formed on both sides of the gate 220 , A second insulating spacer film (not shown) extending conformally along the exposed surface of the semiconductor fin pattern 204X and the exposed surface of the buried insulating film 206 is formed, and then the second insulating spacer film is etched back And a pair of outer insulating spacers 240 covering the pair of corner insulating spacers 230 are formed at the concave corner portions C2 (see FIG. 5E).

The outer insulating spacer 240 is made of a material having a dielectric constant smaller than that of the corner insulating spacer 230.

The width OW2 of the outer insulating spacer 240 can be controlled by the thickness of the second insulating spacer film. The height OH2 of the outer insulating spacer 240 can be controlled by the time during which the etch-back process of the second insulating spacer film is performed. The height OH2 of the outer insulating spacer 240 may correspond to the second height HB2 illustrated in Figs. 4A and 4B.

5G, an epitaxial semiconductor layer 210EP is formed on the exposed surface of the semiconductor fin pattern 204X illustrated in FIG. 5F, so that the semiconductor fin pattern 204X and the semiconductor made of the epitaxial semiconductor layer 210EP Thereby forming the pin 204.

The semiconductor layer may be epitaxially grown from the exposed surface of the semiconductor fin pattern 204X using a selective epitaxial growth (SEG) process to form the epitaxial semiconductor layer 210EP.

In some embodiments, the epitaxial semiconductor layer 210EP may be made of the same semiconductor material as the semiconductor material that constitutes the semiconductor fin pattern 204X. In some other embodiments, the epitaxial semiconductor layer 210EP may be made of a semiconductor material different from the semiconductor material constituting the semiconductor fin pattern 204X. For example, the epitaxial semiconductor layer 210EP may be made of Si, Ge, SiGe, SiC, or a combination thereof.

In some embodiments, a reduced pressure CVD (RPCVD) process may be used to form the epitaxial semiconductor layer 210EP. Depending on the composition of the precursor which may be used during epitaxial semiconductor layer (210EP) form is to be formed, may comprise a Si-containing gas and / or Ge-containing gas such as SiH _4, GeH _4. When the SiGe layer is formed as the epitaxial semiconductor layer 210EP, the atomic ratio of Ge to Si can be controlled by controlling the partial pressures of the Si-containing gas and the Ge-containing gas.

During the epitaxial growth process for forming the epitaxial semiconductor layer 210EP, facets can be formed due to the different growth rates at different crystal planes. For example, the growth rate in the (111) plane may be lower than the growth rate in the other plane, such as the (110) plane and the (100) plane. Etching gas such as HCl gas may be added to the process gas during the epitaxial growth process to remove the facets that are formed due to the difference in growth rate of the different crystal planes. In this case, epitaxial growth and etching are performed in-situ in the same chamber so that the epitaxial semiconductor layer 210EP can be formed to have a round-shaped surface profile.

The epitaxial semiconductor layer 210EP constitutes a source / drain region through a subsequent ion implantation process together with the semiconductor fin pattern 204X.

Depending on the channel type in the channel region of the semiconductor fin 204, the epitaxial semiconductor layer 210EP may be formed of a material that induces a tensile strain or a compressive strain. Such a strain can contribute to improving the performance of the transistor, for example, the mobility. For example, the epitaxial semiconductor layer 210EP constituting the semiconductor fin 204 in which the N channel is formed is formed of SiC so as to induce tensile strain, and the epitaxial semiconductor layer 210EP constituting the semiconductor fin 204 constituting the P- The taxi semiconductor layer 210EP may be formed of SiGe to cause a compressive strain, but the technical idea of the present invention is not limited thereto.

The semiconductor fin 204 may include an epitaxial semiconductor layer 210EP so that the source / drain formed on the semiconductor fin 204 may have a raised source / drain (RSD) structure.

5H, an impurity ion (IIP2) having a second doping concentration higher than the first doping concentration is applied to the semiconductor fin 204 by using an insulating capping layer 222 and an outer insulating spacer 240 as an ion implantation mask. Drain regions 210B (see FIG. 4C) are formed on the semiconductor fins 204 on both sides of the gate 220 to form the source / drain regions 210.

In some embodiments, the source / drain extension region 210A formation process described with reference to FIG. 5D may be omitted. In this case, the source / drain region 210 may be formed in the semiconductor fin 204 only by implanting the impurity ions (IIP2) described with reference to FIG. 5H.

Since the source / drain region 210 has an RSD structure including the epitaxial semiconductor layer 210EP, the thickness of the source / drain region 210 increases, and the overall parasitic resistance can be reduced.

Although not shown, a salicide process may be performed on the surface of the source / drain region 210 to reduce the resistance in the source / drain region 210 to form a metal silicide film. In some embodiments, the metal silicide film may comprise a metal comprising cobalt, nickel, platinum, palladium, vanadium, titanium, tantalum, ytterbium, zirconium, or a combination thereof. Forming a metal film on a surface of the source / drain region 210 to form the metal silicide film; a step of reacting the metal film and the source / drain region 210; And removing the catalyst.

Referring to FIG. 5I, an insulating material is deposited on the resultant structure including the semiconductor fin 204 formed with the source / drain regions 210, thereby forming an interlayer insulating layer 260 having a planarized upper surface.

In some embodiments, the interlayer insulating layer 260 may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or an ULK (ultra low K) layer having an ultra low dielectric constant K of about 2.2 to 2.4, For example, a SiOC film or a SiCOH film.

Referring to FIG. 5J, the interlayer insulating layer 260 is partially etched to form a slot-shaped opening 260S that exposes the source / drain region 210 of the semiconductor fin 204.

In this example, the case where the opening 260S has a slot shape is exemplified, but the technical idea of the present invention is not limited to this. For example, the opening 260S may have a hole shape.

Referring to FIG. 5K, a conductive material is deposited on the interiors 260S and the interlayer insulating layer 260 shown in FIG. 5J to form a conductive layer, and then the conductive layer 260 is formed using a chemical mechanical polishing (CMP) A portion of the layer is removed until the top surface of the interlayer insulating layer 260 is exposed to form a contact plug 270 in contact with the source / drain region 210 in the opening 260S.

6 is a perspective view for explaining a main configuration of a semiconductor device 200B according to embodiments of the present invention.

The semiconductor device 200B has substantially the same configuration as the semiconductor device 200A exemplified in Figs. 3A to 3C except that it includes two semiconductor fins 204. Fig. Although two semiconductor pins 204 are illustrated in FIG. 6, they may include three or more semiconductor pins 204 as desired in the design.

7A and 7B are diagrams for explaining a main configuration of a semiconductor device 300A according to embodiments of the present invention. FIG. 7A is a partial perspective view of a semiconductor device 300A, FIG. 7B-7B 'of Fig. 7A. 7A and 7B illustrate a semiconductor device 300A comprising a finFET fabricated from a bulk substrate.

The semiconductor element 300A includes a semiconductor layer 304 extending in one direction (X direction in FIGS. 7A and 7B). The semiconductor layer 304 includes an active region 304X formed of a semiconductor fin protruding from the substrate 302 and extending in a first direction. In this example, only one semiconductor layer 304 is formed, but the technical idea of the present invention is not limited thereto. A case where a plurality of semiconductor layers 304 are formed on the substrate 302 is also included in the technical idea of the present invention.

The semiconductor layer 304 further includes an epitaxial semiconductor layer 304EP covering an upper surface and a part of both sidewalls of the active region 304X.

In some embodiments, the substrate 302 may comprise a semiconductor such as Si, Ge. In some other embodiments, the substrate 302 may comprise a compound semiconductor such as Ge, SiGe, SiC, GaAs, InAs, or InP. In some embodiments, the substrate 302 may include a conductive region, for example, a well doped with an impurity, or a structure doped with an impurity.

The active region 304X extends in one direction (X direction in FIGS. 7A and 7B). A device isolation film 306 is formed on the substrate 302 around the active region 304X. The active region 304X protrudes above the isolation layer 306 in a pin shape.

The semiconductor fin 304 includes a pair of source / drain regions 310 and a channel region 312 extending between the pair of source / drain regions 310.

A gate 320 extends over the isolation 302 on the substrate 302. The gate 320 extends in a direction (Y direction in FIGS. 7A and 7B) intersecting the active region 304X while covering the top and both sides of the active region 304X. The gate 320 constitutes a MOS transistor TR2. The MOS transistor TR2 includes a MOS transistor of a three-dimensional structure in which a channel is formed on the upper surface and both sides of the active region 304X.

The gate 320 has a side wall 320S extending from the element isolation film 306 in a vertical direction (Z direction in FIG. 7A) to a predetermined height HCG.

In some embodiments, the gate 320 may be comprised of doped polysilicon, a metal, a conductive metal nitride, a metal suicide, an alloy, or a combination thereof. For example, the gate 320 may include at least one metal selected from Al, Ti, Ta, W, Ru, Nb, Mo, or Hf, or a nitride thereof.

The top surface of the gate 320 is covered by an insulating capping layer 322. In some embodiments, the insulating capping layer 322 may be a silicon nitride film, a silicon oxide film, or a combination thereof.

A gate dielectric layer 324 is interposed between the channel region 312 and the gate 320. The gate dielectric layer 324 may be a silicon oxide layer or a high-k dielectric layer having a dielectric constant higher than that of the silicon oxide layer.

Corner insulating spacers 330 are formed on both sides of the gate 320 to extend along the upper surfaces of the side walls 320S and the isolation layers 306 of the gate 320. [

The corner insulating spacer 330 is formed on the gate 320 at a concave corner portion C3 (see FIGS. 8C and 8D) formed between the gate 320, the active region 304X, 320 along the side wall 320S.

The corner insulating spacer 330 includes a first surface 332 that covers at least a portion of the gate 320 sidewall 320S from one side of the gate dielectric layer 324 adjacent the sidewall 320S of the gate 320, And a second surface 334 (see FIG. 8D) covering a portion of the active region 304X. The first surface 332 of the corner insulating spacer 330 may directly contact at least a portion of the sidewall 320S of the gate 320. [ The second surface 334 may be in direct contact with a portion of the active region 304X.

The first surface 332 of the corner insulating spacer 330 covers the sidewall 320S of the gate 320 to a first height HCl less than the height HCG of the sidewall 320S. However, the technical idea of the present invention is not limited thereto. The first surface 332 of the corner insulating spacer 330 may cover the sidewall 320S at various heights within a range not exceeding the height HCG of the sidewall 320S of the gate 320 .

An outer insulating spacer 340 is formed on the corner insulating spacer 330. The outer insulating spacer 340 may extend over the isolation layer 306 to a second height HC2 that is greater than the first height HCl. 7A and 7B illustrate that the second height HC2 of the outer insulating spacer 340 is higher than the upper surface of the gate 320 and lower than the upper surface of the insulating capping layer 322. However, The technical idea is not limited to this. For example, the second height HC2 of the outer insulating spacer 340 may be less than or equal to the height H1 of the corner insulating spacer 330 and the height of the top surface of the insulating capping layer 322 And can be selected accordingly.

The outer insulating spacers 340 may cover the remaining portions of the sidewalls 320 S of the gate 320 that are not covered by the corner insulating spacers 330. The outer insulating spacer 340 may have a surface that is in direct contact with the remaining portion of the sidewalls 320S of the gate 320 that is not covered by the corner insulating spacer 330. In some embodiments, when the sidewall 320S of the gate 320 is completely covered by the corner insulating spacer 330, the outer insulating spacer 340 is formed above the corner insulating spacer 330, 322, respectively.

The outer insulating spacer 340 has a dielectric constant that is smaller than the dielectric constant of the corner insulating spacer 330.

For details of the corner insulating spacer 330 and the outer insulating spacer 340, refer to FIG. 1 and described with respect to the corner insulating spacer 130 and the outer insulating spacer 140.

The corner insulating spacers 330 are spaced apart from the horizontal spacing L3 (see FIG. 7B) from the side wall 320S of the gate 320 to the outer wall of the outer insulating spacer 340 along the side wall of the active area 304X And a small width CW3 (see Fig. 7A). The corner insulating spacer 330 covers the element isolation film 306 by the width CW3 within a distance corresponding to the horizontal spacing distance L3 from the side wall 320S of the gate 320. [

In some embodiments, the width CW3 in the horizontal direction of the corner insulating spacer 330 is within a range from the side wall 320S of the gate 320 to a distance of 1/2 of the horizontal spacing L3 Can be selected.

Although the source / drain region 310 is illustrated in FIG. 7B as extending to the bottom of the epitaxial semiconductor layer 304EP and below and the outer insulating spacer 330, the technical idea of the present invention is limited to the illustrated example It is not.

The active region 304X, the gate 320, the element isolation film 306, and the active region 304X of the insulating spacer region extending along the side wall 320S of the gate 320 in the semiconductor device 300A illustrated in Figs. 7A and 7B, A corner insulating spacer 330 made of an insulating material having a relatively high dielectric constant is disposed inside the concave corner portion C3 formed between the corner portions. Therefore, it is possible to suppress the occurrence of fringing capacitance in the semiconductor element 300A and to improve the "on" current characteristic and the "off" current characteristic of the transistor and to prevent the performance of the transistor from deteriorating can do. In addition, an outer insulating spacer 340 made of an insulating material having a dielectric constant smaller than that of the corner insulating spacer 330 is formed on an outer side portion of the insulating spacer region formed in the concave corner portion C3. Therefore, the parasitic capacitance in the semiconductor device 300A can be reduced, thereby improving the operation speed of the transistor and reducing power consumption.

8A to 8G are cross-sectional views illustrating a method of fabricating a semiconductor device according to embodiments of the present invention. In this example, the process of manufacturing the semiconductor device 300A illustrated in FIGS. 7A and 7B will be described as an example. In FIGS. 8A to 8G, the same reference numerals as in FIGS. 7A and 7B denote the same members, and a detailed description thereof will be omitted here.

8A, a device isolation trench 303 is formed on a substrate 302 to form a plurality of pin-shaped protruding portions upward from the substrate 302 and extending in one direction (for example, the Z direction in FIG. 8A) Thereby forming the active region 304X. The plurality of pinned active regions 304X may include P-type or N-type impurity diffusion regions.

Thereafter, an insulating film covering the plurality of active regions 304X is formed while filling the plurality of element isolation trenches 303, and then the insulating film is removed from the plurality of element isolation trenches 303, The insulating film is etched back to form a plurality of element isolation films 306 filling a part of the plurality of element isolation trenches 303. [ As a result, the plurality of active regions 304X protrude above the plurality of device isolation films 306 and are exposed outside the device isolation film 306. [

The plurality of device isolation films 306 may be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof. The plurality of element isolation films 306 may include an insulating liner (not shown) made of a thermal oxide film and a buried insulating film (not shown) for burying the lower portion of the trench 303 on the insulating liner.

8B, a dielectric layer 324L covering the isolation layer 306 and the active region 304X is formed on the substrate 302 and a conductive layer 320L having a top surface planarized on the dielectric layer 324L is formed. .

Details of the dielectric layer 324L and the conductive layer 320L are as described for the dielectric layer 224L and the conductive layer 220L with reference to FIG. 5B.

Thereafter, an insulating capping layer 322 is formed on the conductive layer 320L using a photolithography process. The insulating capping layer 322 is formed to cover a region where the gate 320 (see FIG. 8C) is to be formed in the upper surface of the conductive layer 320L.

8C, the conductive layer 320L and the dielectric layer 324L illustrated in FIG. 8B are sequentially etched using the insulating capping layer 322 as an etch mask to form the gate 320 and the gate dielectric layer 324 .

The gate 320 extends in a direction (Y direction in FIG. 8C) intersecting the extending direction of the active region 304X. In some embodiments, the gate 320 may be formed to have a line width (WL3) of about 10-30 nm, but is not limited thereto.

Corner portions C3 are provided on both sides of the gate 320 between the sidewall of the gate 320, the active region 304X, and the isolation film 306. And the gate dielectric film 324 is exposed at the concave corner portion C3.

Referring to FIG. 8D, a corner insulating spacer 330 is formed in the concave corner portion C3 to cover a part of the side wall 320S of the gate 320, in a manner similar to that described with reference to FIG. 5E.

The corner insulating spacer 330 may be selected to have a width CW3 selected within a range of about 1 to 20 nm and a height CH3 selected within a range of about 3 to 60 nm, It is not. The height CH3 of the corner insulating spacer 330 may correspond to the first height H1 illustrated in FIG. 7A.

Referring to FIG. 8E, an outer insulating spacer 340 is formed at the concave corner portion C3 to cover the corner insulating spacer 330, in a manner similar to that described with reference to FIG. 5F.

The outer insulating spacer 340 is made of a material having a dielectric constant smaller than that of the corner insulating spacer 330.

The width OW3 of the outer insulating spacer 340 is greater than the width CW3 of the corner insulating spacer 330 and the height OH3 of the outer insulating spacer 340 is greater than the height of the corner insulating spacer 330 (CH3). The height OH3 of the outer insulating spacer 340 may correspond to the second height HC2 illustrated in FIG. 7A.

8F, an epitaxial semiconductor layer 304EP is formed on the exposed surface of the active region 304X illustrated in FIG. 8E to form a semiconductor pin 304P composed of the active region 304X and the epitaxial semiconductor layer 304EP 304 are formed.

The details of the epitaxial semiconductor layer 304EP and the method of forming the epitaxial semiconductor layer 304EP are substantially the same as those described for the epitaxial semiconductor layer 310EP with reference to FIG. 5G.

The semiconductor fin 304 may include an epitaxial semiconductor layer 304EP so that the source / drain regions formed in the semiconductor fin 304 may have a raised source / drain (RSD) structure.

8G, impurity ions IIP3 are injected into the semiconductor fin 304 by using the insulating capping layer 322 and the outer insulating spacer 340 as an ion implantation mask, Source / drain regions 310 are formed in the fin 304. [

Although not shown, in order to reduce the resistance in the source / drain region 310, a salicide process is performed on the surface of the source / drain region 310 to form a metal silicide film .

The corner insulating spacers 330, the outer insulating spacers 340, and the pair of source / drain regions 310 are then etched using processes similar to those described with reference to Figures 5i-5k The resultant product can be covered with an interlayer insulating film and a normal contact forming process can be performed.

9 is a perspective view for explaining a main configuration of a semiconductor device 300B according to embodiments of the present invention.

The semiconductor device 300B has substantially the same configuration as that of the semiconductor device 300A illustrated in Figs. 7A and 7B except that the semiconductor device 300B includes two semiconductor fins 304. Fig. Although two semiconductor pins 304 are illustrated in FIG. 9, they may include three or more semiconductor pins 304 as required in the design.

10 is a plan view of the memory module 400 according to the technical idea of the present invention.

The memory module 400 includes a module substrate 410 and a plurality of semiconductor chips 420 attached to the module substrate 410.

The semiconductor chip 420 includes a semiconductor device according to the technical idea of the present invention. The semiconductor chip 420 includes at least one semiconductor element of the semiconductor devices 100A, 100B, 200A, 200B, 300A, and 300B illustrated in FIGS.

At one side of the module substrate 410, a connection part 430 that can be inserted into the socket of the mother board is disposed. A ceramic decoupling capacitor 440 is disposed on the module substrate 410. The memory module 400 according to the technical idea of the present invention is not limited to the configuration illustrated in FIG. 10 but may be manufactured in various forms.

FIG. 11 is a schematic block diagram of a display driver IC (DDI) 500 according to embodiments of the present invention and a display device 520 having the DDI 500.

11, the DDI 500 includes a controller 502, a power supply circuit 504, a driver block 506, and a memory block 508 ). The control unit 502 receives and decodes a command applied from a main processing unit (MPU) 522, and controls each block of the DDI 500 to implement an operation according to the command. The power supply circuit portion 504 generates a drive voltage in response to the control of the control portion 502. [ The driver block 506 drives the display panel 524 using the driving voltage generated by the power supply circuit portion 504 in response to the control of the controller 502. [ The display panel 524 may be a liquid crystal display panel (PDP) or a plasma display panel (PDP). The memory block 508 may include a memory such as a RAM and a ROM for temporarily storing a command input to the controller 502 or control signals output from the controller 502 or storing necessary data. At least one of the power supply circuit portion 504 and the driver block 506 includes at least one semiconductor element of the semiconductor elements 100A, 100B, 200A, 200B, 300A, and 300B illustrated in Figs.

12 is a circuit diagram of a CMOS inverter 600 according to embodiments of the present invention.

The CMOS inverter 600 includes a CMOS transistor 610. The CMOS transistor 610 includes a PMOS transistor 620 and an NMOS transistor 630 connected between a power supply terminal Vdd and a ground terminal. The CMOS transistor 610 includes at least one semiconductor element of the semiconductor devices 100A, 100B, 200A, 200B, 300A, and 300B illustrated in FIGS.

13 is a circuit diagram of a CMOS SRAM device 700 according to embodiments of the present invention.

The CMOS SRAM device 700 includes a pair of driving transistors 710. The pair of driving transistors 710 includes a PMOS transistor 720 and an NMOS transistor 730 connected between a power supply terminal Vdd and a ground terminal. The CMOS SRAM device 700 further includes a pair of transfer transistors 740. The source of the transfer transistor 740 is cross-connected to a common node of the PMOS transistor 720 and the NMOS transistor 730 constituting the driving transistor 710. A power supply terminal Vdd is connected to a source of the PMOS transistor 720 and a ground terminal is connected to a source of the NMOS transistor 730. A word line WL is connected to the gate of the pair of transfer transistors 740 and a bit line BL and an inverted bit line are connected to drains of the pair of transfer transistors 740, respectively.

At least one of the driving transistor 710 and the transfer transistor 740 of the CMOS SRAM device 700 may include at least one of the semiconductor devices 100A, 100B, 200A, 200B, 300A, and 300B illustrated in FIGS. Semiconductor devices.

14 is a circuit diagram of a CMOS NAND circuit 800 according to embodiments of the present invention.

The CMOS NAND circuit 800 includes a pair of CMOS transistors to which different input signals are transmitted. The CMOS NAND circuit 800 includes at least one semiconductor device of the semiconductor devices 100A, 100B, 200A, 200B, 300A, and 300B illustrated in FIGS.

15 is a block diagram illustrating an electronic system 900 according to embodiments of the present invention.

The electronic system 900 includes a memory 910 and a memory controller 920. The memory controller 920 controls the memory 910 in response to a request from the host 930 for reading data from the memory 910 and / or writing data to the memory 910. At least one of the memory 910 and the memory controller 920 includes at least one semiconductor device of the semiconductor devices 100A, 100B, 200A, 200B, 300A, and 300B illustrated in FIGS.

16 is a block diagram of an electronic system 1000 according to embodiments of the present invention.

The electronic system 1000 includes a controller 1010, an input / output device (I / O) 1020, a memory 1030, and an interface 1040, which are interconnected via a bus 1050, respectively.

The controller 1010 may include at least one of a microprocessor, a digital signal processor, or similar processing devices. The input / output device 1020 may include at least one of a keypad, a keyboard, and a display. The memory 1030 may be used to store instructions executed by the controller 1010. [ For example, the memory 1030 may be used to store user data.

The electronic system 1000 may comprise a wireless communication device, or a device capable of transmitting and / or receiving information under a wireless environment. The interface 1040 may be configured as a wireless interface for transmitting / receiving data over the wireless communication network in the electronic system 1000. The interface 1040 may include an antenna and / or a wireless transceiver. In some embodiments, the electronic system 1000 is a third generation communication system, e.g., code division multiple access (CDMA), global system for mobile communications (GSM), north American digital cellular (NADC) extended-time division multiple access (WCDMA), and / or wideband code division multiple access (WCDMA). The electronic system 1000 includes at least one semiconductor device of the semiconductor devices 100A, 100B, 200A, 200B, 300A, and 300B illustrated in FIGS.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, This is possible.

A semiconductor device comprising: a semiconductor substrate; 106 active region; 110 source / drain region; 112 channel region; 120 gate; 120S side wall; 122 insulative capping layer; 124 gate dielectric; An insulating spacer 202 a substrate 204 semiconductor pin 206 buried insulating layer 208 SOI wafer 210 source / drain region 212 channel region 220 gate 220S side wall 222 insulating capping layer 224 A gate insulating film, a corner insulating spacer, an outer insulating spacer, a substrate, a semiconductor layer, a semiconductor isolation layer, a source / drain region, a channel region, 322: insulating capping layer, 324: gate dielectric film, 330: corner insulating spacer, 340: outer insulating spacer.

Claims (10)

A semiconductor layer having a pair of source / drain regions and a channel region extending between the pair of source / drain regions and extending in a first direction;
A gate extending in a second direction on the semiconductor layer to cover the channel region;
A gate dielectric film interposed between the channel region and the gate,
A corner insulating spacer extending in a second direction along a sidewall of the gate and having a first surface covering at least a portion of a sidewall of the gate from one side of the gate dielectric and a second surface covering a portion of the semiconductor layer,
And an outer insulating spacer covering the sidewall of the gate over the corner insulating spacer and having a dielectric constant that is less than a dielectric constant of the corner insulating spacer. The method according to claim 1,
The sidewall of the gate having a first height,
Wherein the first surface of the corner insulating spacer covers a sidewall of the gate to a second height less than the first height. The method according to claim 1,
Wherein the semiconductor layer is part of a bulk semiconductor substrate,
Wherein the corner insulating spacer extends along a sidewall of the gate at a reentrant corner portion formed between the gate and the pair of source / drain regions. The method according to claim 1,
And a semiconductor substrate disposed under the gate,
Wherein the semiconductor layer comprises a semiconductor fin protruding from the semiconductor substrate and extending in a first direction. 5. The method of claim 4,
Further comprising an element isolation film on the semiconductor substrate, the element isolation film being in contact with both side walls of the semiconductor fin and having a top surface lower in level than the top surface of the semiconductor fin,
Wherein the gate extends in the second direction on the semiconductor fin and the device isolation film,
Wherein the corner insulating spacer extends along the side wall of the gate from the semiconductor fin at a concave corner portion formed between the gate and the semiconductor fin and the device isolation film. The method according to claim 1,
A substrate disposed under the gate;
Further comprising a buried insulating layer interposed between the substrate and the gate,
Wherein the semiconductor layer includes a semiconductor fin extending in the first direction on the buried insulating layer and having a base portion in contact with the buried insulating layer. The method according to claim 6,
The gate extending in the second direction over the semiconductor fin and the buried insulating layer,
Wherein the corner insulating spacer extends along the side wall of the gate from the semiconductor fin at a concave corner portion formed between the gate, the semiconductor fin, and the buried insulating layer. The method according to claim 1,
Wherein the pair of source / drain regions comprises a source / drain extension region having a first doping concentration and a deep source / drain region having a second doping concentration higher than the first doping concentration,
Wherein the corner insulating spacer covers the source / drain extension region by a width less than the horizontal spacing distance between the gate and the deep source / drain region from the sidewall of the gate. A semiconductor layer having a channel region and extending in a first direction;
An insulating layer covering at least a part of the semiconductor layer,
A gate extending in a second direction intersecting the semiconductor layer on the channel region and the insulating layer;
A gate dielectric film interposed between the channel region and the gate,
A corner insulating spacer extending from the semiconductor layer along a sidewall of the gate and having a first surface covering at least a portion of a sidewall of the gate and a second surface covering a portion of the semiconductor layer,
And an outer insulating spacer covering the sidewall of the gate over the corner insulating spacer and having a dielectric constant that is less than a dielectric constant of the corner insulating spacer. 10. The method of claim 9,
Wherein the corner insulating spacer has a width smaller than a horizontal spacing distance from the side wall of the gate to the outer wall of the outer insulating spacer along the first direction.

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