KR20150015760A - Template for light emitting device fabricating and method of fabricating ultraviolet light emitting device - Google Patents

Abstract

A template for manufacturing a light emitting device and a method of manufacturing a light emitting device using the template are disclosed. Wherein the template for manufacturing the light emitting element comprises a growth substrate, a GaN layer positioned on the growth substrate, an AlN layer located on the GaN layer, an n-type Al _x Ga _(1-x) N ( claim 1 n-type containing 0 <x <1) semiconductor layer, and disposed on the first 1 n-type semiconductor layer, _{and, Al y a (1-y} ) N layer (0 <y <1) / Al z a _{And a} second superlattice layer including a _(1-z) N layer (0 &lt; z &lt; 1). Thus, crystallinity of the semiconductor layers formed on the template can be improved.

Description

TECHNICAL FIELD [0001] The present invention relates to a template for manufacturing a light emitting device, and a method of manufacturing the same. BACKGROUND OF THE INVENTION [0002]

The present invention relates to a template for manufacturing a light emitting device and a method of manufacturing an ultraviolet light emitting device, and more particularly, to a template for manufacturing a light emitting device and a method of manufacturing an ultraviolet light emitting device that can form a super lattice layer to form a high quality semiconductor layer.

BACKGROUND ART Light emitting devices are inorganic semiconductor devices that emit light generated by recombination of electrons and holes, and are used in various fields such as displays, automobile lamps, general lighting, and optical communication devices. In particular, ultraviolet light emitting devices can be used as UV curing, sterilization, white light sources, medical fields, and equipment accessories, and the use range thereof is increasing.

Since an ultraviolet light emitting device emits light having a relatively short peak wavelength (generally, a peak wavelength of 400 nm or less), AlGaN having an Al content of 10% or more is used when an ultraviolet light emitting device is manufactured using a nitride semiconductor. In such an ultraviolet light emitting element, when the band gap energy of the n-type and p-type nitride semiconductor layers is smaller than the energy of the ultraviolet light emitted from the active layer, ultraviolet light emitted from the active layer is injected into the n-type and p- Can be absorbed. In this case, the luminous efficiency of the light emitting element is significantly reduced. Therefore, not only the active layer of the ultraviolet light-emitting element but also other semiconductor layers located in the light-emitting direction of the light-emitting element have an Al content of 10% or more.

In manufacturing an ultraviolet light-emitting device, a sapphire substrate is generally used as a growth substrate. However, when an Al _x Ga _(1-x) N (0.1 ≦ x ≦ 1) layer is grown on a sapphire substrate, cracks or braking occur due to thermal and structural deformation due to high Al content. This is due to the difference in lattice mismatch and / or thermal expansion coefficient between the sapphire substrate and the Al _x Ga _(1-x) N (0.1 x 1) layer. To the prior art, to minimize the generation is such a problem, form the high-temperature grown AlN layer on the sapphire substrate, or after the formation of the AlN / AlGaN superlattice layer _{Al x Ga (1-x)} N (0.2 ≤ x ≤ 1), an active layer, and a p-type semiconductor layer were formed to fabricate a light emitting device.

However, in the case of an ultraviolet light emitting device including an AlN layer grown on a sapphire substrate, it is difficult to separate the growth substrate from the semiconductor layers. In general, when a sapphire substrate is used as a growth substrate, the growth substrate is separated from the semiconductor layers using a laser lift-off. However, the wavelengths of the excimer lasers mainly used in the laser lift-off technique are longer wavelengths or substantially similar wavelengths than the band gap energy of AlN. For example, a KrF excimer laser has a wavelength of 248 nm and is transmitted through an AlN layer, which is difficult to use. The ArF excimer laser has a wavelength of 193 nm which can be absorbed by the AlN layer but is not so different from the wavelength (about 200 nm) corresponding to the band gap energy of AlN, so that a part of the laser is formed in the AlN layer or the AlN / AlGaN superlattice layer , And the pulse energy of the ArF excimer laser is low and does not provide sufficient energy to separate the substrate.

For this reason, the conventional ultraviolet light emitting device is manufactured as a horizontal type light emitting device or a flip chip type light emitting device including a growth substrate. In the horizontal type or flip chip type light emitting device, a part of the active layer is removed and is also vulnerable to heat emission, and the efficiency of the light emitting device is low.

Further, it is difficult to grow a film having a relatively good crystallinity as compared with GaN in Al _x Ga _(1-x) N (0.1 x 1), and the internal quantum efficiency of the produced light emitting device is low. It is generally known that crystallinity is improved when Al _x Ga _(1-x) N (0.1? X? 1) is grown at a high temperature of 1200 占 폚 or higher using MOCVD (Metal Organic Chemical Vapor Deposition). However, when the MOCVD equipment is used at a high temperature of 1200 ° C or more, the lifetime of the equipment can be shortened, and it is difficult to stably grow Al _x Ga _1-x N (0.1 ≦ x ≦ 1). Accordingly, it has been difficult to mass-produce ultraviolet light-emitting devices having high crystallinity and high internal quantum efficiency using conventional MOCVD equipment.

A problem to be solved by the present invention is to provide a template for manufacturing an ultraviolet light emitting device.

A further object of the present invention is to provide an ultraviolet light emitting device having excellent semiconductor properties without damage and a method of manufacturing the same.

A template for manufacturing a light emitting device according to an embodiment of the present invention includes a growth substrate; A GaN layer located on the growth substrate; An AlN layer located on the GaN layer; A first n-type semiconductor layer located on the AlN layer and including n-type Al _x Ga _(1-x) N (0 <x <1); And an Al _y a _(1-y) N layer (0 <y <1) / Al _z a _(1-z) N layer (0 <z <1) located on the first n-type semiconductor layer The second superlattice layer.

The template may further comprise a first superlattice layer positioned between the AlN layer and the first n-type semiconductor layer, wherein the first superlattice layer is formed between the AlN layer grown at the first pressure and the second superlattice layer at the second pressure Layer structure of the grown AlN layer, and the first pressure and the second pressure may be different from each other.

The template may further include a GaN buffer layer positioned between the growth substrate and the GaN layer.

X <y, and x <z.

The growth substrate may include a sapphire substrate.

According to another embodiment of the present invention, there is provided a method of manufacturing an ultraviolet light emitting device, comprising: forming a GaN layer on a growth substrate; Forming an AlN layer on the GaN layer at a first temperature; Forming a first n-type semiconductor layer containing n-type Al _x Ga _(1-x) N (0 <x <1) on the AlN layer; Forming a second superlattice layer on the first n-type semiconductor layer; Forming a second n-type semiconductor layer including AlGaN on the second superlattice layer; Forming an active layer and a p-type semiconductor layer including a nitride semiconductor on the second n-type semiconductor layer; Above, but from the GaN layer includes separating the growth substrate, the second cho forming the lattice layer, the third and pressure _{Al y a (1-y)} N layer (0 <y <1) is grown in the (0 &lt; z &lt; 1) layers alternately laminated on the Al _z a _(1-z) N layer grown at a pressure of 4 atm. The third pressure and the fourth pressure may be different from each other.

The third pressure may be lower than the fourth pressure.

The third pressure may be greater than 0 and less than 100 Torr, and the fourth pressure may be greater than 0 and less than 300 Torr.

The manufacturing method may further include forming a first superlattice layer on the AlN layer at a second temperature before forming the first n-type semiconductor layer.

Forming the first superlattice layer may include alternately repeating layers of an AlN layer grown at a first pressure and an AlN layer grown at a second pressure, the first pressure and the second pressure being can be different.

The first pressure may be less than the second pressure, the first pressure may be greater than 0 and less than 100 Torr, and the second pressure may be greater than 0 and less than 400 Torr.

The second temperature may be a temperature higher than the first temperature.

The manufacturing method may further include bonding the supporting substrate on the p-type semiconductor layer before separating the growth substrate.

The manufacturing method may further include removing the GaN layer, the AlN layer, the first n-type semiconductor layer, and the second superlattice layer after the growth substrate is separated to expose one surface of the second n-type semiconductor layer .

Further, forming the first electrode on the exposed surface of the second n-type semiconductor layer may further include forming the first electrode on the exposed surface of the second n-type semiconductor layer.

Meanwhile, the manufacturing method may include removing the p-type semiconductor layer and the active layer to partially expose the second n-type semiconductor layer, and forming a first electrode on the exposed surface of the second n-type semiconductor layer, And forming a second electrode on the p-type semiconductor layer.

In other embodiments, it may further comprise forming a GaN buffer layer on the growth substrate prior to forming the GaN layer.

Further, the growth substrate may be a sapphire substrate, and separating the growth substrate may include using a laser lift-off.

According to the present invention, by providing the template for manufacturing a light emitting device including the second superlattice layer, the crystallinity of the semiconductor layers grown on the template can be improved and the applied stress can be minimized.

Further, by providing a method of manufacturing an ultraviolet light-emitting device using the template, it is possible to provide an ultraviolet light-emitting device having improved light efficiency and reliability.

1 to 4 are cross-sectional views illustrating a template for fabricating a light emitting device according to an embodiment of the present invention and a method of manufacturing the same.
5 to 11 are cross-sectional views illustrating a method of manufacturing an ultraviolet light-emitting device according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so that those skilled in the art can sufficiently convey the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the width, length, thickness, etc. of components may be exaggerated for convenience. It is also to be understood that when an element is referred to as being "above" or "above" another element, But also includes the case where there are other components in between. Like reference numerals designate like elements throughout the specification.

The respective composition ratios, growth methods, growth conditions, thicknesses, etc. for the semiconductor layers described below are examples, and the present invention is not limited thereto. For example, in the case of being denoted by AlGaN, the composition ratio of Al and Ga can be variously applied according to the needs of ordinary artisans. In addition, the semiconductor layers described below can be grown using a variety of methods commonly known to those of ordinary skill in the art (such as MOCVD (Metal Organic Chemical Vapor Deposition), MBE (Molecular Beam Epitaxy), or HVPE (Hydride Vapor Phase Epitaxy). However, in the embodiments described below, it is described that the semiconductor layers are grown in the same chamber using MOCVD, and the source gases introduced into the chamber can use a source known to a common technician according to the composition ratio, But is not limited to.

1 to 4 are cross-sectional views illustrating a template for fabricating a light emitting device according to an embodiment of the present invention and a method of manufacturing the same.

Referring to FIG. 1, a GaN layer 130 and an AlN layer 140 are formed on a growth substrate 110. Further, the GaN buffer layer 120 may be further formed on the growth substrate 110 before the GaN 130 is formed.

The growth substrate 110 is not limited as long as it is a substrate for growing a nitride semiconductor layer. For example, the growth substrate 110 may be a sapphire substrate, a silicon carbide substrate, a spinel substrate, or a nitride substrate such as a GaN substrate or an AlN substrate. In particular, in this embodiment, the growth substrate 110 may be a sapphire substrate.

The GaN layer 130 may be grown to a thickness of about 1 mu m on the growth substrate 110 and grown at a temperature of about 900 to about 1100 DEG C and a pressure of about 200 Torr. Since the template for fabricating the light emitting element includes the GaN layer 130, a laser lift-off can be used in the growth substrate 110 separation process, which will be described later.

The AlN layer 140 may be grown to a thickness of about 20 nm on the GaN layer 130 and grown at a pressure of about 200 Torr and a first temperature. The first temperature may be, for example, 650 to 750 占 폚. The AlN layer 140 may allow the semiconductor layers including AlGaN grown on the AlN layer 140 to grow easily.

On the other hand, the GaN buffer layer 120 may be grown to a thickness of about 25 nm on the growth substrate 110 before the growth of the GaN layer 130, and may be grown at a temperature of about 600 ° C and a pressure of 600 Torr. In particular, when the growth substrate 110 is a sapphire substrate, the GaN buffer layer 120 can serve as a nucleus layer for other semiconductor layers to grow, and can also mitigate the difference in lattice constant.

Referring to FIGS. 2 and 3, a first n-type semiconductor layer 160 is formed on the AlN layer 140. Also, a first superlattice layer 150 may be further formed on the AlN layer 140 before the first n-type semiconductor layer 160 is formed.

Forming the first superlattice layer 150 may be performed by alternating the AlN layer grown at the first pressure and the AlN layer grown at the second pressure, for example, at a temperature of about 900 to about 1100 &lt;Lt; / RTI &gt; The repeatedly stacked AlN layers may each have a thickness of about 5 nm, whereby a superlattice layer may be formed. At this time, the first pressure may be different from the second pressure, and the first pressure may be a pressure lower than the second pressure. For example, the first pressure may be greater than 0 and less than 100 Torr, and the second pressure may be greater than 0 and less than 400 Torr.

The AlN layer grown at the first pressure of the first superlattice layer 150 and the AlN layer grown at the second pressure may have different growth rates due to the difference in pressure. Accordingly, the dislocation can be prevented from being propagated, or the propagation path can be changed, so that the dislocation density of other semiconductor layers grown in the subsequent process can be reduced. In addition, since the first superlattice layer 150 is grown at a second temperature higher than the first temperature, the first superlattice layer 150 can have a higher crystallinity than the AlN layer 140. Thus, the crystallinity of the other semiconductor layers grown in the subsequent process can be improved.

The first n-type semiconductor layer 160 may include an Al _x Ga _(1-x) N layer (0 <x <1) and may be doped with n-type impurities including Si. The first n-type semiconductor layer 160 can be grown to have a thickness of about 1 mu m at a temperature of about 900 to 1100 DEG C and a pressure of 100 Torr.

Next, referring to FIG. 4, a second superlattice layer 170 is formed on the first n-type semiconductor layer 160.

Second cho forming the grid layer 170, the 3 Al _y is grown at a pressure of Ga _(1-y) N layer (0 <y <1) and Al _z Ga _(1-z is grown at a fourth pressure ₎ N layers (0 &lt; z &lt; 1). _{Al y Ga (1-y)} N layer (0 <y <1) and _{Al z Ga (1-z)} N layer (0 <z <1) that the repeated lamination are each approximately at a temperature of about 900 to 1100 ℃ 5 nm and about 10 nm thick. Accordingly, a superlattice layer including an Al _y Ga _(1-y) N layer (0 <y <1) and an Al _z Ga _(1-z) N layer (0 <z <1) can be formed.

The third pressure and the fourth pressure may be different pressures, and the third pressure may be lower than the fourth pressure. For example, the third pressure may be greater than 0 and less than 100 Torr, and the fourth pressure may be greater than 0 and less than 300 Torr. The composition ratio of the Al _y Ga _(1-y) N layer (0 <y <1) and the Al _z Ga _(1-z) N layer (0 <z <1) It may be the same. For example, if the growth conditions other than pressure are the same, the AlGaN layer grown at lower pressure may have a higher Al composition ratio than the AlGaN layer grown at higher pressure. Therefore, the source inflow amounts of the Al _y Ga _(1-y) N layer (0 <y <1) and the Al _z Ga _(1-z) N layer (0 <z <1) can be adjusted to have the same composition ratio . On the other hand, when the source inflow amounts of the Al _y Ga _(1-y) N layer (0 <y <1) and the Al _z Ga _(1-z) N layer (0 <z <1) are made constant, which can form an _{Al y Ga (1-y)} N layer (0 <y <1) and _{Al z Ga (1-z)} N layer (0 <z <1).

The Al _y Ga _(1-y) N layer (0 <y <1) and the Al _z Ga _(1-z) N layer (0 <z <1) may have different growth rates due to the difference in growth pressure. Thus, the dislocation can be prevented from propagating or the propagation path can be changed, so that the dislocation density of the other semiconductor layers grown in the subsequent process can be reduced. Further, when the composition ratios of the Al _y Ga _(1-y) N layer (0 <y <1) and the Al _z Ga _(1-z) N layer (0 <z <1) are made different from each other, The stress can be relaxed, so that the crystallinity of the other semiconductor layers to be grown in the succeeding process can be improved, and damage such as cracks can be prevented from occurring.

On the other hand, the Al composition ratio of the second superlattice layer 170 and the first n-type semiconductor layer 160 can be controlled to be different from each other. In addition, x <y and x <z can be the composition ratio of the respective layers are adjusted so that, for example, a 1 n-type semiconductor layer 160 may include Al _{0 .08} Ga _{0 .92} N, and the second at least one layer of super lattice layer 170 may be a layer Al _{0 .2} Ga _{0 .8} N.

According to the above-described manufacturing method, a template for manufacturing a light emitting element as shown in Fig. 4 is provided. The template for fabricating a light emitting device according to this embodiment can improve the crystallinity of the semiconductor layers formed on the template by including the above-described structures, and also relieves stress due to the difference in lattice constant, Can be prevented. Therefore, the light emitting device manufactured from the semiconductor layers grown on the template can have high internal quantum efficiency and reliability.

5 to 11 are cross-sectional views illustrating a method of manufacturing an ultraviolet light-emitting device according to another embodiment of the present invention.

Referring to FIG. 5, a second n-type semiconductor layer 181 is formed on a template for manufacturing a light emitting device as shown in FIG.

The second n-type semiconductor layer 181 may include an AlGaN layer and may be doped with an n-type impurity including an impurity such as Si. The second n-type semiconductor layer 180 may be grown to have a thickness of about 2 [mu] m at a temperature of about 900 to 1100 [deg.] C and a pressure of 100 Torr. The second n-type semiconductor layer 181 may be an n-type semiconductor layer that supplies electrons for substantially emitting light, unlike the first n-type semiconductor layer 160. Accordingly, the second n-type semiconductor layer 181 can be doped at a relatively high concentration as compared with the first n-type semiconductor layer 160. [

The second n-type semiconductor layer 181 may be a single layer or may be formed of multiple layers including a plurality of layers. Furthermore, the second n-type semiconductor layer 181 may be formed of a gradation layer continuously changing its composition ratio. For example, the second n-type semiconductor layer 181 may be formed so that the Al composition ratio is continuously changed so as to reduce the stress due to the difference in lattice constant between the second superlattice layer 170 and the active layer 183 .

Referring to FIG. 6, an active layer 183 and a p-type semiconductor layer 185 are formed on the second n-type semiconductor layer 181.

The active layer 183 may include (Al, Ga, In) N and may include multiple barrier layers (not shown) and well layers (not shown) alternately stacked to form a multiple quantum well structure (MQW) . For example, the barrier layer and the well layer may each include a four-component nitride semiconductor such as AlInGaN. At this time, the material can be controlled such that the band gap energy of the barrier layer is greater than the band gap energy of the well layer. Further, by controlling the composition ratio of the nitride semiconductor of the active layer 183, light having a peak wavelength in a desired ultraviolet region can be emitted.

In addition, the barrier layer closest to the second n-type semiconductor layer 181 of the barrier layers may have a higher Al content than other barrier layers. By forming the barrier layer closest to the second n-type semiconductor layer 181 to have a wider band gap than other barrier layers, it is possible to reduce the movement speed of the electrons, thereby effectively preventing electron overflow.

The p-type semiconductor layer 185 may be formed on the active layer 183 and may be formed to a thickness of about 0.1 mu m at a temperature of about 900 to 1000 DEG C and a pressure of about 100 Torr. The p-type semiconductor layer 185 may include a nitride semiconductor such as AlGaN, and may further include an impurity such as Mg to be doped into the p-type.

Furthermore, the p-type semiconductor layer 185 may further include a delta doping layer (not shown) for lowering ohmic contact resistance.

Referring to FIG. 7, a supporting substrate 190 is formed on the p-type semiconductor layer 185.

The support substrate 190 may be an insulating substrate, a conductive substrate, or a circuit substrate. For example, the support substrate 190 may be a sapphire substrate, a gallium nitride substrate, a glass substrate, a silicon carbide substrate, a silicon substrate, a metal substrate, or a ceramic substrate.

The supporting substrate 190 may be bonded to the p-type semiconductor layer 185 so that a bonding layer (not shown) for bonding the supporting substrate 190 and the p- Can be formed.

The bonding layer may include a metal material, for example, AuSn. The AuSn-containing bonding layer may bond the support substrate 190 and the p-type semiconductor layer 185 by eutectic bonding. When the supporting substrate 190 is a conductive substrate, the bonding layer electrically connects the p-type semiconductor layer 185 and the supporting substrate 190.

Further, a metal layer (not shown) may be further formed between the supporting substrate 190 and the p-type semiconductor layer 185.

The metal layer may include a reflective metal layer (not shown) and a barrier metal layer (not shown), and the barrier metal layer may be formed to cover the reflective metal layer.

The reflective metal layer may be formed through deposition and lift-off techniques. The reflective metal layer may serve to reflect light and may serve as an electrode electrically connected to the p-type semiconductor layer 185. Thus, the reflective metal layer preferably comprises a material capable of forming an ohmic contact with high reflectivity to ultraviolet light. The reflective metal layer may include, for example, a metal containing at least one of Ni, Pt, Pd, Rh, W, Ti, Al, Ag and Au.

Meanwhile, the barrier metal layer prevents mutual diffusion of the reflective metal layer and other materials. Thus, it is possible to prevent an increase in contact resistance and a reduction in reflectivity due to damage to the reflective metal layer. The barrier metal layer may include Ni, Cr, Ti, and may be formed of multiple layers.

Referring to FIG. 8, the growth substrate 110 is separated from the semiconductor layers. The growth substrate 110 may be separated from the GaN layer 130.

The growth substrate 110 may be separated by various methods such as laser lift off, chemical lift off, stress lift off, thermal lift off, and the like.

For example, when the growth substrate 110 is a sapphire substrate, it can be separated using a laser lift-off. According to this embodiment, since the GaN layer 130 can be formed under the AlN layer 140, the growth substrate 110 can be easily separated even by using a KrF excimer laser. Therefore, it is possible to solve the problem that it was difficult to separate the growth substrate using the laser lift-off in the conventional ultraviolet light emitting device.

However, the present invention is not limited thereto, and additional layers (for example, a sacrificial layer) may be further formed between the growth substrate 110 and the semiconductor layers, (110) can be separated.

9, after the growth substrate 110 is separated, the GaN buffer layer 120, the GaN layer 130, the AlN layer 140, the first and second superlattice layers 160 and 180, And the first n-type semiconductor layer 170 may be removed to expose one surface of the second n-type semiconductor layer 181.

The layers 120, 130, 140, 150, 160, 170 located on top of the second n-type semiconductor layer 181 may be chemically and / or thermally coupled to one side of the second n-type semiconductor layer 181, Physical methods, etching, or the like.

On the other hand, it is possible to further increase the roughness of the surface of the exposed second n-type semiconductor layer 181 to form a roughness (not shown) on the surface of the second n-type semiconductor layer 181. The roughness may be formed using wet etching or the like. For example, the roughness may be PEC (Photo-Enhanced Chemical) etching, etching using a sulfuric acid phosphoric acid solution, or the like. The size of the roughness may be variously determined depending on the etching conditions, for example, the average height may be 0.5 탆 or less. By forming the roughness, the light extraction efficiency of the ultraviolet light emitting device of the present invention can be improved.

10, the device isolation trenches 210 may be formed by patterning the first n-type semiconductor layer 181, the active layer 183, and the p-type semiconductor layer 185. By forming the element dividing grooves 210, the upper surface of the supporting substrate 190 can be partially exposed. Furthermore, the first electrode 220 can be formed on each of the device regions divided by the device dividing groove 210.

The patterning of the first n-type semiconductor layer 181, the active layer 183 and the p-type semiconductor layer 185 can be performed using a photolithography and etching process, Or may be formed to have a predetermined slope.

The first electrode 220 may serve to supply external power to the second n-type semiconductor layer 181, and may be formed using a deposition and lift-off technique.

Subsequently, the supporting substrate 190 in the area under each device dividing groove 210 is separated along S1 so that an ultraviolet light emitting element as shown in Fig. 11 can be provided.

The ultraviolet light emitting device according to this embodiment includes a first n-type semiconductor layer 181, an active layer 183, and a p-type semiconductor layer 185 formed on the template for manufacturing a light emitting element of Fig. Therefore, the first n-type semiconductor layer 181, the active layer 183 and the p-type semiconductor layer 185 have a low defect density and can have excellent crystallinity and the first n-type semiconductor layer 181, The stress applied to the p-type semiconductor layer 183 and the p-type semiconductor layer 185 is small and damage such as cracks can be prevented. Accordingly, the light emitting device can have high light efficiency and reliability.

Meanwhile, in the embodiment described with reference to the drawings, the vertical type light emitting device in which the growth substrate 110 is removed is described, but the present invention is not limited thereto. The above-described template for manufacturing a light emitting element can also be used for manufacturing a horizontal type flip chip type light emitting device. 6, the p-type semiconductor layer 185 and a part of the active layer 183 are partially removed to partially expose the second n-type semiconductor layer 181, and the p-type semiconductor layer 185 and the exposed The second electrode and the first electrode are formed on the surface of the second n-type semiconductor layer 181 so that a horizontal or flip chip type light emitting device can be manufactured.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, Variations and changes are possible.

Claims (18)

Growth substrate;
A GaN layer located on the growth substrate;
An AlN layer located on the GaN layer;
A first n-type semiconductor layer located on the AlN layer and including n-type Al _x Ga _(1-x) N (0 <x <1); And
Disposed on the first 1 n-type semiconductor layer, including the _{Al y a (1-y)} N layer (0 <y <1) / Al z a (1-z) N layer (0 <z <1) And a second super lattice layer. The method according to claim 1,
Further comprising a first superlattice layer positioned between the AlN layer and the first n-type semiconductor layer,
Wherein the first superlattice layer comprises a repeating layer structure of an AlN layer grown at a first pressure and an AlN layer grown at a second pressure, wherein the first pressure and the second pressure are different. The method according to claim 1,
And a GaN buffer layer positioned between the growth substrate and the GaN layer. The method according to claim 1,
Wherein x <y and x <z. The method according to claim 1,
Wherein the growth substrate comprises a sapphire substrate. Forming a GaN layer on the growth substrate;
Forming an AlN layer on the GaN layer at a first temperature;
Forming a first n-type semiconductor layer containing n-type Al _x Ga _(1-x) N (0 <x <1) on the AlN layer;
Forming a second superlattice layer on the first n-type semiconductor layer;
Forming a second n-type semiconductor layer including AlGaN on the second superlattice layer;
Forming an active layer and a p-type semiconductor layer including a nitride semiconductor on the second n-type semiconductor layer;
And separating the growth substrate from the GaN layer,
The second cho forming the grating _{layer, Al y a (1-y} ) is grown on the third pressure N layer (0 <y <1) and Al _z a _(1-z) is grown at a fourth pressure N Layer (0 &lt; z &lt; 1), wherein the third pressure and the fourth pressure are different from each other. The method of claim 6,
Wherein the third pressure is lower than the fourth pressure. The method of claim 7,
Wherein the third pressure is greater than 0 and less than 100 Torr, and the fourth pressure is greater than 0 and less than or equal to 300 Torr. The method of claim 6,
Before forming the first n-type semiconductor layer,
And forming a first superlattice layer on the AlN layer at a second temperature. The method of claim 9,
Forming the first superlattice layer comprises:
Wherein the first pressure and the second pressure are different from each other, wherein the first pressure and the second pressure are alternately repeatedly laminated by alternately repeating lamination of the AlN layer grown at the first pressure and the AlN layer grown at the second pressure. The method of claim 10,
Wherein the first pressure is lower than the second pressure,
Wherein the first pressure is greater than 0 and less than 100 Torr, and the second pressure is greater than 0 and less than 400 Torr. The method of claim 9,
Wherein the second temperature is higher than the first temperature. The method of claim 6,
Before separating the growth substrate,
And bonding the supporting substrate to the p-type semiconductor layer. 14. The method of claim 13,
After the growth substrate separation,
Removing the GaN layer, the AlN layer, the first n-type semiconductor layer, and the second super lattice layer to expose one surface of the second n-type semiconductor layer. 15. The method of claim 14,
And forming a first electrode on the exposed surface of the second n-type semiconductor layer. The method of claim 6,
The p-type semiconductor layer and the active layer are partially removed to partially expose the second n-type semiconductor layer,
And forming a first electrode on the exposed surface of the second n-type semiconductor layer and a second electrode located on the p-type semiconductor layer. The method of claim 6,
Further comprising forming a GaN buffer layer on the growth substrate before forming the GaN layer. 18. The method of claim 17,
Wherein the growth substrate is a sapphire substrate,
And separating the growth substrate by using a laser lift-off.

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