KR20140140803A - Light emitting device and method for fabricating the same - Google Patents

Abstract

A light emitting device and a manufacturing method thereof are disclosed. The light emitting device includes a light emitting structure including a second conductivity type semiconductor layer, an active layer located on the second conductivity type semiconductor layer, and a first conductivity type semiconductor layer located on the active layer, A metal layer located under at least one second groove, under the second groove and at least a portion of the light emitting structure, and electrically connected to the second conductivity type semiconductor layer; And a first insulating layer which is located under the second groove and at least partially covers a side surface of the metal layer and a side surface of the second electrode pad, At least a portion of the first insulating layer is interposed between the side surface of the second electrode pad and the metal layer.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a light emitting device,

The present invention relates to a light emitting device and a manufacturing method thereof, and more particularly to a light emitting device including buried electrode pads and a method of manufacturing the same.

BACKGROUND ART [0002] Light emitting devices are inorganic semiconductor devices that emit light generated by recombination of electrons and holes, and have recently been used in various fields such as displays, automobile lamps, and general lighting.

In general, a horizontal type light emitting element in which an n-type electrode and a p-type electrode are arranged horizontally is widely used. Such a horizontal light emitting device has a relatively simple manufacturing method, but a part of the active layer is removed to form an electrode of the lower semiconductor layer, so that the light emitting area is reduced. In addition, the current-leaning phenomenon occurs due to the horizontal arrangement of the electrodes, thereby reducing the luminous efficiency of the light emitting device. In addition, the sapphire substrate is the most widely used as a growth substrate for a horizontal flat type light emitting device, and the sapphire substrate has low thermal conductivity, so that heat emission of the light emitting device is difficult. As a result, the junction temperature of the light emitting element is increased, and the internal quantum efficiency of the light emitting element is lowered.

Vertical light emitting devices and flip chip type light emitting devices have been developed to solve the problems of the horizontal light emitting device as described above, and disclosed in Korean Patent Laid-Open Publication No. 10-2010-0044726. 4 includes a conductive substrate 110, a first electrode layer 120, an insulating layer 130, a second electrode layer 140, a second semiconductor layer 150, and a second electrode layer 140 sequentially stacked. An active layer 160, and a first semiconductor layer 170. Here, in order to provide an electrical connection to the second semiconductor layer 150, an exposed region 145 extending in the horizontal direction from the second electrode layer 140 is formed, and an electrode pad portion (not shown) 147 are formed.

However, when the device having a structure such as this, the electrode pads and the exposed parts may result in damage to the oxide or the like, damage to parts of the electrode pad is to increase the contact resistance causes an increase of the forward voltage (V _f). Thus, the output of the light emitting element can be reduced, which causes the reliability of the light emitting element to be reduced and the life time shortened.

Korean Patent Publication No. 10-2010-0044726

SUMMARY OF THE INVENTION It is an object of the present invention to provide a light emitting device having a structure capable of preventing oxidation of an electrode pad and having a reduced contact resistance and a lower forward voltage.

A further object of the present invention is to provide a method for easily manufacturing the light emitting device.

A light emitting device according to an embodiment of the present invention includes a light emitting structure including a second conductive semiconductor layer, an active layer positioned on the second conductive semiconductor layer, and a first conductive semiconductor layer positioned on the active layer, At least one second groove penetrating the light emitting structure, a metal layer located under the second groove and at least a part of the light emitting structure, the metal layer being electrically connected to the second conductive type semiconductor layer, A second electrode pad located on the metal layer and a first insulating layer located below the second groove and at least partially covering a side surface of the metal layer and a side surface of the second electrode pad, The lower surface of the two-electrode pad is formed at a lower position than the lower surface of the second conductive type semiconductor layer, and at least a part of the first insulating layer is formed between the side surface of the second electrode pad and the metal layer .

According to this, it is possible to prevent the second electrode pad from being damaged and increase the contact resistance, and to prevent the forward voltage of the light emitting device from increasing.

The second electrode pad may include a plurality of electrode pad layers, and the second electrode pad may include an upper electrode pad layer and a lower electrode pad layer.

The side surface of the lower electrode pad layer may be covered with the first insulating layer, and at least a part of the side surface of the upper electrode pad layer may be exposed.

In addition, the lower electrode pad layer may include Al.

Furthermore, the upper electrode pad layer may include Au.

In some embodiments, the metal layer may include a reflective metal layer and a cover metal layer, the cover metal layer may cover the side and bottom surfaces of the reflective metal layer, and the reflective metal layer may be formed of the cover metal layer and the second conductive type And may be located between the semiconductor layers.

The lower surface of the second electrode pad may be in contact with the cover metal layer, and a portion of the second electrode pad may be buried in the cover metal layer.

Further, the cover metal layer may include multiple layers, and the cover metal layer may include a first cover metal layer covering the side surface of the second electrode pad and a second cover metal layer contacting the lower surface of the second electrode pad. have.

The adhesive force between the second cover metal layer and the second electrode pad bottom surface may be greater than the adhesive force between the first cover metal layer and the second electrode pad bottom surface.

Meanwhile, the first cover metal layer may include Ti, and the second cover metal layer may include Au.

The light emitting device may further include a first electrode which is in ohmic contact with the first conductivity type semiconductor layer and is located under the light emitting structure.

The light emitting device may further include at least one first groove located on a bottom surface of the light emitting structure and partially exposing the first conductivity type semiconductor layer.

The first electrode may be located in the first groove, and may extend downward from the first conductive semiconductor layer.

In other embodiments, the light emitting device may further include a second insulating layer for insulating the metal layer from the first electrode.

Furthermore, the light emitting device may further include a bonding layer and a first electrode pad, which are electrically connected to the first electrode and are positioned below the second insulating layer.

Meanwhile, the first electrode may be disposed along a region below a rim portion of the light emitting structure.

The second electrode pad may be disposed on one side of the light emitting structure and the first electrode may extend from the other side of the light emitting structure toward the second electrode pad.

In some embodiments, the light emitting structure may include lower mesas spaced apart by the first groove, and including the second conductive semiconductor layer and the active layer.

The metal layer may include a reflective metal layer and a cover metal layer, and the reflective metal layer may be positioned below the lower mesa, and the cover metal layer may cover the side surfaces and the bottom surface of the reflective metal layer.

A method of manufacturing a light emitting device according to another embodiment of the present invention includes forming a second conductive semiconductor layer, an active layer located on the second conductive semiconductor layer, and a first conductive semiconductor layer located on the active layer Forming a first insulating layer on the light emitting structure, and patterning the first insulating layer to partially expose the second conductivity type semiconductor layer, and exposing the surface of the exposed second conductivity type semiconductor layer and the second electrode layer Forming a metal layer covering the first insulating layer on the first electrode pad forming region, penetrating the light emitting structure and forming a second groove on the second electrode pad forming region, wherein a portion of the first insulating layer And exposing the metal layer to form a second electrode pad on the metal layer, wherein at least a portion of the first insulating layer is exposed on the first layer, Claim is interposed between the second electrode pad and the metal layer side.

Partially removing the first insulating layer may include removing an upper portion of the metal layer.

A portion of the side surface of the second electrode pad may be covered with the metal layer.

In addition, the first insulating layer may include SiO ₂ , and the first insulating layer may be partially removed with a BOE solution.

The metal layer may include multiple layers, and the metal layer may include a Ti layer located on the top.

The method of manufacturing a light emitting device according to claim 1, wherein a part of the second conductivity type semiconductor layer and a part of the active layer are removed to form a first groove partially on the lower surface of the first conductivity type semiconductor layer, Type semiconductor layer and the first electrode electrically connected to the lower surface of the first semiconductor layer.

The light emitting device manufacturing method may further include forming a second insulating layer covering at least a part of the side surface of the first electrode and insulating the first electrode from the metal layer.

According to the present invention, since at least a part of the side surface of the second electrode pad is covered with the first insulating layer, the second electrode pad can be prevented from being oxidized and damaged. Accordingly, it is possible to prevent the increase of the contact resistance and the forward voltage caused by the damage of the second electrode pad, thereby improving the reliability and lifetime of the light emitting device.

According to the method of manufacturing a light emitting device of the present invention, since the first insulating layer covering the side surface of the second electrode pad can be easily formed, the light emitting element having a structure capable of protecting the second electrode pad can be easily manufactured can do.

1 is a plan view illustrating a light emitting device according to an embodiment of the present invention.
Figs. 2 to 4 are sectional views corresponding to A-A ', B-B' and C-C ', respectively, in Fig.
5 to 16B are cross-sectional views and plan views illustrating a method of manufacturing a light emitting device according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so that those skilled in the art can sufficiently convey the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the width, length, thickness, etc. of components may be exaggerated for convenience. It is also to be understood that when an element is referred to as being "above" or "above" another element, But also includes the case where there are other components in between. Like reference numerals designate like elements throughout the specification.

1 is a plan view for explaining a light emitting device 100 according to an embodiment of the present invention, and FIGS. 2 to 4 correspond to A-A ', B-B', and C-C ' Respectively. Hereinafter, the light emitting device 100 of the present invention will be described in detail with reference to FIGS. 1 to 4. FIG.

1 to 4, a light emitting device 100 includes a light emitting structure 120 including a first conductive semiconductor layer 121, an active layer 123, and a second conductive semiconductor layer 125, A groove 211, a metal layer 140, a second electrode pad 150, and a first insulating layer 131. Further, the light emitting device 100 may include a first groove 213, a first electrode 160, a second insulating layer 133, a bonding layer 170, a first electrode pad 180, and a passivation layer 190 ). ≪ / RTI >

The light emitting structure 120 includes a first conductivity type semiconductor layer 121, an active layer 123 and a second conductivity type semiconductor layer 125. The first conductivity type semiconductor layer 121 includes a second conductivity type semiconductor layer 121, And the active layer 123 may be interposed between the first and second conductivity type semiconductor layers 121 and 125. In addition, the light emitting structure 120 may further include a roughness R formed on the upper surface thereof, and may further include a plurality of lower mesas M formed on the lower surface thereof.

The first conductive semiconductor layer 121 and the second conductive semiconductor layer 125 may include a III-V compound semiconductor, for example, a nitride semiconductor such as (Al, Ga, In) N, . The first conductivity type semiconductor layer 121 may include an n-type semiconductor layer doped with an n-type impurity (for example, Si), and the second conductivity type semiconductor layer 125 may include a p-type impurity (for example, , Mg) doped p-type semiconductor layer. It may also be the opposite. Further, the first conductive semiconductor layer 121 and / or the second conductive semiconductor layer 125 may be a single layer or may include multiple layers. For example, the first conductive semiconductor layer 121 and / or the second conductive semiconductor layer 125 may include a cladding layer and a contact layer, and may include a superlattice layer.

The active layer 123 may include a multiple quantum well structure (MQW), and an element forming the multiple quantum well structure and its composition may be adjusted so as to emit light having a desired peak wavelength in the multiple quantum well structure. For example, the well layer of the active layer 123 may be a ternary semiconductor layer such as In _x Ga _{y (1-x)} N (0 _x 1) or Al _x In _y Ga _(1-xy) N 0 < = x < = 1, 0 < y < 1, 0 x + y 1) . However, the present invention is not limited thereto.

Hereinafter, a description of the well-known semiconductor layers 121, 123, and 125 including the III-V compound semiconductor will be omitted.

The roughness R may be formed on the upper surface of the first conductivity type semiconductor layer 121, and may include irregular irregularities. Roughness (R) can be formed by wet etching or PEC etching or the like. By including the roughness R formed on the upper surface of the light emitting structure 120, light extraction efficiency of light emitted to the upper surface of the light emitting structure 120 can be improved.

The lower mesas M may be positioned below the light emitting structure 120 and each lower mesa M may include a second conductive semiconductor layer 125 and an active layer 123. Further, the lower mesa M may further include a part of the first conductivity type semiconductor layer 121.

The lower mesas M may be spaced apart from each other by the first grooves 213 and may be arranged in various shapes. For example, referring to FIGS. 1 and 3, the three lower mesas M may be arranged side by side in one direction, and may be arranged parallel to each other in the vertical direction as in FIG. Further, the lower mesas M may not be completely separated from each other, or may be partially connected to each other. That is, in this embodiment, the three lower mesas M may be connected to each other in a region between the first electrode 160 and the second electrode pad 150. However, the present invention is not limited thereto, and the lower mesa M may be formed and arranged in various shapes and sizes.

On the other hand, the light emitting structure 120 may have a sloped side surface. By having the light emitting structure 120 have inclined side faces, the light emitting efficiency can be improved.

The second grooves 211 may penetrate the light emitting structure 120. Accordingly, the second electrode pad 150 may be partially exposed to the lower portion of the second groove 211. The second grooves 211 may be formed at least one, and may also be formed at various positions. For example, as shown in FIG. 1, the second grooves 211 may be formed on one side of the light emitting device 100. However, the position of the second groove 211 is not limited to this, and may be formed as a plurality of two or more at various positions as necessary.

The metal layer 140 may be located below the second trench 211 and below at least a portion of the light emitting structure 120. For example, the metal layer 140 may be located under the second trenches 211 and below the lower mesas M. [ In addition, the metal layer 140 may be integrally formed over the entire light emitting device 100. The metal layer 140 may be electrically connected to the second conductive semiconductor layer 125. In this embodiment, the metal layer 140 is in direct contact with the second conductive semiconductor layer 125 and is electrically connected.

Further, the metal layer 140 may include a reflective metal layer 141 and a cover metal layer 143.

The reflective metal layer 141 may function to reflect light and may function as an electrode electrically connected to the second conductivity type semiconductor layer 125. Accordingly, the reflective metal layer 141 may include a metal having high reflectivity and capable of forming an ohmic contact with the second conductive semiconductor layer 125. For example, the reflective metal layer 141 may include at least one of Ni, Pt, Pd, Rh, W, Ti, Al, Ag and Au. Also, the reflective metal layer 141 may comprise a single layer or multiple layers.

The reflective metal layer 141 may be positioned below the lower mesa M and may contact the second conductive semiconductor layer 125. 2 and 3, the reflective metal layer 141 may be located below the lower mesa M and below the second conductive semiconductor layer 125, and the second conductive semiconductor layer 125 The area of the surface of the semiconductor wafer W may be smaller than the area of the semiconductor wafer W1. Accordingly, light directed downward from the light emitted from the active layer 123 can reach the reflective metal layer 141 and be reflected upward, so that light extraction efficiency of the light emitting device 100 can be improved.

The cover metal layer 143 can prevent mutual diffusion of the reflective metal layer 141 and other materials so that the reflective metal layer 141 is prevented from being damaged by diffusing other external materials into the reflective metal layer 141 . The cover metal layer 143 may be formed to cover the lower surface and the side surface of the reflective metal layer 141 and may be formed below the lower mesas M and under the second trench 211. [ The cover metal layer 143 may be integrally formed over the entire light emitting device 100 and may electrically connect the second conductive semiconductor layer 125 located in each of the lower mesas M. [ Further, the cover metal layer 143 may cover at least a part of the first insulating layer 131.

The cover metal layer 143 may be electrically connected to the reflective metal layer 141 and may be electrically connected to the second conductive semiconductor layer 125 to serve as an electrode together with the reflective metal layer 141. The cover metal layer 143 may include at least one of, for example, Au, Ni, Ti, Cr, and may include a single layer or multiple layers. Further, when the cover metal layer 143 includes multiple layers, the cover metal layer 143 may include a second cover metal layer and a first cover metal layer which are sequentially stacked. At this time, the cover metal layer 143 under the region where the second electrode pad 150 is located may not include the first cover metal layer, and thus the side surface of the second electrode pad 150 may be formed on the first cover metal layer And the lower surface of the second electrode pad 150 may be in contact with the second cover metal layer. For example, the cover metal layer 143 may include an Au layer, a Ti layer, a Ni layer, an Au layer, and a Ti layer which are sequentially stacked. The cover metal layer 143 under the region where the second electrode pad 150 is located ) May be composed of an Au layer, a Ti layer, an Ni layer, and an Au layer. Accordingly, a part of the side surface of the second electrode pad 150 may be covered with the Ti layer, and a part of the second electrode pad 150 may be buried in the cover metal layer 143. This will be described in detail later.

The first insulating layer 131 may be located below the light emitting structure 120 and may be located below the periphery of the rim of the lower mesas M and below the second groove 211. The first insulating layer 131 may at least partially cover the side surfaces of the metal layer 140 and the side surfaces of the second electrode pad 150. [ The first insulating layer 131 may include an insulating material, for example, SiO ₂ or SiN. Further, the first insulating layer 131 may include multiple layers, and may include a distributed Bragg reflector in which materials having different refractive indices are alternately stacked.

The second electrode pad 150 may be located in the second groove 211 and may be disposed on the metal layer 140. Further, the second electrode pad 150 may be electrically connected to the metal layer 140 to be electrically connected to the second conductive semiconductor layer 125. The second electrode pad 150 may electrically connect an external power source to the second conductive semiconductor layer 125.

The upper surface of the metal layer 140 under the second electrode pad 150 may be formed lower than the upper surface of the metal layer 140 in the other portion. Accordingly, the lower surface of the second electrode pad 150 may be formed at a lower position than the lower surface of the second conductive type semiconductor layer 125. Further, at least some of the side surfaces of the second electrode pad 150 may be covered with the first insulating layer 131, and some side surfaces of the second electrode pad 150 may be exposed. That is, at least a part of the first insulating layer 131 may be interposed between the side surface of the second electrode pad 150 and the metal layer 140, so that the second electrode pad 150 is electrically connected to the first insulating layer 131 And may be formed in a buried form.

The second electrode pad 150 is at least partly embedded in the first insulating layer 131 so that the side surface of the second electrode pad 150 is not exposed to the outside. Therefore, the second electrode pad 150 can be prevented from being oxidized, thereby preventing an increase in contact resistance and an increase in forward voltage due to oxidation of the electrode pad. Furthermore, reliability of the light emitting device 100 can be improved.

In addition, the second electrode pad 150 may include a plurality of electrode pad layers, and may include an upper electrode pad layer and a lower electrode pad layer. At this time, the side surface of the lower electrode pad layer can be covered with the first insulating layer 131 and further covered with the cover metal layer 143. The upper electrode pad layer may be partially covered with the first insulating layer 131. The upper electrode pad layer may include Au, and the lower electrode pad layer may include Al. When exposed to the outside, Al is easily oxidized compared to other metals, causing damage to the second electrode pad 150. According to the present embodiment, the lower electrode pad layer whose side is covered with the first insulating layer 131 includes Al, and the upper electrode pad layer includes Au, so that the surface of the second electrode pad 150 Damage can be prevented. In addition, since the second electrode pad layer 150 is embedded in the first insulating layer 131, the thickness of the upper electrode pad layer containing Au for preventing oxidation of Al can be reduced. Therefore, the amount of Au which is relatively expensive can be reduced, thereby reducing the manufacturing cost.

Specifically, for example, as shown in FIG. 16B, the cover metal layer 143 and the second electrode pad 150 may each include a plurality of layers. The cover metal layer 143 may include a first cover metal layer and a second cover metal layer. The first cover metal layer may include a Ti layer 1431 and the second cover metal layer may include an Au layer 1432, A Ni layer 1433, a Ti layer 1434, and an Au layer 1435. [ The second electrode pad 150 may include an upper electrode pad layer and a lower electrode pad layer, and the upper electrode pad layer may include an Au layer 1501. The lower electrode pad layer may include an Ni layer 1502, An Al layer 1503, and a Ni layer 1504. [ The side surfaces of the Al layer 1503 of the second electrode pad 150 are covered with the first insulating layer 131 and the Ti layer 1431 of the cover metal layer 143 to form the Al layer 1503 Oxidation can be prevented. Since the Ni layer 1504 of the second electrode pad 150 is more adhesive to the Au layer 1432 than the adhesion of the Ni layer 1504 to the Ti layer 1431, ). ≪ / RTI > This can prevent the contact resistance and the forward voltage from increasing due to the damage of the second electrode pad 150 and prevent the second electrode pad 150 from being peeled off from the cover metal layer 143 . However, the above-described metal layers are merely illustrative, and various other metals are included in the scope of the present invention.

1 to 4, the light emitting device 100 includes a first groove 213, a first electrode 160, a second insulating layer 133, a bonding layer 170, a first electrode pad 180 ), And a protective layer 190, as shown in FIG.

The first trench 213 is formed under the light emitting structure 120 and the lower surface of the second conductive type semiconductor layer 125 is partially exposed by the first trench 213. In addition, the first grooves 213 may be located between the lower mesas M and the side surfaces thereof, and may be formed along the imaginary line dividing the lower mesas M. [ For example, as shown in FIGS. 1 to 3, a first groove 213 may be formed in a region dividing a rim portion region of the light emitting device 100 and a lower mesa M, as shown in FIGS.

The first electrode 160 may be located on the lower surface of the light emitting structure 120 and may be located in the first groove 213 and may be in ohmic contact with the first conductive semiconductor layer 121. The first electrode 160 may extend from the first groove 213 and extend downward from the light emitting structure 120. The lower surface of the first electrode 160 may be formed to extend from the lower surface of the metal layer 140 Can be in a low position.

The first electrode 160 may be electrically connected to the first conductivity type semiconductor layer 121 to supply current to the first conductivity type semiconductor layer 121. The material of the electrode is not limited. For example, the first electrode 160 may include Ti, Ni, Au, Ag, Al, Cu, and the like. 1, the first electrode 160 may be located in a region between the edge region of the light emitting device 100 and the lower mesa M, and may be formed on the entire surface of the light emitting device 100 As shown in Fig. As a result, the current dispersion effect can be further improved.

However, the position and shape of the first electrode 160 are not limited to the above-described embodiments, and may be variously formed as needed.

The second insulating layer 133 may be located under the light emitting structure 120 and may be located between the metal layer 140 and the first electrode 160. The second insulating layer 133 may cover the bottom surface and the side surface of the metal layer 140 and at least a part of the side surface of the first electrode 160 and further may cover the entire lower surface of the light emitting structure 120. Accordingly, the second insulating layer 133 can isolate the metal layer 140 from the first electrode 160, thereby preventing the light emitting device 100 from being short-circuited.

The second insulating layer 133 fills the first groove 213 and may cover a part of the side surface of the first electrode 160. The second insulating layer 133 is formed so as to surround the first electrode 160 in the first groove 213 so that the first electrode 160 is electrically connected to the active layer 123 of the lower mesa M, It is possible to prevent the layer 125 from being electrically connected.

The second insulating layer 133 may include an insulating material and may include, for example, SiO ₂ , SiN. In addition, the second insulating layer 133 may include a plurality of layers.

Meanwhile, the first electrode 160 may protrude from the lower surface of the second insulating layer 133. Accordingly, the first electrode pad 180 electrically connected to the first electrode 160 can be easily formed under the insulating layer 133.

The bonding layer 170 may be located under the second insulating layer 133. In addition, the bonding layer 170 may cover at least a part of the lower surface and the side surface of the first electrode 160, and thus may be in contact with and electrically connected to the first electrode 160. The bonding layer 170 functions to bond the first electrode pad 180 to the light emitting structure 120 and may electrically connect the first electrode 160 and the first electrode pad 180 .

The bonding layer 170 may include a metal, for example, Au and Sn. The Au and Sn may include an eutectic structure, which may be formed through eutectic bonding. However, the bonding layer 170 is not limited thereto.

The first electrode pad 180 may be located below the bonding layer 170 and may electrically connect the first electrode 160 and the first conductive semiconductor layer 125 to an external power source.

The first electrode pad 180 may be a supporting substrate, or may be a conductive substrate, a circuit substrate, or an insulating substrate having a conductive pattern. In this embodiment, the first electrode pad 180 may include a metal, for example, a structure in which an Mo layer and a Cu layer are stacked. Further, the first electrode pad 180 may include Ti, Cr, Ni, Al, Cu, Ag, Au, Pt, and the like.

The protective layer 190 may cover the upper surface and side surfaces of the light emitting structure 120 and may partially cover the lower surface of the second trench 211. Also, the side surface of the second electrode pad 150 can be partially covered, and the upper surface of the second electrode pad 150 is exposed without being covered with the protective layer 190. The protective layer 190 may protect the light emitting structure 120 from the outside and may further include a roughness R so as to have a gentle slope than the slope of the roughness R on the upper surface of the first conductivity type semiconductor layer 121, So that the light extraction efficiency can be improved. The protective layer 190 may include an insulating material, for example, it may include SiO _2.

The light emitting device 100 according to the present embodiment includes a second electrode pad 150 embedded in the first insulating layer 131. Accordingly, it is possible to effectively prevent the second electrode pad 150 from being damaged due to oxidation or the like, thereby preventing contact resistance and an increase in forward voltage.

5 to 16B are cross-sectional views and plan views illustrating a method of manufacturing a light emitting device according to another embodiment of the present invention. Figs. 5 to 12 show a part of a cross section taken along the line B-B 'in Fig. 1, and Figs. 13 to 16A show a part of a cross section taken along the line A-A' in Fig.

5, a light emitting structure 120 including a first conductivity type semiconductor layer 121, an active layer 123, and a second conductivity type semiconductor layer 125 is formed on a growth substrate 110, A first insulating layer 130 is formed on the light emitting structure 120.

The growth substrate 110 is not limited as long as it can grow the light emitting structure 120 and may be, for example, a sapphire substrate, a silicon carbide substrate, a silicon substrate, a gallium nitride substrate, an aluminum nitride substrate, or the like. In particular, in this embodiment, the growth substrate 110 may be a patterned sapphire substrate (PSS) or a gallium nitride substrate.

The first conductivity type semiconductor layer 121, the active layer 123 and the second conductivity type semiconductor layer 125 may include a III-V compound semiconductor, for example, (Al, Ga, In) N, And may include the same nitride-based semiconductor. The first conductivity type semiconductor layer 121 may include an n-type impurity (for example, Si) and the second conductivity type semiconductor layer 125 may include a p-type impurity (for example, Mg) have. It may also be the opposite. The active layer 123 may comprise a multiple quantum well structure (MQW).

The first conductivity type semiconductor layer 121, the active layer 123 and the second conductivity type semiconductor layer 125 may be formed of a metal organic chemical vapor deposition (MOCVD), a molecular beam epitaxy (MBE), a hydride vapor phase epitaxy (HVPE) May be grown on the growth substrate 110 using the technique of FIG.

The first insulating layer 130 may be formed on the second conductive semiconductor layer 125 and may include an insulating material. For example, the first insulating layer 130 may be formed by depositing SiO ₂ on the second conductive semiconductor layer 125 using E-beam evaporation. The first insulating layer 130 may be formed to cover the second conductive semiconductor layer 125 and not expose the upper surface of the second conductive semiconductor layer 125.

6A and 6B, the upper surface of the second conductive type semiconductor layer 125 is partially exposed by patterning the first insulating layer 131, and the upper surface of the exposed second conductive type semiconductor layer 125 A reflective metal layer 141 is formed.

The first insulating layer 131 may be partially removed using wet etching or dry etching. For example, the first insulating layer 131 may be partially removed by wet etching using a buffered oxide etchant (BOE) solution. Also, as shown in FIG. 6B, the first insulating layer 131 may be patterned to have three openings. However, the patterning pattern shown in FIG. 6B corresponds to an example, and may be patterned in various forms, as shown in FIG.

After the first insulating layer 131 is patterned, the reflective metal layer 141 may be formed on the exposed region of the second conductive semiconductor layer 125. The reflective metal layer 141 may be formed on the second conductive type semiconductor layer 125 using a technique such as deposition or the like, and may be formed at a desired position using a lift-off technique or the like. Meanwhile, the reflective metal layer 141 may be formed to have a similar shape along the outline of the exposed region of the second conductive type semiconductor layer 125, or may be formed to have a smaller size than the exposed region. Accordingly, the first insulating layer 131 and the reflective metal layer 141 may be spaced apart from each other. 6B, within the region where the first insulating layer 131 is removed and the second conductivity type semiconductor layer 125 is exposed, the reflective metal layer 141 is formed along the outline of the exposed region And a gap may be formed between the reflective metal layer 141 and the first insulating layer 131. Referring to FIG.

The description related to the reflective metal layer 141 is substantially similar to that described in the embodiments of FIGS. 1 to 4, and therefore, a detailed description thereof will be omitted.

7A and 7B, a cover metal layer 143 is formed to cover the upper surface and the side surface of the reflective metal layer 141 to form the metal layer 140. FIG. The metal layer 140 may include a reflective metal layer 141 and a cover metal layer 143.

It is preferable that the cover metal layer 143 completely covers the side surface and the upper surface of the reflective metal layer 141 so that the reflective metal layer 141 is not exposed. Further, the cover metal layer 143 may partly cover the first insulating layer 131, and thus may be filled in the gap between the reflecting metal layer 141 and the first insulating layer 131. The cover metal layer 143 may be integrally formed and may be formed to cover the first insulating layer 131 on one side of the growth substrate 110, as shown in FIG. 7B. That is, as shown in FIG. 7B, the cover metal layer 143 is formed around the one edge of the growth substrate 110 in parallel with the one edge, and is formed along three axes extending in the other direction from the edge. As shown in FIG. Accordingly, the first insulating layer 131 can be partially exposed. However, the shape of the cover metal layer 143 is not limited to that of the present embodiment, and may be variously formed depending on the patterning pattern of the first insulating layer 131, the shape of the reflective metal layer 141, and the like.

The cover metal layer 143 may be formed using deposition and lift-off techniques. The description related to the cover metal layer 143 is substantially the same as that described in the embodiments of FIGS. 1 to 4, and thus a detailed description thereof will be omitted.

Referring to FIG. 8, the first insulating layer 131 and the light emitting structure 120 are partially removed to form a first trench 213. By forming the first trenches 213, the first conductivity type semiconductor layer 121 can be partially exposed.

The first groove 213 may be formed in a region where the first insulating layer 131 is exposed, for example, in a region where the first insulating layer 131 is exposed in FIG. 7B. The first groove 213 is formed by removing the first insulating layer 131 by wet etching using BOE or the like and then removing the second conductive semiconductor layer 125 and the active layer 123 by dry etching . At this time, the first conductive semiconductor layer 121 may be further etched.

On the other hand, the first groove 213 is formed to form the lower mesa M including the second conductivity type semiconductor layer 125 and the active layer 123. The lower mesa M may be divided into a plurality of portions by the first groove 213. By forming the lower mesa M, the reflective metal layer 141 can be positioned on the lower mesa M.

9, a second insulating layer 133 is formed to cover the cover metal layer 143, the first insulating layer 131, and fill the first trenches 213. Referring to FIG. The second insulating layer 133 may be formed entirely on the growth substrate 110 so that the cover metal layer 143 is not exposed and the first insulating layer 133 may be formed in the first groove 213 The second conductive semiconductor layer 125 and the side surfaces of the active layer 123, that is, the side surfaces of the lower mesa M, are preferably formed.

The second insulating layer 133 may include SiO ₂ , and may be formed using a method such as electron beam deposition.

10A and 10B, an opening is formed by partially removing the second insulating layer 133 and patterning the first insulating layer 133. Accordingly, the first conductive semiconductor layer 121 under the first groove 213, To be partially exposed. Thereafter, the first electrode 160 filling the opening is formed.

Partially removing the second insulating layer 133 may include removing a second insulating layer 133 located over the first groove 213 and the second insulating layer 133 may include removing BOE Can be removed using a wet etch. At this time, it is preferable that an opening is formed between the opening portion formed in the second insulating layer 133 and the second conductive semiconductor layer 125 and the active layer 123 so that the second insulating layer 133 remains. When the second conductivity type semiconductor layer 125 or the active layer 123 is exposed during the formation of the opening, the first electrode 160 and the second conductivity type semiconductor layer 125 may contact with each other and an electrical failure may occur. Therefore, it is preferable that the opening is formed such that the side surface of the opening is surrounded by the second insulating layer 133 and the first conductivity type semiconductor layer 121 is exposed only on the bottom surface.

Next, the first electrode 160 filling the opening formed by partially removing the second insulating layer 133 is formed. The first electrode 160 may be formed using deposition and lift-off. In addition to filling the opening, the first electrode 160 may protrude from the second insulating layer 133 and may cover a part of the upper surface of the second insulating layer. Accordingly, when the bonding layer 170 described later is formed, the bonding layer 170 can be more effectively contacted.

Meanwhile, the first electrode 160 may be formed on the first groove 213 and integrally formed as shown in FIG. 10B. In addition, since it is formed on one side of the growth substrate 110 so as not to be deviated, the current dispersion effect can be improved. The formation position of the first electrode 160 may be variously formed depending on the formation position of the first groove 213, and the present invention is not limited to the shape shown in FIG. 10B.

The description related to the first electrode 160 is substantially similar to that described in the embodiments of FIGS. 1 to 4, and therefore, a detailed description thereof will be omitted.

Next, referring to FIG. 11, the growth substrate 110 is separated from the light emitting structure 120.

The growth substrate 110 may be removed by various methods, such as, for example, laser lift-off, chemical lift-off, or stress lift-off. Depending on the method of removing the growth substrate 110, additional layers may be further interposed between the light emitting structure 120 and the growth substrate 110. For example, when the growth substrate 110 is a sapphire substrate, the growth substrate 110 may be removed by laser lift off. At this time, the manufacturing method may further include forming a sacrificial layer (not shown) between the growth substrate 110 and the light emitting structure 120.

Referring to FIG. 12, a bonding layer 170 and a first electrode pad 180 are formed on a second insulating layer 133.

The bonding layer 170 is in ohmic contact with the first electrode 160 and bonds the first electrode pad 180 with the light emitting structure 120. The bonding layer 170 may be formed by bonding the first electrode pad 180, the second insulating layer 133, and the first electrode 160 on the second insulating layer 133. For example, AuSn may be used to process bond the second insulating layer 133 and the first electrode 160 and the first electrode pad 180 so that the bonding layer 170 includes AuSn . In the process bonding using AuSn, the AuSn is heated to a temperature (for example, about 350 DEG C) higher than the process temperature of AuSn (Eutectic temperature, about 280 DEG C), and then the heated AuSn is bonded to the second insulating layer 133 and the first And the electrode pad 180, and cooling the AuSn.

The first electrode pad 180 may be a supporting substrate, for example, a conductive substrate, a circuit substrate, or an insulating substrate having a conductive pattern. In this embodiment, the first electrode pad 180 may include a metal, for example, a structure in which an Mo layer and a Cu layer are stacked. Further, the first electrode pad 180 may include Ti, Cr, Ni, Al, Cu, Ag, Au, Pt, and the like.

The first electrode pad 180 may serve to support the light emitting structure 120 and may function as an electrode pad electrically connected to the first conductive semiconductor layer 121.

Referring to FIG. 13, a part of the light emitting structure 120 is removed to form a second groove 211 penetrating the light emitting structure 120. Further, the roughness R is formed on the surface of the first conductivity type semiconductor layer 121. Roughness (R) may be formed by wet etching using a solution containing at least one of KOH and NaOH, or may be formed using PEC etching. The roughness R may be formed naturally on the separation surface of the first conductivity type semiconductor layer 121 when the growth substrate 110 is separated from the first conductivity type semiconductor layer 121. For example, when the growth substrate 110 is separated from the first conductivity type semiconductor layer 121 using a chemical lift-off or a stress lift-off, a sacrificial layer (not shown) The roughness R may be formed on the separation surface of the first conductivity type semiconductor layer 121 from the cavity formed in the first conductivity type semiconductor layer.

However, the above-described methods for forming the roughness R correspond to examples, and the roughness R is formed on the upper surface of the first conductivity type semiconductor layer 121 using various methods known to those skilled in the art can do.

Fig. 13 is a top view and a bottom view opposite to those shown in Fig. 5 to Fig. Hereinafter, the concept of the top and bottom will be described based on the one shown in Fig. However, the concept of the above and below is for convenience of description, and the present invention is not limited thereto. FIG. 13 partially shows a cross-section of a portion corresponding to A-A 'in FIG.

The second trench 211 may be formed on one side of the light emitting structure 120 and may include a first conductive semiconductor layer 121, an active layer 123, and a second conductive semiconductor layer 125 ). ≪ / RTI > In particular, the second groove 211 may be formed in a portion where only the cover metal layer 143 is formed without forming the reflective metal layer 141 below. When the second trench 211 is formed, the first insulating layer 131 may be partially exposed under the second trench 211. The width of the lower surface of the second groove 211 is preferably smaller than the width of the first insulating layer 131 located below the second groove 211.

Referring to FIG. 14, a protective layer 190 is formed to cover the top and side surfaces of the light emitting structure 120 and the second trenches 211. The protective layer 190 may include an insulating material, for example, it may include SiO _2. The protective layer 190 may be formed using a technique such as electron beam deposition.

15A and 15B, the protective layer 190 and the first insulating layer 131 located under the second groove 211 are partially removed to expose the cover metal layer 143. Next, as shown in FIG. Accordingly, the second electrode pad formation region 150 'may be formed in the region where the protection layer 190 and the first insulation layer 131 are removed. On the other hand, the second electrode pad formation region 150 'may be surrounded by the first insulation layer 131.

In addition, while the protective layer 190 and the first insulating layer 131 are removed, the cover metal layer 143 can be partially removed. Accordingly, the side surface of the second electrode pad formation region 150 'may be partially surrounded by the cover metal layer 143. For example, when the protective layer 190 and the first insulating layer 131 include SiO ₂ and the cover metal layer 143 includes multiple layers and a Ti layer is formed on the top thereof, When the layer 190 and the first insulating layer 131 are partially etched, the Ti layer may also be etched into the BOE. 15B, the Au layer 1435, the Ti layer 1434, the Ni layer 1433, the Au layer 1432, and the Ti layer 1431, in which the cover metal layer 143 is sequentially stacked, When the protective layer 190 and the first insulating layer 131 are etched using BOE, the uppermost Ti layer 1431 is etched at the same time. Therefore, the upper surface of the cover metal layer 143 under the second electrode pad formation region 150 'becomes the Au layer 1432 instead of the Ti layer 1431. Accordingly, if the second electrode pad 150 is formed using a metal having a stronger adhesion to the Au layer 1432 than the Ti layer 1431, peeling of the second electrode pad 150 can be prevented. However, the present invention is not limited thereto. If necessary, the multi-layered material constituting the cover metal layer 143 may be variously used.

Referring to FIGS. 16A and 16B, a second electrode pad 150 is formed in the second electrode pad formation region 150 '. Accordingly, the light emitting device 100 shown in Figs. 1 to 4 can be provided.

The second electrode pad 150 can contact the cover metal layer 143 and is covered at least a part of its side by the first insulating layer 131. Furthermore, the protective layer 190 also covers at least a part of the side surface of the second electrode pad 150.

The second electrode pad 150 may be formed using deposition and lift-off techniques. The second electrode pad 150 is formed in the second electrode pad formation region 150 'so that at least a portion of the side surface of the second electrode pad 150 can be covered with the first insulation layer 131. [ Accordingly, damage such as oxidation of the second electrode pad 150 can be prevented, and contact resistance and forward voltage can be prevented from increasing. The description related to the second electrode pad 150 is substantially the same as that described in the embodiments of FIGS. 1 to 4, and thus a detailed description thereof will be omitted.

Referring to FIG. 16B, the second electrode pad 150 may include an upper electrode pad layer and a lower electrode pad layer. At this time, the upper electrode pad layer may include an Au layer 1501, and the lower electrode pad layer may include an Ni layer 1504, an Al layer 1503, and an Ni layer 1502 which are sequentially stacked. The cover metal layer 143 is the same as that in Fig. 15B. The Ni layer 1504 positioned at the lowermost portion of the second electrode pad 150 has a larger adhesive force with Au than Ti. The lower surface of the second electrode pad 150 is brought into contact with the Au layer 1432 and the second electrode pad 150 and the cover metal layer 143 Can be more stably contacted. In addition, since the Ti layer 1431 of the cover metal layer 143 is etched at the same time during the etching process of the protective layer 190 and the first insulating layer 131, an additional process is required to partially remove the cover metal layer 143 It does not.

Meanwhile, although the present embodiment describes a method of manufacturing one light emitting device 100, the present invention is not limited thereto. For example, it is also included in the present invention that a plurality of light emitting structures 120 are formed on a growth substrate 110, and then a plurality of light emitting devices 100 are formed by separating the plurality of light emitting structures 120.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, Variations and changes are possible.

Claims (26)

A light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, an active layer disposed on the second conductive semiconductor layer, and a first conductive semiconductor layer disposed on the active layer;
At least one second groove penetrating the light emitting structure;
A metal layer located under the second groove and at least a portion of the light emitting structure and electrically connected to the second conductivity type semiconductor layer;
A second electrode pad located in the second groove and positioned on the metal layer; And
And a first insulating layer located below the second groove and at least partially covering a side surface of the metal layer and a side surface of the second electrode pad,
Wherein a lower surface of the second electrode pad is formed at a position lower than a lower surface of the second conductive type semiconductor layer, and at least a portion of the first insulating layer is interposed between the side surface of the second electrode pad and the metal layer. The method according to claim 1,
Wherein the second electrode pad includes a plurality of electrode pad layers, and the second electrode pad includes an upper electrode pad layer and a lower electrode pad layer. The method of claim 2,
Wherein a side surface of the lower electrode pad layer is covered with the first insulating layer, and at least a side surface of the upper electrode pad layer is exposed. The method of claim 3,
Wherein the lower electrode pad layer comprises Al. The method of claim 3,
Wherein the upper electrode pad layer comprises Au. The method according to claim 1,
Wherein the metal layer comprises a reflective metal layer and a cover metal layer,
Wherein the cover metal layer covers side surfaces and bottom surfaces of the reflective metal layer, and the reflective metal layer is located between the cover metal layer and the second conductive type semiconductor layer. The method of claim 6,
The lower surface of the second electrode pad is in contact with the cover metal layer,
And a portion of the second electrode pad is buried in the cover metal layer. The method of claim 7,
Wherein the cover metal layer includes multiple layers, and the cover metal layer includes a first cover metal layer covering the side surface of the second electrode pad and a second cover metal layer contacting the lower surface of the second electrode pad. The method of claim 8,
Wherein the adhesive force between the second cover metal layer and the second electrode pad bottom surface is greater than the adhesive force between the first cover metal layer and the second electrode pad bottom surface. The method of claim 8,
Wherein the first cover metal layer comprises Ti, and the second cover metal layer comprises Au. The method according to claim 1,
And a first electrode that is in ohmic contact with the first conductive semiconductor layer and is located under the light emitting structure. The method of claim 11,
And at least one first groove located on a bottom surface of the light emitting structure and partially exposing the first conductive type semiconductor layer. The method of claim 12,
Wherein the first electrode is located in the first groove and extends downward from the first conductive semiconductor layer. The method of claim 11,
And a second insulating layer for insulating the metal layer from the first electrode. 15. The method of claim 14,
Further comprising a bonding layer and a first electrode pad electrically connected to the first electrode and positioned under the second insulating layer. 14. The method of claim 13,
Wherein the first electrode is disposed along a region below a rim portion of the light emitting structure. 18. The method of claim 16,
The second electrode pad is disposed on one side of the light emitting structure,
Wherein the first electrode extends from the other side of the light emitting structure toward the second electrode pad. The method of claim 12,
Wherein the light emitting structure includes lower mesas spaced apart by the first trench and including the second conductive semiconductor layer and the active layer. 19. The method of claim 18,
Wherein the metal layer comprises a reflective metal layer and a cover metal layer,
Wherein the reflective metal layer is positioned below the lower mesas, and the cover metal layer covers side and bottom surfaces of the reflective metal layer. Forming a first insulating layer on the light emitting structure including the second conductive semiconductor layer, the active layer located on the second conductive semiconductor layer, and the first conductive semiconductor layer located on the active layer;
Patterning the first insulating layer to partially expose the second conductive type semiconductor layer;
Forming a metal layer covering the surface of the exposed second conductive type semiconductor layer and the first insulating layer on the second electrode pad forming region;
Forming a second groove on the second electrode pad formation region through the light emitting structure, wherein a portion of the first insulation layer is exposed under the second groove;
Partially removing the first insulating layer below the second groove to expose the metal layer;
And forming a second electrode pad on the metal layer,
Wherein at least a part of the first insulating layer is interposed between the side of the second electrode pad and the metal layer. The method of claim 20,
Wherein the partially removing the first insulating layer comprises removing an upper portion of the metal layer. 23. The method of claim 21,
Wherein a portion of a side surface of the second electrode pad is covered with the metal layer. 23. The method of claim 21,
The first insulating layer includes the SiO _2,
Wherein the first insulating layer is partially removed with a BOE solution. 24. The method of claim 23,
Wherein the metal layer comprises multiple layers and the metal layer comprises a Ti layer located on top. The method of claim 20,
The second conductivity type semiconductor layer and a part of the active layer are removed to form a first groove partially on the lower surface of the first conductivity type semiconductor layer,
And forming a first electrode electrically connected to the lower surface of the first conductive semiconductor layer exposed in the first groove. 26. The method of claim 25,
Further comprising forming a second insulating layer covering at least a part of a side surface of the first electrode and insulating the first electrode from the metal layer.

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