KR20140140305A - Display device - Google Patents

Abstract

The present invention relates to a display device using an organic electroluminescent device as a light emitting device, and a display device 10 includes a plurality of pixel circuits Px (i, j) of n rows and m columns (m and n are natural numbers respectively) And a plurality of pixel circuits of n rows and m columns are composed of a plurality of pairs of pixel circuit columns each consisting of a pair of pixel circuit columns composed of pixel circuits of two columns of odd and even columns adjacent to each other, The row (Px (i, j)) shares a data line (Ldj) for applying a gray-scale signal, and a gate line for applying row selection signals to the plurality of pixel circuits in the m- The gate line Lgiodd for the circuit and the gate line Lgieven for the even-column pixel circuit.

Description

Display device {DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device and a display method, and more particularly to an organic light emitting display device using an organic electroluminescent device as a light emitting device.

An organic electroluminescent device (hereinafter referred to as " organic EL device ") has a structure in which an organic light emitting layer containing an organic compound is inserted between a pair of electrodes formed of a positive electrode and a negative electrode formed on a transparent substrate such as glass, Holes and electrons are injected into the organic light emitting layer from the pair of electrodes to recombine the excitons to emit excitons to emit light when the excitons lose their activity, Emitting device.

An organic electroluminescent display device using the organic electroluminescent device as a light emitting device (hereinafter sometimes simply referred to as " organic electroluminescent display device ") is lightweight and thin and has excellent brightness and viewing angle characteristics Has attracted attention as a next generation flat panel display device.

FIG. 1 is a diagram illustrating the configuration of a driving unit of a conventional organic light emitting display device.

1 (a), a conventional organic light emitting diode display device 1 includes a plurality of pixel circuits 11 (i, j) (i = 1 to n, j = 1 to m , a gate driver (row selection driver) 12, a data driver 14, a controller 15, and an anode driver (not shown).

1 (b), each pixel circuit 11 (i, j) corresponds to each pixel of the image, and each pixel circuit 11 (i, j) Two transistors T11 and T12, and a capacitor C1.

The gate driver 12 sequentially outputs the high level output signal OUT [k] to the gate lines Lg1, Lg2, ..., Lgn under the control of the controller 15, (N, 1) to 11 (n, m) are sequentially selected and the data driver 14 selects (1, 1) to 11 (1, m), 11 (2,1) to 11 (2, m) by applying the gradation signals based on the pixel data to the data lines Ld1 to Ldm, , 11 (n, 1) to 11 (n, m)).

When the writing is completed in this manner, the controller 15 controls the unillustrated anode driver so that the anode driver supplies the anode voltage signals VDD (1) to VDD (n) at the high level to the anode lines La ) To La (n), whereby the transistor T12 of the pixel circuit 11 (i, j) uses the voltage held by each capacitor C1 as the gate voltage, and outputs the gate voltage Vgs And supplies a corresponding current to the organic EL element 101 to emit light.

However, in the OLED display 1 of FIG. 1, one gate line per row unit and one data line per column unit are formed, and each pixel circuit is formed at a position where the gate line and the data line cross each other.

Therefore, for example, when the organic light emitting display device is a display device having a resolution of VGA (640 × 480), 640 gate lines are required, and in the case of the color display device, 1440 (= 480 × 3) 1280 gate lines are required for a display device having an HD (1280 x 720) resolution, and 2160 (= 720 x 3) data lines are required for a color display device.

In FIG. 1, for convenience of description, each driver including a controller is not shown as being arranged at the right and left sides of a display unit composed of a plurality of pixel circuits, but in an actual display device, And the various drivers including the controller are respectively disposed in the lower part of the rectangular bezel in the form of IC or the like and the gate line and each anode line are drawn out from the IC And extend in the row direction through the left and right side bezels, and the data lines extend from the IC in the vertical direction of the display portion.

Therefore, as the number of various lines including the gate line increases, the width of the bezel of the display device must be widened. Also, due to the parasitic capacitance generated at the intersection of the gate line and the data line, The number of lines constituting various lines including the gate line should be as small as possible. In order to reduce the number of lines connecting the IC and each pixel circuit, one gate line is required to have two or more rows of pixels A method in which two rows of pixels share one gate line or a method in which two rows of pixels share one data line can be considered.

A display device described in Patent Document 1 is known as a method in which pixels of two columns share one data line.

2 is a circuit diagram showing a schematic configuration of a conventional organic light emitting diode display device described in Patent Document 1. In FIG.

2A, the organic light emitting diode display of Patent Document 1 includes a plurality of selection gate lines S1-Sn, a plurality of light emission gate lines Em11-Em1n, Em21-Em2n, and a plurality of data lines And a plurality of unit pixels 110. Each unit pixel 110 includes two sub pixels 111 and 112 arranged in a column direction.

2B, the two sub pixels 111 and 112 formed in one unit pixel share one pixel and the pixel driving part 115, and the pixel driving part 115 is connected to the driving transistor M1, a switching transistor M2 and a capacitor C1.

In addition, the scan driver 200 divides one field into two subfields, sequentially applies a selection signal to a plurality of selection gate lines (S1-Sn) in each subfield, and a plurality The emit signal is sequentially applied to the emit gate lines Em11-Em1n of the first subfield, and the emit signal is sequentially applied to the plurality of emit gate lines Em21-Em2n in the next subfield.

The data driver 300 applies a data signal to the data lines D1 to Dn and applies a data signal corresponding to the subpixel 111 in one subfield and corresponds to the subpixel 112 in the next subfield. The data signal is applied.

In Patent Documents 2 to 5, a plurality of selection gate lines (S1-Sn), a plurality of light emission gate lines (Em11-Em1n, Em21-Em2n), a plurality of data lines (D1-Dm) Each unit pixel 110 includes two sub-pixels 111 and 112 arranged in a column direction, and two sub-pixels formed in each unit pixel are divided into one select gate line and pixel A display device sharing the driver 115 is described.

Patent Document 1: JP-A-2005-0000759 Patent Document 2: Japanese Patent Application Laid-Open No. 2004-0037266 Patent Document 3: Japanese Patent Application Laid-Open No. 2004-0037288 Patent Document 4: Japanese Patent Application Laid-Open No. 2004-0038260 Patent Document 5: Japanese Patent Application Laid-Open No. 2004-0038261

Since the two subpixels formed in each unit pixel share one select gate line and the pixel driver, the description of the above Patent Documents 1 to 5 is based on the fact that one data line Dj, one select gate line Si, A pixel driver 115 including a transistor and a capacitor C1 shares two sub pixels 111 and 112 to thereby constitute a data line Dj and a selection gate line Si and a pixel driver 115 It is possible to reduce the number of transistors and capacitors.

However, since the display devices of Patent Documents 1 to 5 divide each unit pixel 110 into two sub-pixels 111 and 112 arranged in the column direction and drive them separately, Two transistors M3a (Em1-Em1n) connected to the two light-emitting gate lines (Em11-Em1n) and the light-emitting gate lines (Em21-Em2n) need a plurality of gate lines (Em11-Em1n) And M3b. As a result, the number of transistors per unit pixel is the same as that of the related art, and the number of gate lines (gate lines) is rather increased. Therefore, the number of all signal lines , Which leads to an increase in RC delay and voltage drop, and furthermore, a decrease in the aperture ratio of the display device and a decrease in resolution.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to reduce the number of data lines of a display device, thereby reducing a width of a bezel required for an extended arrangement of data lines, And further to improve the aperture ratio and the resolution of the panel as the data line decreases.

Further, the present invention reduces the number of anode lines of the display device, thereby reducing the width of the bezel required for the extended arrangement of the anode lines, while reducing the RC delay and the voltage drop, and further improving the aperture ratio And to increase the resolution of the panel.

A display device of the present invention for solving the above problems is a display device including a plurality of pixel circuits of n rows and m columns (m and n are natural numbers respectively), wherein the plurality of pixel circuits of the n rows and m columns are adjacent to each other And a plurality of pairs of pixel circuit columns each including a pair of pixel circuit columns constituted by pixel circuits of two columns of an odd column and an even column, wherein the pair of pixel circuit columns share a data line for applying gray level signals, a gate line for applying a row selection signal to each of a plurality of pixel circuits of m rows and n columns on a row basis is composed of a gate line for an odd column pixel circuit and a gate line for an even column pixel circuit.

The display device of the present invention is a display device having a plurality of pixel circuits of n rows and m columns (m and n are natural numbers respectively), and is composed of pixel circuits of two columns of odd number columns and even number columns adjacent to each other in the column direction An odd column pixel circuit gate line for applying a row select signal to each of the odd column pixel circuits on a row basis; A gate line for an even-numbered column circuit for applying a row selection signal in units of a pixel circuit unit and a data line for applying a gray-scale signal in units of the pair of pixel circuit columns.

The even-numbered pixel circuits of the pair of pixel circuit columns and the odd-numbered column pixel circuits of the other pair of pixel circuit columns adjacent to the pair of pixel circuit columns may share the anode line for applying the anode voltage to each pixel circuit.

Wherein each of the plurality of pixel circuits includes a switching transistor which is driven by the row selection signal and applies a gradation signal representing the gradation of the image data to one end of the capacitor and a current control circuit which is driven by the switching transistor to output a current based on the gradation signal Wherein the switching transistor of the odd column pixel circuit comprises a driving transistor for supplying a driving current to the organic EL element, a capacitor for charging the gray level signal, and an organic EL element for emitting light with a luminance corresponding to the current amount of the current, And the switching transistors of the even column pixel circuits may be connected to the gate lines for the even column pixel circuits.

And the switching transistors of the odd column pixel circuits and the even column pixel circuits may be n-channel FETs.

The switching transistors of the odd column pixel circuits and the even column pixel circuits may be p-channel FETs.

A switching transistor of the odd-number column pixel circuit has a gate connected to the gate line for the odd-numbered column pixel circuit, a source and a drain form a first current path between the data line and the gate of the driving transistor and one end of the capacitor , The switching transistor of the even column pixel circuit has a gate connected to the gate line for the even column pixel circuit and a source and a drain form a first current path between the data line and the gate of the driving transistor and one end of the capacitor Wherein the driving transistor has a gate connected to one end of the first current path and one end of the capacitor, and a source and a drain form a second current path between the other end of the capacitor and the anode power supply terminal and the organic EL element Maybe.

According to the present invention, the number of data lines of the display device can be reduced in half, so that the number of intersections at which the data lines intersect the lines supplying different signals decreases, thereby reducing the parasitic capacitance at the intersections, The RC delay (RC delay) of the row selection signal supplied from the line decreases, and the voltage drop (IR Drop) generated in the gate line can also be reduced.

In addition, since the number of data lines is reduced to half compared with the conventional one, the aperture ratio of the display device increases, thereby increasing the resolution of the display device.

In addition, since the number of anode lines can be greatly reduced, the present invention can achieve the same effect as the reduction of the data lines.

FIG. 1 is a diagram illustrating the configuration of a driving unit of a conventional organic light emitting display device.
2 is a diagram showing a schematic configuration of a conventional organic light emitting diode display.
3 is a diagram showing the configuration of a driving unit of a display device according to a preferred embodiment of the present invention.
4 is a circuit diagram showing a schematic configuration of the pixel circuit of the display device of Fig.
5 is a timing chart showing driving timings of a display apparatus according to a preferred embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 3 is a diagram showing the configuration of a driving section of a display apparatus according to a preferred embodiment of the present invention, and FIG. 4 is a circuit diagram showing a schematic configuration of some pixel circuits of the display apparatus of FIG.

3, the display device 10 of the present embodiment includes a plurality of pixel circuits Px (i, j) (i = 1 to n, n, (a row selection driver) 12, a data driver 14, an anode driver 13, and a controller 15, each of which is composed of a gate driver (j = 1 to m, m and n are natural numbers).

Here, the pixel circuit Px (i, j) corresponds to each pixel of the display section.

The display device 10 of the present embodiment is a display device in which a plurality of pixel circuits of n rows and m columns constituting a display unit are constituted of a plurality of pixel circuit columns each consisting of a pixel circuit composed of two rows of odd- For example, an odd column pixel circuit (Pxodd (1,1 to n, 1)) and an even column pixel circuit (Pxeven (1,2 to n And 2 share a data line Ld1 for applying a gray scale signal supplied from the data driver 14 to each pixel circuit.

A pair of pixel circuit arrays consisting of the odd-numbered column pixel circuits Pxodd (1,3 to n, 3) and the even-numbered column pixels Pxeven (1,4 to n, 4) And a data line Ld2 for supplying a gray-scale signal to be applied.

In the same manner, a pair of pixel circuits (Pxodd (1, m-1 to n, m-1) composed of the last pair of odd column pixel circuits (Ldm / 2, m is an even number) for supplying a gray-scale signal applied from the archival data driver 14.

On the other hand, in the display device 10 of the present embodiment, even-numbered column circuits (Pxeven (1, 2 to n, 2)) of the first pair of pixel circuits in the column direction and odd- The pixel circuits Pxodd (1,3 to n, 3) share the anode line La2 for supplying the anode voltage VDD applied from the anode driver 13.

The pixel circuits Pxeven (1,4 to n, 4) in the even-numbered columns of the second pair of pixel circuits and the odd-numbered column circuits Pxodd (1,5 to n, 5) Share the anode line La3 for supplying the anode voltage VDD applied from the anode driver 13. [

(Pxeven (1, m-2 to n, m-2) in the even-numbered column of the last and the second pair of pixel circuits and the odd column pixel circuit (Pxodd , m-1 to n, m-1) also share an anode line (Lan / 2) for supplying the anode voltage VDD applied from the anode driver 13.

However, the pixel circuits in the first column and the m-th column do not share the anode lines in the two columns, but have one anode line in one column. That is, in the pixel circuit column Pxodd (1,1 to n, 1) in the first column, the anode voltage VDD is applied from the anode line La1 and the pixel circuit column Pxodd (1, m to n, m) is supplied with the anode voltage (VDD) from the anode line (Lan / 2 + 1).

On the other hand, in the present embodiment, the gate lines for applying the row selection signals supplied from the gate driver 12 to the respective pixel circuits are connected to the gate lines Lgiodd for the odd column pixel circuits and the gate lines Lgieven for the even- It consists of two gate lines.

In general, the display device 10 of the present embodiment has a structure in which a plurality of pixel circuits of n rows and m columns are constituted of a plurality of pixel circuit columns each consisting of a pixel circuit composed of two columns of odd-numbered columns and even- And a data line for applying a gray scale signal supplied from the data driver 14 to each pixel circuit in the pair of pixel circuit column units is shared.

In this embodiment, the even-numbered column circuit of any one of the plurality of pairs of pixel circuit columns and the odd-numbered column circuit of the next pair of pixel circuit columns are connected to the respective anode- And the anode line to which the voltage VDD is applied (except for the first column and the m-th column).

In this embodiment, a gate line for applying a row selection signal supplied from the gate driver 12 to each pixel circuit on a row-by-row basis is connected to the gate line Lgiodd for the odd column pixel circuit and the gate line Lgiodd for the even- Lgieven).

Accordingly, the row selection signal supplied from the gate driver 12 through each gate line in units of rows is divided into a first half pulse period and a second half pulse period, A signal of a high level is applied to the gate line Lgiodd of the odd column pixel circuit, and a signal of High level is applied to the gate line Lgieven of the even column pixel circuit in the second half pulse period.

As described above, in the display device 10 of the present embodiment, the number of data lines is reduced by half (1/2) as compared with the conventional display device 1 because one data line is shared by two columns of pixel circuit columns. .

In addition, since the even-numbered pixel circuits of a pair of pixel circuit rows except for the first column and the mth column and the odd-numbered column pixel circuits of the next pair of pixel circuit columns share the anode line, the conventional display device 1 The number of anode lines can be reduced to about half (precisely m / 2-1).

Next, the pixel circuit of this embodiment will be described in detail.

Fig. 4 is a circuit diagram showing a schematic configuration of pixel circuits of some pixels among all the pixels of the display device of Fig. 3. In Fig. 4, for convenience of explanation, among the plurality of pixel circuits of row n, row m, Only the pixel circuits Pxodd (1,1) to Pxeven (1,6) and Pxodd (2,1) to Pxeven (2,6), which are pixel circuits of two rows and six columns from the upper left corner.

4, the odd-numbered column pixel circuits Pxodd (1,1 to n, 1) in the pixel circuit Px (i, j) of the present embodiment are respectively connected to the organic EL elements 101odd and two And the even-numbered column circuits Pxeven (1 to 2, n, 2) are provided with the organic EL element 101even and two transistors (the transistors T11odd and T12odd) and the capacitor Codd A switching transistor T11even, a driving transistor T12even, and a capacitor Ceven.

Likewise, the odd-numbered column pixel circuits (Pxodd (1,3 to n, 3)) in the subsequent pair of pixel circuit rows are connected to the organic EL element 101odd and two transistors (the switching transistor T11odd and the driving transistor T12odd) Numbered column pixel circuits Pxeven (1,4 to n, 4) are provided with an organic EL element 101even, two transistors (switching transistor T11even and a driving transistor T12even), and a capacitor Codd Ceven).

Here, the organic EL element 101odd and the organic EL element 101even, the capacitor Codd and the capacitor Ceven are organic EL elements and capacitors having the same configuration, respectively, and the driving transistor T12odd and the driving transistor T12even are transistors of the same type and capacitors Codd and Ceven are capacitors connected between the gate and drain of the transistors T12odd and T12even, respectively.

The switching transistor T11odd and the switching transistor T11even are also of the same type. In the present embodiment, the TFT is formed of an n-channel FET (Field Effect Transistor).

The organic EL elements 101odd and 101even are display elements having a structure in which an organic EL layer composed of a pixel electrode (anode electrode), a single or plural carrier transport layers, and the like and a counter electrode are sequentially layered, and the pixel electrode The anode voltage VDD of the anode potential is applied and the cathode voltage Vss of the cathode potential is applied to the counter electrode (cathode electrode).

Each of the transistors T11odd, T11even, T12odd and T12even has a drain, a source and a gate, a semiconductor layer is provided between the drain and the source, a predetermined bias voltage is applied between the drain and the source, A channel is formed in the semiconductor layer, and this channel becomes a current path between the drain and the source.

The transistor T11odd of the odd column pixel circuit Pxodd (i, j) is a switching transistor for applying a gradation signal Vdata representing the gradation of the image data Data to one end of the capacitor Codd, As well as an n-channel transistor.

 The sources of the switching transistors T11odd of the odd-numbered column pixel circuits Pxodd (i, j) are respectively connected to the gate of the driving transistor T12odd and one end of the capacitor Codd, and the drains thereof are connected to the corresponding data lines Ldj, And the gates thereof are connected to the gate lines Lgiodd for the odd column pixel circuits, respectively.

The transistor T11even of the even column pixel circuit Pxeven (i, j + 1) is also a switching transistor for applying a gradation signal Vdata indicating the gradation of the image data Data to one end of the capacitor Ceven Channel transistors, the sources of which are connected to the gate of the driving transistor T12odd and one end of the capacitor Codd, the drains of which are connected to the corresponding data lines Ldj, Are connected to the gate lines Lgieven for the even column pixel circuits, respectively.

When the high level signals are sequentially output to the gate lines Lg1odd, Lg2odd, ... Lgnodd for the odd column pixel circuits, the respective switching transistors T11odd of the odd column pixel circuits Pxodd (i, j) are turned on And outputs the gradation signal Vdata inputted to the data line Ldj to the gate of the driving transistor T12odd and one end of the capacitor Codd.

When the high level signals are sequentially output to the gate lines Lg1even, Lg2even, ..., Lgneven for the respective even-numbered circuits, the respective switching transistors T11even of the even-numbered column circuits Pxeven (i, j + And outputs the gradation signal Vdata inputted to the data line Ldj to the gate of the driving transistor T12even and one end of the capacitor Ceven.

The driving transistors T12odd and T12even control the amount of current of the current based on the gradation signals Vdata while controlling the organic EL elements 101odd and the even column pixel circuits Pxeven (i, j) of the odd column pixel circuits Pxodd i, j + 1), the gate of which is connected to the source of the switching transistors T11odd and T11even and the one end of the capacitors Codd and Ceven, respectively, and the drain thereof is connected to the anode power source Terminal VDD and the capacitors Codd and Ceven, respectively, and the sources are connected to the anodes of the organic EL elements 101odd and 101even, respectively.

3, the gate driver 12 of the present embodiment controls the gate driver 12 to select the pixel circuits on a row-by-row basis. The gate driver 12 outputs the output signals OUT ( 1) to (n) are sequentially output to the gate lines Lg1odd to Lgnodd for odd-numbered column circuits and the gate lines for the even-numbered column circuits Lg1even to Lgneven, respectively.

The data driver 14 is a driver for writing the gradation signal Vdata of the display signal based on the pixel data Data supplied to the capacitors Codd and Ceven of each pixel circuit Px (i, j) Generates the gradation signals Vdata in units of rows in accordance with the image data Data supplied from the controller 15 and supplies the generated gradation signals Vdata to the gate drivers 12 through the data lines Ld1 to Ldm / To the pixel circuit of the selected row.

The controller 15 controls the gate driver 12, the anode driver 13 and the data driver 14 and includes a central processing unit (CPU), a read only memory (ROM), a random access memory (RAM) , The start signal is supplied to the gate driver 12 with the clock signal being output to the gate driver 12 so that the gate driver 12 starts to operate and the end signal as the reset signal is supplied to the gate driver 12 The operation of the gate driver 12 is stopped.

The controller 15 supplies a start signal, image data (Data), a clock signal, and the like to the data driver 14.

The anode driver 13 is connected to the driving transistors T12odd and T12even of the pixel circuit Px (i, j) via the anode line Lai under the control of the controller 15, Level is supplied to the driving transistors T12odd and T12even of the pixel circuit Px (i, j) and the operation is started by the start signal from the controller 15 and supplied from the controller 15 Lt; / RTI >

The cathode voltage Vss of the organic EL elements 101odd and 101even is set to 0 V and the voltage VDD of the High level supplied from the anode driver 13 is supplied to the pixel circuits Is set to, for example, +15 V and the voltage of the Low level is set to 0 V or less. The voltage of the organic EL element 101odd 101even of the pixel Px (i, j) However, the cathode voltage Vss and the anode voltage VDD of the organic EL elements 101odd and 101even are not limited to the above values and the cathode voltage Vss and the anode voltage Vdd may be changed according to the characteristics of the organic EL elements 101odd and 101even. (VDD) can be appropriately set.

Next, the operation of the display apparatus 10 of the present embodiment will be described. 5 is a timing chart showing the driving timings of the display device 10 according to the preferred embodiment of the present invention.

First, the characteristics of the row selection signal applied from the gate driver 12 to each pixel circuit through the gate line will be briefly described.

As described above, in the present embodiment, a pair of pixel circuit columns formed by adjacent odd column pixel circuits (Pxodd (i, j)) and even column pixel circuits (Pxeven (i, j + 1) And the gate lines for applying the row selection signals to the odd column pixel circuits Pxodd (i, j) and the even column pixel circuits Pxeven (i, j + 1) are different from each other, 12 to the respective pixel circuits is also different from the conventional method.

5, the gate driver 12 of the present embodiment divides one pulse period of a row selection signal for row selection into a first half pulse period and a second half pulse period, During the / 2 pulse period, a high-level row selection signal is applied to the odd-numbered column circuit gate line Lgiodd, and in the latter half pulse period, the even-numbered column circuit gate line Lgieven receives a high- To sequentially perform row selection.

4 and 5, first, under the control of the controller 15, the gate driver 12 supplies the odd-numbered column pixel circuits (also referred to as " The row selection signal of the first half pulse period is applied to Pxodd (1,1), Pxodd (1,3), ... Pxodd (1, m-1).

(1, m-1)) of the odd-numbered column circuits (Pxodd (1,1), Pxodd (1,3), ... Pxodd The odd column pixel circuits Pxodd (1, 1), Pxodd (1, 3), ... Pxodd (1, m-1) are selected.

Then, in the second half pulse period, the gate driver 12 supplies the even-numbered pixel circuits Pxeven (1, 2), Pxeven (1, 4), Pxeven ..., Pxeven (1, m)) are applied to the even-numbered column circuits Pxeven (1, m) Each switching transistor T11even is turned on and the even column pixel circuits Pxeven (1, 2), Pxeven (1, 4), ... Pxeven (1, m) are selected.

In this way, odd column pixel circuits (Pxodd (1,1), Pxodd (1,3), ... Pxodd (1, m-1) 1) is selected, the data driver 14 supplies the odd-numbered column pixel circuits Pxodd (1,1 to 1, m-1) through the data lines Ld1, Ld2, ..., Ldm / (1, 1), Pxodd (1, 3), ..., Pxodd (1), and Pxodd (Vdata) is written to each capacitor (Codd) of each of the pixels (1, m, 1, m-1) through each transistor (T11odd).

Next, by using the high level row selection signal of the second half pulse period, each switching transistor (Pxeven (1, m)) of the even column pixel circuits (Pxeven (1, 2), Pxeven (1, m) are selected and the data driver 14 selects the even-numbered column circuits Pxeven (1, 2), Pxeven (1, m) of the row selection signal to the even-numbered column circuits Pxeven (1, 2), Pxeven (1, 4), ..., Pxeven (1, m) in the first row via the data lines Ld1, Ld2, ..., Ldm / (1, m), Pxeven (1, 4), ..., Pxeven (1, m) are applied to the even- ) Is written into each of the capacitors Ceven through the transistor T11even.

In the same way, the gate driver 12 sequentially drives the second row, the third row, ... , The odd-numbered column pixel circuits in the n-th row and the even-numbered column circuits are sequentially selected. In this period, the data driver 14 outputs the gradation signals Vdata (Vdata) based on the image data supplied during each pulse period of the row selection signal ) To the selected pixel circuits, respectively, thereby sequentially writing the gray-scale signals Vdata into the respective capacitors Codd of the selected pixel circuits.

When the sequential writing operation is completed in this manner, the controller 15 controls the anode driver 13 to turn on the anode voltage VDD of the high level through the anode line Lai to the pixel circuits Px the transistors T12odd and T12even of the respective pixel circuits Px (i, j) are supplied with the voltages held by the capacitors Codd and Ceven as gate voltages Vgs, By supplying a current corresponding to the voltage Vgs to the organic EL elements 101odd and 101even, the organic EL elements 101odd and 101even emit light with a luminance corresponding to the current value of this current.

As described above, according to the present embodiment, in the display device 10, a pair of pixel circuit columns constituted by pixel circuits of two columns of odd-numbered columns and even-numbered columns which are adjacent to each other among a plurality of pixel circuits constituting the display portion, , The number of data lines can be reduced to half, so that the number of intersections at which the data lines intersect the lines supplying different signals is reduced. The RC delay (RC delay) of the row selection signal supplied from the gate line is reduced, and the voltage drop (IR drop) generated in the gate line is also greatly reduced .

In addition, since the number of data lines is reduced to half compared with the conventional one, the aperture ratio of the display device increases, thereby increasing the resolution of the display device.

In this embodiment, the even-numbered column circuit of any one of the plurality of pairs of pixel circuit columns and the odd-numbered column circuit of the next pair of pixel circuit columns are connected to the respective anode- Since the anode line to which the voltage is applied is shared, the same effect as the effect of decreasing the data line is obtained.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above embodiments. Various changes and modifications within the scope of the present invention are possible.

In the above embodiment, the switching transistors of the odd-number column pixel circuit Pxodd (i, j) and the even-number column pixel circuit Pxeven (i, j + 1) The configuration of the switching transistor is not limited to this, and contrary to the present embodiment, a p-channel type FET may be used. In this case, however, the polarity of the row selection signal supplied from the gate driver 12 through each gate line may be reversed from that of the present embodiment, and this is obvious in the field of the present invention, Is omitted.

In the above embodiment, the capacitors Codd and Ceven of the pixel circuits are connected between the gate and the drain of the driving transistors T12odd and T12even. However, the positions of the capacitors Codd and Ceven are not limited thereto And the capacitors Codd and Ceven may be connected between the gate and the source of the transistors T12odd and T12even, respectively.

10 display device
12 gate driver
13 Anode driver
14 data driver
15 controller
The Px (i, j) pixel circuit
Pxodd (i, j) odd column pixel circuit
Pxeven (i, j + 1) even column pixel circuits
Lg1odd, Lg2odd, ... , Lgnodd Gate lines for odd column pixel circuits
Lg1even, Lg2even, ... , Lgneven gate line for even column pixel circuit
Ld1, Ld2, ... , An Ldm / 2 data line
La1, La2, ... , Lan / 2 + 1 anode line
T11 switching transistor
T12 driving transistor
C capacitor
101 organic EL device

Claims (7)

a display device having a plurality of pixel circuits of n rows and m columns (m and n are natural numbers respectively)
Wherein the plurality of pixel circuits of the n-th row and m-th column are composed of a plurality of pairs of pixel circuit columns each of which is a pair of pixel circuit columns composed of pixel circuits of two columns of odd-numbered columns and even-
Wherein the pair of pixel circuit columns share a data line for applying a gray level signal,
And a gate line for applying a row selection signal to each of a plurality of pixel circuits of the mth row and the nth column is composed of two gate lines: a gate line for an odd column pixel circuit and a gate line for an even column pixel circuit. a display device having a plurality of pixel circuits of n rows and m columns (m and n are natural numbers respectively)
A plurality of pairs of pixel circuit columns each including a pair of pixel circuit columns formed by pixel circuits of two columns of odd-numbered columns and even-numbered columns adjacent to each other in the column direction,
A gate line for an odd-numbered column circuit for applying row selection signals to the odd-numbered column pixel circuits on a row-by-row basis,
A gate line for an even-numbered column circuit for applying a row selection signal to each of the even-numbered column circuits on a row-
And a data line for applying a gray-scale signal in units of the pair of pixel circuit columns. The method according to claim 1 or 2,
Numbered column pixel circuits of the pair of pixel circuit columns and odd-numbered column pixel circuits of another pair of pixel circuit columns adjacent to the pair of pixel circuit columns share an anode line for applying an anode voltage to each pixel circuit. The method according to claim 1 or 2,
Each of the plurality of pixel circuits includes:
A switching transistor which is driven by the row selection signal to apply a gradation signal indicative of the gradation of the image data to one end of the capacitor,
A driving transistor driven by the switching transistor to supply a current based on the gray-scale signal to the organic EL element,
A capacitor for charging the gray-scale signal,
And an organic EL element which emits light with a luminance corresponding to an amount of the current of the current,
And the switching transistors of the odd column pixel circuits are connected to the gate lines for the odd column pixel circuits, and the switching transistors of the even column pixel circuits are connected to the gate lines for the even column pixel circuits. The method of claim 4,
And the switching transistors of the odd column pixel circuits and the even column pixel circuits are n-channel FETs. The method of claim 4,
And the switching transistors of the odd column pixel circuits and the even column pixel circuits are p-channel FETs. The method of claim 4,
A switching transistor of the odd-number column pixel circuit has a gate connected to the gate line for the odd-numbered column pixel circuit, a source and a drain form a first current path between the data line and the gate of the driving transistor and one end of the capacitor ,
The switching transistor of the even column pixel circuit has a gate connected to the gate line for the even column pixel circuit and a source and a drain form a first current path between the data line and the gate of the driving transistor and one end of the capacitor ,
Wherein the driving transistor has a gate connected to one end of the first current path and one end of the capacitor, and a source and a drain form a second current path between the other end of the capacitor and the anode power supply terminal and the organic EL element.

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