KR20140137713A - Organinc light emitting display device and manufacturing method for the same - Google Patents

Abstract

According to an aspect of the present invention, there is provided an organic light emitting display comprising: an organic light emitting element in which a pixel electrode, an intermediate layer including a light emitting layer, and a cathode electrode are sequentially stacked; A cathode contact portion including an upper electrode in contact with the cathode electrode and a lower electrode formed in the same layer as the pixel electrode and in contact with the upper electrode; And at least three or more cathode contact portions are formed in a direction crossing the wiring, and the wiring is disposed between the cathode contact portions, to provide.

Description

[0001] The present invention relates to an organic light emitting display device and a manufacturing method thereof,

The present invention relates to an organic light emitting display and a method of manufacturing the same.

There is an increasing trend in global signal lines supplied from pixel circuits of large-sized current-emitting organic light emitting display devices.

The cathode electrode applies the same voltage to all the pixels as the common electrode, and receives the cathode voltage from the external terminal through the cathode contact portion. At this time, the cathode contact portion has a structure in which the source / drain electrode forming material exposed to the pixel defining layer and the cathode electrode are in contact with each other.

The wiring is insulated by an interlayer insulating film. The interlayer insulating film is in contact with the cathode electrode extending from the cathode contact portion. Therefore, when an external force is concentrated on the wiring, a short circuit may occur between the cathode electrode and the wiring.

The present invention provides an organic light emitting display device capable of preventing a short circuit between a cathode electrode and a wiring.

According to an aspect of the present invention, there is provided an organic light emitting display comprising: an organic light emitting element in which a pixel electrode, an intermediate layer including a light emitting layer, and a cathode electrode are sequentially stacked; A cathode contact portion including an upper electrode in contact with the cathode electrode and a lower electrode formed in the same layer as the pixel electrode and in contact with the upper electrode; And at least three or more cathode contact portions are formed in a direction crossing the wiring, and the wiring is disposed between the cathode contact portions, to provide.

The lower electrode includes a first electrode formed on the same layer as the pixel electrode; And a second electrode contacting the first electrode and the upper electrode.

Wherein the first electrode and the second electrode comprise a transparent conductive metal oxide and the second electrode and the upper electrode are made of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Mo, Ti, W, MoW, Cu, and La.

A gate electrode including an active layer, a bottom gate electrode formed on the same layer as the first electrode, and a top gate electrode formed on the same layer as the second electrode, a source electrode formed on the same layer as the upper electrode and in contact with the active layer, And a thin film transistor including a drain electrode.

And a capacitor including a lower capacitor electrode formed on the same layer as the active layer and an upper capacitor electrode formed on the same layer as the first electrode.

An interlayer insulating film disposed between the lower electrode and the upper electrode; And a pixel defining layer disposed on the interlayer insulating layer in contact with an edge region of the upper electrode.

A first wiring formed on the same layer as the pixel electrode; And a second wiring disposed on the first wiring and in contact with the interlayer insulating film.

The upper electrode may contact the lower electrode through a contact hole formed in the interlayer insulating film.

The interlayer insulating film may include an inorganic insulating material.

The pixel defining layer may include an organic insulating material.

The cathode contact portion may be formed in a non-display region.

The cathode contact portion may be formed in a slit shape in a direction crossing the wiring.

The wirings may be disposed one by one between the cathode contact portions.

The wiring may be a global signal wiring.

According to an aspect of the present invention, a first electrode pattern for forming a pixel electrode, a second electrode pattern for forming a lower electrode, and a third electrode pattern for forming a wiring are formed, respectively, Forming at least three or more electrode patterns in a direction crossing the electrode pattern and arranging the third electrode pattern between the second electrode patterns; Forming an interlayer insulating film so as to cover the wiring and having an opening exposing the upper surface of the first electrode pattern and a contact hole exposing the upper surface of the second electrode pattern; Forming the pixel electrode from the first electrode pattern and forming an upper electrode in contact with the lower electrode through the contact hole; Forming a pixel defining layer exposing a portion of the pixel electrode and the upper electrode; And forming a cathode electrode in the form of a front electrode on the pixel defining layer in contact with the upper electrode.

The lower electrode may be formed in a non-display region.

The lower electrode may be formed in a slit shape in a direction crossing the wiring, and the wiring may be disposed one by one between the lower electrodes.

The wiring may be a global signal wiring.

The interlayer insulating film may include an inorganic insulating material.

The pixel defining layer may include an organic insulating material.

According to an aspect of the present invention, it is possible to prevent a short circuit between the cathode electrode and the wiring.

1 is a plan view schematically showing the structure of an organic light emitting diode display 1 according to an embodiment of the present invention.
2 is a cross-sectional view taken along the line II-II in FIG.
FIGS. 3 to 9 are cross-sectional views schematically showing a manufacturing process of the organic light emitting diode display 1 shown in FIG.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view schematically showing the structure of an organic light emitting diode display 1 according to an embodiment of the present invention.

The OLED display 1 includes a display region 110 on which a plurality of pixels are arranged and a non-display region 120 formed outside the display region 110 on a substrate 100.

The substrate 100 may be a crystalline silicon (LTPS) substrate, a glass substrate, a plastic substrate, or the like.

In the display area 110, pixels which are basic units of image representation are arranged in a matrix form, and wirings electrically connected to each pixel are formed. The pixel may include a pixel circuit including at least one thin film transistor (TFT) and a capacitor Cst and an organic light emitting element EL. The organic light emitting device EL has a structure in which a pixel electrode connected to a thin film transistor (TFT), an organic light emitting layer, and a cathode electrode in the form of a front electrode are stacked. A cathode voltage is applied to each pixel through the cathode electrode.

The non-display region 120 may include a cathode bus region 150 electrically connected to a cathode electrode of the display region 110 through a cathode contact portion (CCNT). The cathode bus region 150 provides a cathode voltage applied from the outside through the cathode contact portion CCNT to each pixel. One or more cathode bus regions 150 may be formed on at least one side of the non-display region 120. One or more cathode contact portions (CCNT) may be formed in the cathode bus region 150.

The embodiment of the present invention is characterized in that the cathode contact portion CCNT is formed in the non-display region 120 so that the cathode bus line and the cathode electrode are electrically in direct contact with each other at the outer portion of the display region 110, Thereby facilitating electrical contact.

The wiring 73 may be connected to the display region 110 through the cathode bus region 150. A current or a voltage may be transferred to the thin film transistor TFT or the organic light emitting element EL located in the display region 110 through the wiring 73. [ The wiring 73 may be a global signal wiring. The global signal wiring can be formed of the same material as the gate of the thin film transistor TFT and all the pixels can be initialized at a time in the pixel structure SEAV, ASEAV, SSE for simultaneous light emission, threshold voltage (Vth) compensation, And the like can be controlled.

The substrate 100 may be bonded to an encapsulating substrate (not shown) facing the substrate 100 by a sealing member (not shown) formed in the non-display region 120. In addition, moisture from the outside can be blocked by a getter (not shown) formed in the non-display area 120.

2 is a cross-sectional view taken along the line II-II in FIG.

2, the OLED display 1 includes a light emitting region 20, a transistor region 30, and a storage region 40 in a display region 110, and a non-display region 120 And a cathode bus region 150.

The light emitting region 20 is provided with an organic light emitting device EL. The organic light emitting device EL includes a pixel electrode 21 electrically connected to one of the source / drain electrodes 37/39 of the thin film transistor TFT, a cathode electrode 25 formed to face the pixel electrode 21, And an intermediate layer 23 interposed between them. The pixel electrode 21 is formed of a transparent conductive metal oxide and may be formed of the same material as the lower gate electrode 33 of the thin film transistor TFT.

The transistor region 30 is provided with a thin film transistor (TFT) as a driving element. The thin film transistor TFT is composed of the active layer 31, the gate electrode 35 and the source / drain electrodes 37 and 39. The gate electrode 35 is composed of a lower gate electrode 33 and an upper gate electrode 34 on the lower gate electrode 33. The lower gate electrode 33 may be formed of a transparent conductive metal oxide. Between the gate electrode 35 and the active layer 31, a first insulating layer 102, which is a gate insulating film for insulating therebetween, is interposed. In addition, source / drain regions 31s / 31d doped with a high concentration of impurities are formed on both edges of the active layer 31, and these are connected to the source / drain electrodes 37/39, respectively. And between the source / drain regions 31s / 31d function as a channel region 31c.

The storage region 40 is provided with a capacitor Cst. The capacitor Cst includes a lower capacitor electrode 41 and an upper capacitor electrode 43, and a first insulating layer 102 is interposed therebetween. Here, the lower capacitor electrode 41 may be formed in the same layer as the active layer 31 of the thin film transistor TFT. The lower capacitor electrode 41 may be made of a semiconductor material and is doped with impurities to improve electrical conductivity. The upper capacitor electrode 43 may be formed on the same layer as the lower gate electrode 33 of the thin film transistor TFT and the pixel electrode 21 of the organic light emitting element EL.

The cathode bus region 150 includes a cathode contact portion (CCNT) to which the lower electrode 51 and the cathode electrode 25 are electrically connected. The upper electrode 55 is in direct contact with the cathode electrode 25 and is electrically connected. A second electrode 54 directly contacting the first electrode 53 but not directly contacting the cathode electrode 25 is formed on the first electrode 53. [ An upper electrode 55 directly contacting the cathode electrode 25 but not directly contacting the first electrode 53 is formed on the second electrode 54. The first electrode 53 is formed on the same layer as the lower gate electrode 33 of the thin film transistor TFT, the pixel electrode 21 of the organic light emitting element EL and the upper capacitor electrode 43 of the capacitor Cst . The second electrode 54 may be formed on the same layer as the upper gate electrode 34 of the thin film transistor TFT. The upper electrode 55 may be formed on the same layer as the source / drain electrode 37/39 of the thin film transistor (TFT).

The cathode bus region 150 includes a wiring 73 that is insulated from the cathode contact portion (CCNT). The wiring 73 may be disposed between the cathode contact portions CCNT. The wiring 73 is disposed on the first wiring 71 and the first wiring 71 formed on the same layer as the pixel electrode 21 or the first electrode 53 and is in contact with the second insulating layer 105 And a second wiring 72 for connecting the first and second wirings.

At least three or more cathode contact portions CCNT may be formed in a direction intersecting with the wiring 73. At this time, the wiring 73 may be disposed between the cathode contact portions (CCNT). The cathode contact portion CCNT may be formed in a slit shape in a direction crossing the wiring 73 and the wiring 73 may be disposed one by one between the cathode contact portions CCNT. By locating the cathode contact portion CCNT and the wiring 73 as described above, the localized force F, which can cause a short circuit between the cathode electrode 25 and the wiring 73, is dispersed, . As a result, the vertical short failure between the cathode electrode 25 and the wiring 73 can be prevented, and the reliability of the product can be improved.

FIGS. 3 to 9 are cross-sectional views schematically showing a manufacturing process of the organic light emitting diode display 1 shown in FIG. Hereinafter, a manufacturing process of the OLED display 1 shown in FIG. 2 will be schematically described.

First, as shown in FIG. 3, an auxiliary layer 101 is formed on the substrate 100. In detail, the substrate 100 may be formed of a transparent glass material having SiO2 as a main component. The substrate 100 is not limited thereto, and a substrate made of various materials such as a transparent plastic material or a metal material can be used.

An auxiliary layer 101 such as a barrier layer, a blocking layer, and / or a buffer layer may be provided on the upper surface of the substrate 100 in order to prevent diffusion of impurity ions, prevent penetration of moisture or outside air, have. The auxiliary layer 101 may be formed by various deposition methods such as plasma enhanced chemical vapor deposition (PECVD), atmospheric pressure CVD (APCVD), and low pressure CVD (LPCVD) using SiO2 and / have.

Next, an active layer 31 of a thin film transistor (TFT) and a lower capacitor electrode 41 are formed on the auxiliary layer 101. The active layer 31 and the lower capacitor electrode 41 may be formed by patterning the polycrystalline silicon layer. The active layer 31 and the lower capacitor electrode 41 may include a semiconductor and may include ionic impurities by doping. The active layer 31 and the lower capacitor electrode 41 may be formed of an oxide semiconductor. Although the active layer 31 and the lower capacitor electrode 41 are separately formed in this embodiment, the active layer 31 and the lower capacitor electrode 41 may be integrally formed.

A first insulating layer 102, a first conductive layer 103 and a second conductive layer 104 are sequentially formed on the entire surface of the substrate 100 on which the active layer 31 and the lower capacitor electrode 41 are formed .

The first insulating layer 102 may be formed by depositing an inorganic insulating film such as SiNx or SiOx by a method such as PECVD, APCVD, or LPCVD. The first insulating layer 102 is interposed between the active layer 31 of the thin film transistor TFT and the gate electrode 350 to serve as a gate insulating film of the thin film transistor TFT, And is interposed between the electrodes 41 to serve as a dielectric layer of the capacitor Cst.

The first conductive layer 103 may include one or more materials selected from transparent materials such as ITO, IZO, ZnO, or In2O3. The first conductive layer 103 may be patterned into the pixel electrode 21, the bottom gate electrode 33, the upper capacitor electrode 43 and the first electrode 53 of the lower electrode 51. [

The second conductive layer 104 may include one or more materials selected from Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, MoW, can do. Preferably, the second conductive layer 104 may be formed of a Mo-Al-Mo or Mo-AlNiLa-Mo three-layer structure. The second conductive layer 104 may later be patterned into the upper gate electrode 34 and the second electrode 54 of the lower electrode 51.

However, the present invention is not limited to the above-described materials, and the first conductive layer 103 includes a material having better corrosion resistance than the second conductive layer 104, and the second conductive layer 104 includes a first conductive layer The present invention satisfies one embodiment of the present invention if it includes a material having a resistance lower than that of the current sensor 103 and a current flows well.

4, the first conductive layer 103 and the second conductive layer 104 are patterned to form a gate electrode 35 and a first electrode pattern (not shown) on the first substrate 10, 20, a second electrode pattern 50, a third electrode pattern 70, and a fourth electrode pattern 40 are formed.

A gate electrode 35 is formed on the active layer 31 in the transistor region 30 and the gate electrode 35 is formed on the lower gate electrode 33 formed as a part of the first conductive layer 103 and the second conductive layer 104 And a top gate electrode 34 formed as a part of the upper gate electrode 34.

The gate electrode 35 is formed so as to correspond to the center of the active layer 31 and the n-type or p-type impurity is doped into the active layer 31 using the gate electrode 35 as a self- Source / drain regions 21s / 21d and a channel region 21c therebetween are formed at the edges of the active layer 31 corresponding to both sides of the gate electrode 35. [ Here, the impurity may be a boron (B) ion or a phosphorus (P) ion.

A first electrode pattern 20 for forming the pixel electrode 21 is formed in the light emitting region 20 and a fourth electrode pattern 40 for forming the upper capacitor electrode 43 is formed in the storage region 40 Is formed on the lower capacitor electrode 41. [ At least three second electrode patterns 50 for forming the first and second electrodes 53 and 54 are formed in the cathode bus region 150 and at least three second electrode patterns 50 are formed between the second electrode patterns 50 A third electrode pattern 70 for forming the wiring 73 including the first wiring 71 and the second wiring 72 is formed on the second wiring pattern 71. [

The wiring 73 formed by the third electrode pattern 70 may be a global signal wiring. The global signal wiring can perform functions such as initializing all the pixels at one time, compensating the threshold voltage (Vth), controlling light emission, etc. in the pixel structure (SEAV, ASEAV, SSE)

At least three or more second electrode patterns 50 for forming the lower electrodes 51 may be formed in a direction intersecting the third electrode patterns 70 for forming the wirings 73. At this time, the third electrode pattern 70 may be disposed between the second electrode patterns 50. The second electrode patterns 50 may be separated in a slit shape in a direction crossing the second electrode patterns 50 and the third electrode patterns 70 may be disposed one by one between the second electrode patterns 50 have. The second electrode pattern 50 and the third electrode pattern 70 are arranged as described above so that at least three or more cathode contact portions CCNT (see FIG. 2) can be formed in the direction intersecting the wiring 73 . At this time, the wiring 73 may be disposed between the cathode contact portions (CCNTs, see FIG. 2). 2) may be formed in a slit shape in a direction crossing the wiring 73 and the wiring 73 may be disposed one by one between the cathode contact portions (CCNTs, see FIG. 2) have. 2) capable of causing a short circuit between the cathode electrode 25 (see FIG. 2) and the wiring 73 by arranging the cathode contact portion CCNT (see FIG. 2) and the wiring 73 as described above, ) Can be prevented from being vertically short-circuited. As a result, vertical short failure between the cathode electrode 25 (see FIG. 2) and the wiring 73 can be prevented, and the reliability of the product can be improved.

Next, as shown in FIG. 5, a second insulating layer 105 is deposited on the entire surface of the substrate 100 on which the gate electrode 35 is formed.

The second insulating layer 105 may be formed of an inorganic insulating material such as the first insulating layer 102 described above. The second insulating layer 105 serves as an interlayer insulating film between the gate electrode 35 and the source / drain electrode 37/39 of the thin film transistor TFT. The second insulating layer 105 also serves to insulate the wiring 73. Meanwhile, the second insulating layer 105 may be formed of at least one organic insulating material selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin, as well as the inorganic insulating material as described above , An organic insulating material and an inorganic insulating material may alternatively be formed.

6, the second insulating layer 105 is patterned to form openings H1 and H2 for exposing the first electrode pattern 20, openings H3 and H4 for exposing the fourth electrode pattern 40, A plurality of contact holes H3 and H4 exposing a part of the source / drain regions 31s and 31d of the active layer 31 and a plurality of contact holes H3 and H4 exposing the top surface of the second electrode pattern 50, (H6).

The first opening H1 and the second opening H2 expose at least a part of the second conductive layer 104 constituting the upper portion of the first electrode pattern 20. The contact holes H3 and H4 expose portions of the source / drain regions 31s / 31d, respectively. The fifth opening H5 exposes at least a part of the second conductive layer 104 constituting the upper portion of the fourth electrode pattern 40. The contact holes H6 expose at least a part of the second conductive layer 104 constituting the upper portion of the second electrode pattern 50. [

Next, as shown in FIG. 7, a third conductive layer 106 is deposited over the entire surface of the substrate 100 so as to cover the second insulating layer 105.

The third conductive layer 106 may be formed of the same conductive material as the first or second conductive layer 103 or 104, but may be formed of various conductive materials. In addition, the conductive material is deposited to a sufficient thickness to fill between the contact holes H3, H4, and H6 and the openings H1, H2, and H5 described above.

Next, as shown in FIG. 8, the third conductive layer 106 is patterned to form a source / drain electrode 37/39 and an upper electrode 55.

The source / drain electrodes 37/39 are electrically connected to the source / drain regions 31s / 31d of the active layer 31 through the contact holes H3 and H4. One of the source / drain electrodes 37/39 (the drain electrode 39 in this embodiment) has a second opening H2 in the edge region of the second conductive layer 104 above the pixel electrode 21 And the pixel electrode 21 is formed to be electrically connected to the pixel electrode 21.

The upper electrode 55 directly contacts the second electrode 54 of the lower electrode 51 through the contact holes H6.

On the other hand, the source / drain electrodes 37/39 are formed and the pixel electrodes 21 and the upper capacitor electrodes 43 are formed. However, the present invention is not limited to this, and the pixel electrode 21 and the upper capacitor electrode 43 may be formed by further etching after the source / drain electrodes 37/39 are formed. The upper second conductive layer 104 exposed by the first opening H1 is removed from the first electrode pattern (see 20 in FIG. 8) to form the pixel electrode 21. Next, as shown in FIG. Then, the upper second conductive layer 104 exposed by the fifth opening H5 is removed from the second electrode pattern (see 40 in FIG. 8) to form the upper capacitor electrode 43.

Therefore, the pixel electrode 21, the bottom gate electrode 33, the upper capacitor electrode 43, and the first electrode 53 of the lower electrode 51 are formed of the same material in the same layer. The upper gate electrode 34 and the second electrode 54 of the lower electrode 51 are formed of the same material in the same layer.

Here, the n-type or p-type impurity may be implanted through the opening exposing the upper portion of the upper capacitor electrode 43 to dope the lower capacitor electrode 41. The impurity implanted in doping may be the same as or different from that used in doping the active layer 31. [

Next, as shown in FIG. 9, a third insulating layer 107 is formed on the substrate 100.

In detail, a third insulating layer 107 is formed on the entire surface of the substrate 100 on which the pixel electrode 21, the source / drain electrodes 37/39, the upper capacitor electrode 43, the lower electrode 51 and the wiring 73 are formed. / RTI > At this time, the third insulating layer 107 may be formed by spin coating or the like with one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin. The third insulating layer 107 may be formed of an inorganic insulating material selected from SiO2, SiNx, Al2O3, CuOx, Tb4O7, Y2O3, Nb2O5, Pr2O3 and the like as well as the organic insulating material. In addition, the third insulating layer 107 may be formed in a multi-layer structure in which an organic insulating material and an inorganic insulating material are alternated. The third insulating layer 107 is patterned to form a ninth opening H9 for exposing a part of the pixel electrode 21 and a tenth opening H10 for exposing a part of the upper electrode 55. [ The third insulating layer 107 functions as a pixel defining layer (PDL) for defining pixels. The third insulating layer 107 is in contact with the edge regions of the pixel electrode 21 and the upper electrode 55.

2, the intermediate layer 23 and the cathode electrode 25 including the organic light emitting layer are formed at the ninth opening H9 that exposes the pixel electrode 21. Next, as shown in FIG.

The intermediate layer 23 includes an emissive layer (EML), a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL) And an electron injection layer (EIL) may be stacked in a single or a composite structure. The organic light emitting layer may be formed of a low molecular weight or high molecular organic material. When the organic light emitting layer emits red, green, and blue light, the organic light emitting layer may be patterned into a red light emitting layer, a green light emitting layer, and a blue light emitting layer, respectively. On the other hand, when the organic light emitting layer emits white light, the organic light emitting layer may have a multilayer structure in which a red light emitting layer, a green light emitting layer, and a blue light emitting layer are laminated so as to emit white light, or may have a multilayer structure including a red light emitting material, May have a single layer structure.

The cathode electrode 25 may be deposited on the entire surface of the substrate 100 to form a common electrode. The cathode electrode 25 directly contacts the upper electrode 55 through the contact hole H10 in the cathode contact portion CCNT.

In the case of a bottom emission type in which an image is formed in the direction of the substrate 100 of the organic light emitting display device 1, the pixel electrode 21 becomes a transparent electrode and the cathode electrode 25 becomes a reflective electrode . The reflective electrode may be formed of a metal having a low work function, for example, Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca, LiF / Can be formed by depositing a thin film.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation and that those skilled in the art will recognize that various modifications and equivalent arrangements may be made therein. It will be possible. Accordingly, the true scope of protection of the present invention should be determined only by the appended claims.

21: pixel electrode 23: middle layer
25: cathode electrode 55: upper electrode
51: lower electrode 73: wiring
CCNT: Cathode contact part

Claims (20)

An organic light emitting element in which a pixel electrode, an intermediate layer including a light emitting layer, and a cathode electrode are sequentially stacked;
A cathode contact portion including an upper electrode in contact with the cathode electrode and a lower electrode formed in the same layer as the pixel electrode and in contact with the upper electrode; And
And a wiring formed on the same layer as the lower electrode,
Wherein at least three or more cathode contact portions are formed in a direction crossing the wiring, and the wiring is disposed between the cathode contact portions. The method according to claim 1,
The lower electrode includes a first electrode formed on the same layer as the pixel electrode; And
And a second electrode contacting the first electrode and the upper electrode. 3. The method of claim 2,
Wherein the pixel electrode and the first electrode comprise a transparent conductive metal oxide,
The second electrode and the upper electrode may be formed of one or more materials selected from Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, MoW, And the organic light emitting display device. 3. The method of claim 2,
A gate electrode including an active layer, a bottom gate electrode formed on the same layer as the first electrode, and a top gate electrode formed on the same layer as the second electrode, a source electrode formed in the same layer as the upper electrode and in contact with the active layer, And a thin film transistor including a source electrode and a drain electrode. 5. The method of claim 4,
And a capacitor including a lower capacitor electrode formed on the same layer as the active layer and an upper capacitor electrode formed on the same layer as the first electrode. The method according to claim 1,
An interlayer insulating film disposed between the lower electrode and the upper electrode; And
And a pixel defining layer in contact with an edge region of the upper electrode and disposed on the interlayer insulating layer. The method according to claim 6,
A first wiring formed on the same layer as the pixel electrode; And a second wiring disposed on the first wiring and in contact with the interlayer insulating film. The method according to claim 6,
Wherein the upper electrode is in contact with the lower electrode through a contact hole formed in the interlayer insulating film. The method according to claim 6,
Wherein the interlayer insulating film comprises an inorganic insulating material. The method according to claim 6,
Wherein the pixel defining layer comprises an organic insulating material. The method according to claim 1,
And the cathode contact portion is formed in a non-display region. The method according to claim 1,
Wherein the cathode contact portion is formed in a slit shape in a direction crossing the wiring. 13. The method of claim 12,
And the wires are disposed one by one between the cathode contact portions. The method according to claim 1,
Wherein the wiring is a global signal wiring. Forming a first electrode pattern for forming a pixel electrode, a second electrode pattern for forming a lower electrode, and a third electrode pattern for forming a wiring, wherein the second electrode pattern is formed to cross the third electrode pattern And arranging the third electrode pattern between the second electrode patterns;
Forming an interlayer insulating film so as to cover the wiring and having an opening exposing the upper surface of the first electrode pattern and a contact hole exposing the upper surface of the second electrode pattern;
Forming the pixel electrode from the first electrode pattern and forming an upper electrode in contact with the lower electrode through the contact hole;
Forming a pixel defining layer exposing a portion of the pixel electrode and the upper electrode; And
And forming a cathode electrode in the form of a front electrode on the pixel defining layer in contact with the upper electrode. 16. The method of claim 15,
And the lower electrode is formed in a non-display region. 16. The method of claim 15,
Wherein the lower electrode is formed in a slit shape in a direction crossing the wiring, and the wiring is disposed one by one between the lower electrodes. 16. The method of claim 15,
Wherein the wiring is a global signal wiring. 16. The method of claim 15,
Wherein the interlayer insulating film comprises an inorganic insulating material. 16. The method of claim 15,
Wherein the pixel defining layer comprises an organic insulating material.

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