KR20140110177A - Bifacial solar cell - Google Patents

Abstract

A double-sided light receiving solar cell according to the present invention includes: a semiconductor substrate containing an impurity of a first conductivity type; An emitter section located on a first side of the substrate and containing an impurity of a second conductivity type; A first dielectric layer located on a front surface of the emitter section and having a plurality of first openings; A back electrometer located on a back surface of the substrate and containing an impurity of the first conductivity type; A second dielectric layer located on a back surface of the rear surface electric field portion and having a plurality of second openings; A first electrode connected to the emitter portion exposed through the first opening; And a second electrode connected to the rear electric field portion exposed through the second opening, wherein the rear electric field portion includes an intrinsic amorphous silicon (ia-Si) layer contacting the semiconductor substrate and containing no impurity, An amorphous silicon (a-Si) layer of a first conductivity type and containing a first conductivity type impurity at a higher concentration than a semiconductor substrate, and a second conductivity type amorphous silicon (Mc-Si) layer of the first conductivity type containing impurities of a high concentration in the semiconductor substrate in comparison with the semiconductor substrate.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a double-

The present invention relates to a double-sided light receiving solar cell.

With the recent depletion of existing energy resources such as oil and coal, interest in alternative energy to replace them is increasing. Among them, solar cells produce electric energy from solar energy, and they are attracting attention because they have abundant energy resources and there is no problem about environmental pollution.

A typical solar cell includes a substrate and an emitter portion that forms a p-n junction with the substrate, and generates a current by using light incident through one side of the substrate.

Therefore, a conventional solar cell has a low current conversion efficiency because light is incident through only one side of the substrate. In recent years, a double-sided light receiving type solar cell has been developed in which light is incident on both sides of a substrate.

SUMMARY OF THE INVENTION The present invention provides a solar cell with improved efficiency.

A double-sided light receiving solar cell according to an embodiment of the present invention includes: a semiconductor substrate containing an impurity of a first conductivity type; An emitter section located on a first side of the substrate, the emitter section containing an impurity of a second conductivity type having opposite conductivity of the first conductivity type; A first dielectric layer located on a front surface of the emitter section and having a plurality of first openings; A back electrometer located on a back surface of the substrate and containing an impurity of the first conductivity type; A second dielectric layer located on a back surface of the rear surface electric field portion and having a plurality of second openings; A first electrode connected to the emitter portion exposed through the first opening; And a second electrode connected to the rear electric field portion exposed through the second opening, wherein the rear electric field portion includes an intrinsic amorphous silicon (ia-Si) layer contacting the semiconductor substrate and containing no impurity, An n-type amorphous silicon (a-Si) layer which is located on the back surface of the first conductivity type amorphous silicon layer and contains impurities of the first conductivity type at a higher concentration than the semiconductor substrate, And a microcrystalline silicon (mc-Si) layer of a first conductivity type containing a higher concentration than the semiconductor substrate.

The rear electric field portion is located on the entire rear surface of the substrate, and the interval between the plurality of openings formed in the second dielectric layer is formed to be 100 mu m to 500 mu m.

The first conductivity type may be n-type, and the second conductivity type may be p-type.

The entire back surface of the first electrode may be in direct contact with the emitter portion. The first electrode may include a plurality of first finger electrodes located on the front surface of the semiconductor substrate and extending in the first direction.

The first electrode may further include a plurality of first bus bar electrodes extending in a second direction orthogonal to the first direction. The first bus bar electrode is physically connected to the first finger electrode.

The first finger electrode and the first bus bar electrode may include a plating layer.

The entire front surface of the second electrode is in direct contact with the microcrystalline silicon layer of the first conductivity type.

The second electrode may include a plurality of second finger electrodes located on the rear surface of the semiconductor substrate and extending in the first direction. The second electrode may further include a plurality of second bus bar electrodes extending in a second direction. The second bus bar electrode is physically connected to the second finger electrode.

The second electrode, for example, the second finger electrode and the second bus bar electrode may comprise a plating layer.

The thickness of the amorphous silicon layer of the first conductivity type is formed larger than the thickness of the microcrystalline silicon layer of the first conductivity type and the thickness of the microcrystalline silicon layer of the first conductivity type is formed larger than the thickness of the intrinsic amorphous silicon layer desirable.

In one example, the intrinsic amorphous silicon layer is formed to a thickness of 1 nm to 5 nm, the first conductive type amorphous silicon layer is formed to a thickness of 10 nm to 30 nm, and the first conductive type microcrystalline silicon layer is formed of 5 Nm to 10 nm in thickness.

The second dielectric layer comprises a first rear dielectric layer and a second rear dielectric layer, wherein the first rear dielectric layer and the second rear dielectric layer each have a fixed charge of opposite conductivity to the back electroluminescent layer.

The first dielectric layer comprises a first front dielectric layer having a fixed charge of opposite conductivity to the emitter portion, a second front dielectric layer having a fixed charge of the same conductivity type as the emitter portion and located on the front surface of the first front dielectric layer, And a third front dielectric layer having a conductive charge type and located on the front surface of the second front dielectric layer.

The first and second front dielectric layers are formed of the same material, such as silicon nitride, and the second and third front dielectric layers are formed of the same material, such as silicon oxide.

The first front dielectric layer is formed of an aluminum oxide film.

In the conventional crystalline solar cell, the emitter portion and the rear portion electric field portion are formed by using a diffusion or ion implantation process. This structure is difficult to reduce the dark saturation current (Jo) of the emitter portion and the rear electric field portion, It is difficult to control the photoelectric conversion efficiency of the solar cell.

In addition, when the first electrode formed on the front surface of the substrate and the second electrode formed on the rear surface of the substrate are formed by a screen printing method, manufacturing cost is very high.

However, in the present invention, the first dielectric layer located on the front surface of the emitter section includes an aluminum oxide film having a fixed charge of the opposite conductivity type to that of the emitter section, so that recombination occurring on the surface of the emitter section is reduced.

Further, a back electric field portion located on the rear surface of the substrate is formed in a three-layer structure of an intrinsic amorphous silicon layer / a first conductive type amorphous silicon layer / a first conductive type microcrystalline silicon layer.

Thus, the passivation property at the interface with the crystalline silicon is improved by the intrinsic amorphous silicon layer, and the amorphous silicon layer of the first conductivity type is formed on the capping film (silicon nitride film) together with the silicon nitride film constituting the first rear dielectric layer of the second dielectric layer capping layer, thereby improving passivation characteristics by annealing. Thus, the recombination occurring at the surface in the back electroluminescent portion is reduced.

And, since the second electrode is in direct contact with the microcrystalline silicon layer of the first conductivity type, the contact resistance with the second electrode is reduced, thereby increasing the fill factor.

In addition, since the back electric field portion includes the microcrystalline silicon layer, it is possible to use a laser beam having a low energy density when forming the openings in the first and second dielectric layers, thereby minimizing heat damage to the substrate by the laser beam, Thus, the occurrence of the dark current Jo is minimized, and the open-circuit voltage Voc is increased.

Since the first electrode directly contacting the exposed emitter through the opening located in the first dielectric layer and the second electrode contacting the exposed backside through the opening located in the second dielectric layer include the plating layer, Cost can be reduced.

In addition, since the deglazing process can be omitted in the plating process, the manufacturing process of the solar cell is simplified, and the first and second dielectric layers include the silicon nitride film and the silicon oxide film, The reflectivity of light is reduced.

1 is a partial perspective view of a double-sided light receiving type solar cell according to the present invention.
FIG. 2 is a cross-sectional view of the solar cell shown in FIG. 1 cut along the line II-II.
Fig. 3 is an enlarged view of the portion A in Fig. 2. Fig.
4 is a view showing passivation characteristics of a rear surface electric field portion according to the present invention.
5 to 8 are views for explaining an example of a method of manufacturing a double-sided light receiving solar cell according to the present invention.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It is to be understood that the present invention is not intended to be limited to the specific embodiments but includes all changes, equivalents, and alternatives falling within the spirit and scope of the present invention.

In describing the present invention, the terms first, second, etc. may be used to describe various components, but the components may not be limited by the terms. The terms may only be used for the purpose of distinguishing one element from another.

For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

The term "and / or" may include any combination of a plurality of related listed items or any of a plurality of related listed items.

Where an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, but other elements may be present in between Can be understood.

On the other hand, when it is mentioned that an element is "directly connected" or "directly coupled" to another element, it can be understood that no other element exists in between.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions may include plural expressions unless the context clearly dictates otherwise.

In the present application, the terms "comprises", "having", and the like are used interchangeably to designate one or more of the features, numbers, steps, operations, elements, components, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, or combinations thereof.

In the drawings, the thickness is enlarged to clearly represent the layers and regions. When a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the case directly above another portion but also the case where there is another portion in between. Conversely, when a part is "directly over" another part, it means that there is no other part in the middle.

Unless otherwise defined, all terms used herein, including technical or scientific terms, may have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

Terms such as those defined in commonly used dictionaries can be interpreted as having a meaning consistent with the meaning in the context of the relevant art and are, unless expressly defined in the present application, interpreted in an ideal or overly formal sense .

In addition, the following embodiments are provided to explain more fully to the average person skilled in the art. The shapes and sizes of the elements in the drawings and the like can be exaggerated for clarity.

Embodiments of the present invention will now be described with reference to the accompanying drawings.

FIG. 1 is a partial perspective view of a double-sided light receiving solar cell according to an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along a line II-II of the double-sided light receiving solar cell shown in FIG. 1, 2 is an enlarged view of a portion A of FIG.

FIGS. 5 to 8 are views for explaining an example of a method of manufacturing a double-sided light receiving type solar cell according to the present invention. FIG. 4 is a view illustrating passivation characteristics of a rear surface electric field portion according to the present invention.

1, a double-sided photoreceptive solar cell according to an embodiment of the present invention includes a substrate 110, an emitter section 120, a first surface of the substrate 110, A first dielectric layer 130, a back surface field (BSF) 170 located on a second side of the substrate 110, e.g., a back surface, A first electrode 140 connected to the emitter section 120 and a second electrode 150 connected to the rear electric section 170. [

Hereinafter, "front surface" refers to a surface facing upward in the accompanying drawings, and "rear surface " refers to a surface facing downward in the accompanying drawings.

The substrate 110 is a semiconductor substrate 110 made of a crystalline silicon containing an impurity of a first conductivity type, for example, an n-type conductivity type. At this time, the silicon may be single crystal silicon or polycrystalline silicon.

Since the substrate 110 has an n-type conductivity type, the substrate 110 contains impurities of pentavalent elements such as phosphorus (P), arsenic (As), antimony (Sb), and the like.

Alternatively, however, the substrate 110 may be of the p-type conductivity type and may be made of a semiconductor material other than silicon. When the substrate 110 has a p-type conductivity type, the substrate 110 may contain an impurity of a trivalent element such as boron (B), gallium, indium, or the like.

Hereinafter, a case where the substrate 110 has an n-type conductivity type will be described as an example.

Such a substrate 110 has a texturing surface whose surface is textured. More specifically, the substrate 110 is formed with a textured surface having a front surface on which the emitter section 120 is located and a back surface located on the opposite side of the front surface.

The emitter portion 120 located on the front surface of the substrate 110 is an impurity portion having a second conductivity type opposite to the conductivity type of the substrate 110, for example, a p-type conductivity type, Lt; RTI ID = 0.0 > 110 < / RTI >

Due to the built-in potential difference due to the pn junction, the electron-hole pairs, which are charges generated by the light incident on the substrate 110, are separated into electrons and holes, electrons move toward the n- Moves toward the p-type.

Therefore, the separated electrons move toward the substrate 110 and the separated holes move toward the emitter part 120 because the substrate 110 is n-type and the emitter part 120 is p-type.

Since the emitter section 120 has a p-type conductivity type, the emitter section 120 is formed by doping an impurity of a trivalent element such as boron (B), gallium (Ga), indium (In) .

Unlike the present embodiment, when the substrate 110 has a p-type conductivity type, the emitter portion 120 has an n-type conductivity type. In this case, the separated holes move toward the substrate 110, and the separated electrons move toward the emitter section 120.

When the emitter section 120 has an n-type conductivity type, the emitter section 120 dopes impurities of pentavalent elements such as phosphorus (P), arsenic (As), antimony (Sb) .

A first region of the emitter section 120 in contact with the first electrode 140 in the emitter section 120 and a second region of the emitter section 120 that is not in contact with or overlapped with the first electrode 140 The impurity doping concentrations may be different.

For example, the first region of the emitter section 120, which overlaps and contacts the first electrode 140 among the emitter sections 120 formed on the front surface of the substrate 110, may have a relatively high doping concentration of the impurity, And the second region of the emitter section 120 which is not in contact with or overlapped with the first electrode 140 may be formed as a low concentration emitter section having a lower doping concentration than that of the high concentration emitter section.

The first dielectric layer 130 formed on the emitter portion 120 may be formed of a material having a negative fixed charge such as aluminum oxide (AlO _x ) or yttrium oxide (Y ₂ O ₃ ) Lt; RTI ID = 0.0 > 130a < / RTI >

The aluminum oxide (AlO _x ) or the trisium oxide (Y ₂ O ₃ ) forming the first front dielectric layer 130a has a chemical passivation property due to the low interface trap density and a negative charge The field-effect passivation characteristics are excellent. It also has excellent stability, moisture permeability and abrasion resistance.

Therefore, the recombination speed of the charges on the surface of the emitter section 120 can be reduced to improve the efficiency of the solar cell and improve the long-term reliability.

The first dielectric layer 130 further includes a second front dielectric layer 130b and a third front dielectric layer 130c located on the first front dielectric layer 130a and a third front dielectric layer 130c further comprises a second front dielectric layer 130c, 130b.

The second front dielectric layer 130b is made of silicon nitride (SiN _x ) having a positive charge and the third front dielectric layer 130c is made of silicon oxide (SiOx) having a positive charge .

The second front dielectric layer 130b and the third front dielectric layer 130c reduce the reflectivity of light incident through the front surface of the substrate 110 and increase the selectivity of a specific wavelength region to increase the efficiency of the solar cell.

The first dielectric layer 130 includes a plurality of openings OP1 that are formed in a line type or a spot type and expose a part of the emitter layer 120. [

The first electrode 140 is formed on the emitter 120 exposed through the opening OP1.

The first electrode 140 is located on the emitter section 120 on the front surface of the substrate and is electrically and physically connected to the emitter section 120.

The first electrode 140 includes a plurality of first finger electrodes 141 and a plurality of first bus bar electrodes 143.

At this time, the plurality of first finger electrodes 141 extend in the first direction shown in FIG. 1, that is, in the X-X 'direction, and extend parallel to the adjacent first finger electrodes 141 at regular intervals.

The plurality of first finger electrodes 141 collects charges, for example, holes, which have migrated toward the emitter section 120.

The plurality of first finger electrodes 141 may be formed of Ni, Cu, Sn, Zn, In, Ti, Au, or combinations thereof. And at least one conductive material selected from the group consisting of

The plurality of first finger electrodes 141 may be formed by a screen printing method for printing and firing a conductive paste containing a conductive material, or may be formed using a plating process using a seed layer. The first finger electrode 141 formed by the plating process includes a plating layer 141a.

The plurality of first bus bar electrodes 143 are located on the same layer as the plurality of first finger electrodes 141 on the emitter section 120 and electrically connect the plurality of first finger electrodes 141 to each other.

At this time, the plurality of first bus bar electrodes 143 are elongated along the second direction orthogonal to the first direction, that is, the second direction (YY 'direction) shown in FIG. 1, And collects the charges collected and moved by the plurality of first finger electrodes 141 and outputs the collected charges to an external device.

The first bus bar electrode 143 may be formed using the same material as the first finger electrode 141 according to the same method.

The entire surface of the first electrode 140 having such a configuration is in direct contact with the emitter section 120.

The rear electric field portion 170 located on the rear surface of the substrate 110 includes an intrinsic amorphous silicon (ia-Si) layer 170a contacting the semiconductor substrate and containing no impurities, An n-type amorphous silicon (n + a-Si) layer 170b containing an n-type impurity at a higher concentration than the semiconductor substrate 110 and an n-type impurity And an n-type microcrystalline silicon (n + mc-Si) layer 170c containing a high concentration of the n-type semiconductor layer 110 in comparison with the semiconductor substrate 110.

The intrinsic amorphous silicon layer 170a may be formed on the entire rear surface of the substrate 110 by plasma enhanced chemical vapor deposition (PECVD), and the recombination rate of charges near the rear surface of the substrate 110 And enhances the internal reflectance of the light passing through the substrate 110 to increase the re-entrance rate of the light that has passed through the substrate 110.

The n-type amorphous silicon layer 170b is formed on the entire rear surface of the intrinsic amorphous silicon layer 170a by a plasma enhanced chemical vapor deposition (PECVD) Type amorphous silicon layer 170b.

The n-type amorphous silicon layer 170b functions to form an ohmic contact between the intrinsic amorphous silicon layer 170c and the microcrystalline silicon layer 170c.

the thickness T2 of the n-type amorphous silicon layer 170b is formed larger than the thickness T3 of the n-type microcrystalline silicon layer 170c and the thickness T3 of the n- Is preferably formed to be larger than the thickness T1 of the silicon layer 170a.

For example, the intrinsic amorphous silicon layer 170a is formed with a thickness T1 of 1 nm to 5 nm, the n-type amorphous silicon layer 170b is formed with a thickness T2 of 10 nm to 30 nm, The microcrystalline silicon layer 170c may be formed to have a thickness T3 of 5 nm to 10 nm.

The rear electric field portion 170 having such a three-layer structure performs a back electric field function, so that a potential barrier that generates a potential difference with the substrate 110 can be formed due to a difference in impurity concentration from the substrate 110.

Accordingly, when the substrate 110 has the n-type conductivity type and the emitter section 120 has the p-type conductivity type, the rear electric section 170 forms an n-type electric field higher than the substrate 110, Electrons that are the majority carriers of the substrate 110 can be moved more easily to the second electrode 150 through the rear electric section 170 and holes that are the majority carriers of the emitter section 120 move toward the second electrode 150 As shown in Fig.

In addition, since the rear electric section 170 includes an amorphous silicon material and a microcrystalline silicon material, the passivation function can be performed together with the rear electric field function described above.

The second dielectric layer 180 located on the rear surface of the rear electric 170 includes a first rear dielectric layer 180a and a second rear dielectric layer 180a having a positive positive charge opposite to that of the rear electric conductor 170, 180b.

More specifically, the first rear dielectric layer 180a is formed of the same material as the second front dielectric layer 130b, e.g., silicon nitride (SiNx), and the second rear dielectric layer 180b is formed of the same material as the third front dielectric layer 130c For example, a silicon oxide film (SiOx).

Since the silicon nitride film forming the first rear dielectric layer 180a can be formed at a lower processing temperature (between 300 ° C and 400 ° C) than the silicon oxide film, the amorphous silicon (a-Si The thermal damage to the backside electrical < RTI ID = 0.0 > 170 < / RTI >

The first and second rear dielectric layers 180a and 180b reduce the reflectivity of light incident through the back surface of the substrate 110 and increase the selectivity of a specific wavelength region to increase the efficiency of the solar cell.

The second dielectric layer 180 is formed in a planar shape of a line type or a spot type to form a plurality of openings OP2 (not shown) exposing a part of the rear electric section 170, in particular, a part of the n-type microcrystalline silicon layer 170c. ).

At this time, the interval between the plurality of openings OP2 is formed to be 100 mu m to 500 mu m.

The reason for defining the interval D1 between the plurality of openings OP2 is that when the laser beam is irradiated on the substrate 110 to form the opening OP2, the interval D1 between the openings becomes excessively narrow The area of the substrate 110 irradiated with the laser beam is excessively increased to deteriorate the characteristics of the substrate 110. If the space D1 between the openings is excessively large, ) Is lowered.

The second electrode 150 is formed on the n-type microcrystalline silicon layer 170c exposed through the opening OP2.

The second electrode 150 is entirely in contact with the n-type microcrystalline silicon layer 170c entirely and includes a plurality of second finger electrodes 151 and a plurality of second bus bar electrodes 153.

The plurality of second finger electrodes 151 extend in the same first direction X-X 'as the plurality of first finger electrodes 151 and the second bus bar electrode 153 extends to the second bus bar electrode 143 And the second bus bar electrode 153 is located at a position facing the first bus bar electrode 143. The second bus bar electrode 153 extends in the second direction Y-Y '

The second bus bar electrode 153 is connected to the interconnector in the same manner as the first bus bar electrode 143 and outputs a carrier collected from the substrate 110 to the second finger electrode 151 to an external device.

The spacing between the second finger electrodes 151 may be greater than the spacing between the first finger electrodes 141.

The second electrode 150 may be formed using a plating method having a relatively low process temperature as compared with the screen printing method, like the first electrode 140.

In this case, the thermal damage to the film of the rear electric section 170 including the amorphous silicon (a-Si) material is minimized, so that the passivation function of the rear electric section 170 can be prevented from deteriorating.

Since the second finger electrode 151 and the second bus bar electrode 153 are in direct contact with the n-type microcrystalline silicon layer 170c, the contact resistance of the second electrode is reduced, and thus the fill factor is increased.

When light is irradiated onto the double-side light-receiving solar cell having such a structure and is incident on the semiconductor substrate 110 through the antireflection film 130 and the emitter section 120, the electron- Occurs. At this time, the reflection loss of the light incident on the substrate 110 is reduced by the first dielectric layer 130, and the amount of light incident on the substrate 110 is increased.

The electron-hole pairs are separated from each other by the pn junction of the substrate 110 and the emitter section 120, and the separated holes move toward the emitter section 120 having the p-type conductivity type, To the substrate 110 having the conductive type.

The electrons that have moved toward the emitter section 120 are collected in the first bus bar electrode 143 through the first finger electrode 141 and electrons moved toward the substrate 110 pass through the rear electric section 170 2 finger electrodes 151 and then transferred to the second bus bar electrode 153. [

Accordingly, when the first bus bar electrode 143 of one of two neighboring solar cells and the second bus bar electrode 153 of another solar cell are connected by an inter-connector, a current flows, Power.

In the double-sided light receiving type solar cell according to the present invention, the rear electric section 170 includes the intrinsic amorphous silicon layer 170a, the n-type amorphous silicon layer 170b and the n-type microcrystalline silicon layer 170c, Layer structure, and performs the back surface electric field function and the passivation function together.

The rear electric conductor 170 of this structure is a carrier which is recombined by a dangling bond near the rear side of the substrate 110 when electrons which are the majority carriers of the substrate 110 move to the rear side of the substrate 110 The magnitude of the dark current (Jo) causing the recombination of carriers can be further reduced, and electrons, which are the majority carriers of the substrate 110, can be transmitted through the rear electric section 170 It is possible to further prevent the positive carriers, which are the majority carriers of the emitter section 120, from moving toward the second electrode 150, while moving to the second electrode 150 more easily.

Here, the dark current Jo means a current value that causes recombination of carriers. Therefore, as the dark current Jo increases, the amount of recombination of the carriers increases. As a result, the short circuit current Jsc of the solar cell decreases and the efficiency of the solar cell decreases.

That is, the passivation effect increases as the dark current (Jo) decreases, and the passivation effect decreases as the dark current (Jo) increases. Therefore, as the dark current (Jo) decreases, the solar cell efficiency may be improved.

Since the rear electric field portion 170 includes the n-type microcrystalline silicon layer 170c, the carrier moving in the direction from the substrate 110 toward the second electrode 150 is more smoothly moved.

4 is a graph showing the difference in passivation characteristics between the solar cell of the present invention and the conventional solar cell having the rear electric section 170 of the three-layer structure and the second dielectric layer 180 of the two-layer structure.

Referring to FIG. 4, since the passivation characteristic of the solar cell of the present invention is superior to that of the conventional solar cell, the open voltage (Implied Voc) of the solar cell of the present invention is increased to the open circuit voltage of the conventional solar cell.

A method of manufacturing a solar cell having such a structure will be described with reference to Figs. 5 to 9. Fig.

First, as shown in Fig. 5, an emitter section 120 containing a p-type impurity is formed on the entire surface of a substrate 110 containing an n-type impurity.

Next, as shown in Fig. 6, an intrinsic amorphous silicon layer 170a, an n-type amorphous silicon layer 170b and an n-type microcrystalline silicon layer 170c are sequentially formed on the back surface of the substrate 110. [

7, aluminum oxide is deposited on the entire surface of the emitter layer 120 to form a first front dielectric layer 130a, and silicon nitride, which can be deposited at a lower processing temperature than silicon oxide, A second front dielectric layer 130b is deposited over the front dielectric layer 130a and a silicon oxide is deposited over the second front dielectric layer 130b to enable deposition at a higher process temperature than silicon nitride, 130c.

The first rear dielectric layer 180a of the second dielectric layer 180 located on the rear surface of the n-type microcrystalline silicon layer 170c is formed simultaneously with the second front dielectric layer 130b and the second rear dielectric layer 180b, Is formed simultaneously with the third front dielectric layer 130c.

8, a plurality of openings OP1 are formed in the first dielectric layer 130 located on the front surface of the substrate 110 by laser ablation, A plurality of openings OP2 are formed in the second dielectric layer 180 located on the rear side using laser ablation.

Thereafter, the first electrode 130 is formed in the emitter section 120 exposed by the opening OP1 and the n-type microcrystalline silicon layer 170c exposed by the opening OP2 The second electrode 140 is formed to manufacture the solar cell shown in FIG.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It belongs to the scope of right.

Claims (18)

A semiconductor substrate containing an impurity of a first conductivity type;
An emitter section located on a first side of the substrate, the emitter section containing an impurity of a second conductivity type having opposite conductivity of the first conductivity type;
A first dielectric layer located on a front surface of the emitter section and having a plurality of first openings;
A back electrometer located on a back surface of the substrate and containing an impurity of a first conductivity type;
A second dielectric layer located on a back surface of the rear electric field portion and having a plurality of second openings;
A first electrode connected to the emitter portion exposed through the first opening; And
A second electrode connected to the rear electric field portion exposed through the second opening,
/ RTI >
(Ia-Si) layer which is in contact with the semiconductor substrate and contains no impurities, and a rear surface electric field portion which is located on the rear surface of the intrinsic amorphous silicon layer and contains impurities of the first conductivity type at a higher concentration than the semiconductor substrate A first conductive type amorphous silicon (a-Si) layer of a first conductivity type and a first conductive type (a-Si) type second conductive type semiconductor layer located on the rear surface of the amorphous silicon layer of the first conductivity type and containing impurities of a first conductivity type Of a microcrystalline silicon (mc-Si) layer. The method of claim 1,
And the rear electric field portion is located on the entire rear surface of the substrate. The method of claim 1,
Wherein a distance between the plurality of openings formed in the second dielectric layer is 100 占 퐉 to 500 占 퐉. The method of claim 1,
Wherein the first conductivity type is an n-type and the second conductivity type is a p-type. The method of claim 1,
Wherein the first electrode comprises a plurality of first finger electrodes located on a front surface of the semiconductor substrate and extending in a first direction. The method of claim 5,
Wherein the first electrode further comprises a plurality of first bus bar electrodes extending in a second direction orthogonal to the first direction, wherein the first bus bar electrode is a double-sided light receiving type Solar cells. The method of claim 6,
Wherein the first finger electrode and the first bus bar electrode comprise a plating layer. The method of claim 1,
Wherein the entire front surface of the second electrode is in direct contact with the microcrystalline silicon layer of the first conductivity type. 9. The method of claim 8,
Wherein the second electrode comprises a plating layer. The method of claim 1,
Wherein the thickness of the amorphous silicon layer of the first conductivity type is greater than the thickness of the microcrystalline silicon layer of the first conductivity type and the thickness of the microcrystalline silicon layer of the first conductivity type is less than the thickness of the amorphous silicon layer of the first conductivity type. A large - sized double - sided light - receiving solar cell. 11. The method of claim 10,
Wherein the intrinsic amorphous silicon layer is formed to a thickness of 1 nm to 5 nm. 11. The method of claim 10,
Wherein the amorphous silicon layer of the first conductivity type is formed to a thickness of 10 nm to 30 nm. 11. The method of claim 10,
Wherein the microcrystalline silicon layer of the first conductivity type is formed to a thickness of 5 nm to 10 nm. 14. The method according to any one of claims 1 to 13,
Wherein the second dielectric layer comprises a first rear dielectric layer and a second rear dielectric layer, wherein the first rear dielectric layer and the second rear dielectric layer each have a fixed charge of opposite conductivity to the rear electric field. The method of claim 14,
Wherein the first dielectric layer comprises a first front dielectric layer having a fixed charge of opposite conductivity to the emitter portion, a second front dielectric layer having a fixed charge of the same conductivity type as the emitter portion and located on the front surface of the first front dielectric layer, And a third front dielectric layer having a fixed electric charge of the same conductivity type as that of the emitter portion and located on the front surface of the second front dielectric layer. 16. The method of claim 15,
Wherein the first rear dielectric layer and the second front dielectric layer are formed of the same material and the second rear dielectric layer and the third front dielectric layer are formed of the same material. 17. The method of claim 16,
Wherein the first front dielectric layer and the second front dielectric layer are formed of a silicon nitride film and the second rear dielectric layer and the third front dielectric layer are formed of a silicon oxide film. 17. The method of claim 16,
Wherein the first front dielectric layer is formed of an aluminum oxide film.

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