KR20140081547A - Method of fabricating emiconductor device having storage node contact - Google Patents

Abstract

A method of fabricating a semiconductor device having a storage node contact of the present invention includes forming a storage node contact hole exposing a portion of a surface of an active region on a substrate having an active region and implanting impurity doping at a lower concentration towards the center of the edge Forming a conductive layer having a concentration gradient in the lower portion of the storage node contact hole, performing a nitroelectric pre-implant for the conductive layer, and forming a metal silicide layer on the conductive layer subjected to the Nitride transition .

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method of manufacturing a semiconductor device having a storage node contact,

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device having a storage node contact.

BACKGROUND ART Semiconductor memory devices, such as Dynamic Random Access Memory (DRAM) devices, include a plurality of transistors and capacitors. The capacitors are connected to the transistors and used to store information. The transistors are formed in a plurality of active regions defined in the surface region of the semiconductor substrate. The capacitors are each connected to the transistor through a storage node contact including a contact pad or a contact plug.

In recent years, as the degree of integration of semiconductor devices has increased, the area occupied by unit cells has also been drastically reduced. In order to overcome the decrease of the cell area, there have been various attempts to change not only the microfabrication process but also the structural change of the unit cell. According to this trend, various attempts have been made to improve the characteristics of the entire semiconductor memory device by changing the structure or characteristics of the storage node contact connecting the capacitor and the transistor.

One of the important characteristics exhibited by storage node contacts is contact resistance. The storage node contact acts as a signal transmission path between the transistor and the capacitor. Therefore, a large contact resistance acts as a cause of slowing the operation speed of the device. In order to reduce the contact resistance of the storage node contact, a polysilicon layer and a metal layer are stacked. In particular, a metal silicide layer is disposed between the polysilicon layer and the metal layer to form an ohmic contact. However, a void, which is an empty space, may be formed in the polysilicon layer in the process of forming the metal silicide layer. The void can greatly increase the contact resistance, and in particular, the voids are moved in a subsequent process after forming the metal silicide layer, and the contact resistance of the storage node contact may be further increased by such a void movement.

The problem to be solved by the present invention is to provide a method of manufacturing a semiconductor device having a storage node contact capable of improving contact resistance by suppressing void movement in a storage node contact.

A method of fabricating a semiconductor device having a storage node contact according to an example of the present invention includes forming a storage node contact hole exposing a portion of a surface of an active region on a substrate having an active region, Forming a conductive layer having a concentration gradient in which impurity doping is performed on the conductive layer, underneath the storage node contact hole, performing a nitroelectric pre-implant for the conductive layer, and forming a metal silicide layer on the conductive layer .

In one example, the storage node contact hole can be formed in a bulb structure in which the width in the lower portion in contact with the active region is larger than the width in the upper portion.

In one example, the storage node contact holes may be defined by an insulating spacer layer covering the bit line stack and the bit line stack.

In one example, the conductive layer may be formed of a polysilicon layer.

In one example, the step of forming a conductive layer comprises: forming a first polysilicon layer having a first impurity-undoped concentration; forming a second polysilicon layer having a second impurity doping concentration lower than the first impurity doping concentration Forming a third polysilicon layer having a third impurity doping concentration below a second impurity doping concentration on the second polysilicon layer; and forming a second polysilicon layer on the third polysilicon layer, Forming a fourth polysilicon layer having a fourth impurity doping concentration less than the third impurity doping concentration and forming a fifth polysilicon layer not doped with impurities on the fourth polysilicon layer have.

In this case, the first impurity doping concentration is 8.0 × 10 ²⁰ to 9.0 × 10 ²⁰ atom / cm 3, the second impurity doping concentration is 6.0 × 10 ²⁰ to 7.0 × 10 ²⁰ atom / cm 3, the third impurity doping concentration is 5.0 10 ²⁰ to 6.0 10 ²⁰ atom / cm 3, and the fourth dopant concentration may be 4.0 10 ²⁰ to 5.0 10 ²⁰ atom / cm 3.

The first polysilicon layer, the second polysilicon layer, and the third polysilicon layer are each formed to a thickness of 40-60 angstroms, the fourth polysilicon layer is formed to a thickness of 100-600 angstroms, and the fifth poly The silicon layer may be formed to a thickness of 50-100 ANGSTROM.

In one example, performing the pre-implantation of the Nitrogen over the conductive layer may include a first Nitrogen pre-implant step performed on the top of the conductive layer, and a second Nitrogen pre- Step < / RTI >

In one example, the first Nitrogen pre-implant step can be performed under conditions that Rp is set to a depth of 400 ANGSTROM to 500 ANGSTROM.

In one example, the second Nitrogen pre-implant step can be performed under conditions where Rp is set to a depth of 100 ANGSTROM to 200 ANGSTROM.

In one example, the metal silicide layer can be formed of a cobalt silicide layer.

In one example, the method may further comprise forming a metal layer over the metal silicide layer.

In this case, the metal layer may be formed of a tungsten layer.

According to the present invention, it is possible to suppress the movement of the void in the vertical direction and the movement in the horizontal direction, thereby advantageously restraining the occurrence of problems such as the open fault of the storage node contact due to the void and the degradation of the characteristics / RTI >

1 is a layout diagram showing a storage node contact formed by a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIGS. 2 to 11 are cross-sectional views illustrating a method of manufacturing a semiconductor device having a storage node contact according to an embodiment of the present invention.

1 is a layout diagram showing a storage node contact formed by the manufacturing method of the semiconductor device 100 according to this embodiment. Referring to FIG. 1, a plurality of active regions 111 ', 112', and 113 'are defined by a device isolation region 120. Each active region 111 ', 112', 113 'is arranged long along a first direction which is oblique in the figure. Next, the word line 200 is formed to be long along the second direction, which is the transverse direction in the drawing. Each active area 110 is overlapped with two word lines 200. Next, a bit line contact hole 400 is formed to expose the bit line contact region of the active regions 111 ', 112', 113 '. Next, the bit line 300 is formed to be long along the third direction which is the vertical direction in the drawing, while overlapping the bit line contact hole 400. Although not shown in the figure, a storage node contact hole 500 is formed by forming an insulating spacer layer on the bit line 300, a storage node contact hole 500 is filled with a conductive layer, and a storage node Thereby forming a contact.

In this example, a portion of the storage node contact hole is first filled with a polysilicon layer having an impurity concentration gradient to form a storage node contact, followed by a night pre-implant. Then, a metal silicide layer is formed on the polysilicon layer, and a metal layer is formed thereon to complete the storage node contact. Accordingly, even if voids are formed in the process of forming the polysilicon layer, it is possible to suppress the movement of the voids in the vertical direction and the horizontal direction, thereby preventing problems such as open defect of the storage node contact caused by voids, Can be suppressed.

FIGS. 2 to 11 are cross-sectional views taken along line I-I 'of FIG. 1. Hereinafter, a method of manufacturing a semiconductor device having a storage node contact according to this embodiment will be described in detail.

First, as shown in FIG. 2, an isolation insulating layer 146 of a substrate 130 made of a semiconductor material such as silicon is formed to define the active regions 111, 112, and 113. In order to form the element isolation insulating layer 146, first, a trench 142 having a predetermined depth is formed in the element isolation region of the substrate 130. A thinner liner layer 144 is formed in the trench 142 and then the trench 142 is filled with an insulating layer to form an element isolation insulating layer 146. The active regions 111, 112, and 113 defined by the element isolation insulating layer 146 have a planar structure that is long along the first direction, which is the oblique direction of FIG. 1, as described with reference to FIG. 1 . 2, the active region 111 arranged in the middle of the three active regions 111, 112, and 113 separated by the element isolation insulating layer 146 in FIG. And an active region 111 'in which a bit line contact hole 400 is formed along I-I'. Thus, the active region 111 shown in FIG. 2 is the middle portion of the active region 111 'of FIG. The active region 112 disposed on the left and the active region 113 disposed on the right of the three active regions 111, 112, and 113 are connected to a storage node contact hole (not shown) along the line I-I ' The active region 112 is the upper end portion of the active region 112 'of FIG. 1 and the active region 113 is the lower end portion of the active region 113' of FIG. 1 .

After the element isolation insulating layer 146 is formed, a hard mask layer pattern 210 for forming a word line (200 in FIG. 1) is formed on the entire surface. 2, the hard mask layer pattern 210 is formed on the active region 111, 112, 113 of the portion where the word line (200 in FIG. 1) is to be formed and a portion of the element isolation insulating layer 146 And has an opening for exposing the surface. Next, a portion exposed by the opening is etched to a certain depth to form a trench, and the inside of the trench is filled with a conductive layer to form a buried word line (200 in FIG. 1). As described with reference to Fig. 1, two buried structure word lines (200 in Fig. 1) are superimposed on one active region. Thus, for example, in the active region 111 ', the region where the bit line contact 400 between the two word lines (200 in FIG. 1) is to be formed and the region where the storage node contacts 500 at both edges are to be formed .

Referring to FIG. 3, a mask layer pattern 220 having openings exposing active regions 111 in which bit line contacts 400 are to be formed on the front side is formed. In one example, the mask layer pattern 220 may be formed of a photoresist layer. In one example, the opening that exposes the active region 111 in which the bit line contact 400 is to be formed may be circular or may be elliptical extending further in one direction (see FIG. 1). Next, the bit line contact hole 400 is formed by etching using the mask layer pattern 220 as an etching mask. The bit line contact hole 400 exposes the element isolation insulating layer 146 to the side and exposes the surface of the active region 111 at the bottom. Although not separately shown in the figure, the active region 111 exposed at the bottom of the bit line contact hole 400 may be an impurity diffusion region doped with an impurity.

Referring to FIG. 4, a conductive layer, such as a polysilicon layer, is deposited to fill the bit line contact holes 400. The etch back process is then performed on the deposited polysilicon layer to form the bit line contact plugs embedded in the bit line contact holes 400. Next, a bit line conductive layer and a bit line hard mask layer are sequentially stacked on the front surface of the resultant formed with the bit line contact plug. In one example, the bit line conductive layer is formed of a tungsten (W) layer having a thickness of 200 Å to 400 Å, and the bit line hard mask layer is formed of a nitride (N) layer having a thickness of 1500 Å to 2000 Å. In some cases, a barrier metal layer such as a titanium nitride (TiN) layer may be further disposed between the tungsten (W) layer and the bit line contact plug.

Next, a mask layer pattern (not shown) is formed to expose a part of the surface of the bit line hard mask layer, and the exposed portion of the bit line hard mask layer is removed using the mask layer pattern as an etching mask to form bit line hard mask layer patterns 330 are formed. In one example, the mask layer pattern may be formed of a photoresist layer. After the bit line hard mask layer pattern 330 is formed, the mask layer pattern is removed. Then, the bit line conductive layer pattern 320 and the bit line contact plug pattern 310 are formed by sequentially etching the bit line conductive layer and the bit line contact plug by etching using the bit line hard mask layer pattern 330 as an etching mask. do. The bit line contact plug pattern 310, the bit line conductive layer pattern 320, and the bit line hard mask layer pattern 330 constitute the bit line 300. As described with reference to FIG. 1, the bit line 300 is disposed along the third direction, which is the longitudinal direction, and one bit line 300 is superimposed on one active region. Therefore, the active region 111 'is an area where the bit line contact 400 is to be formed, for example, an area not overlapped with the word line (200 in FIG. 1) of the portion overlapping one bit line 300.

Referring to FIG. 5, a first bit line spacer layer 340 and a second bit line spacer layer 350 are formed on the front surface of the resultant structure in which the bit line 300 is formed. In one example, in the case of having a peripheral circuit region outside the cell region, such as a DRAM (DRAM) device, the first bit line spacer layer 340 is formed and the second bit line spacer layer 350 ). Thus, the first bit line spacer layer 340 is formed in both the cell region and the peripheral circuit region, while the second bit line spacer layer 350 is formed only in the cell region. The first bit line spacer layer 340 may be formed of a nitride (N) layer having a thickness of 40 ANGSTROM to 65 ANGSTROM. The second bit line spacer layer 350 may be formed of a nitride (N) layer having a thickness of 60 ANGSTROM to 90 ANGSTROM.

Referring to FIG. 6, an anisotropic etch process, such as an etch back process, is performed on the second bit line spacer layer 350 and the first bit line spacer layer 340 to form an active region The first bit line spacer layer 340 and the second bit line spacer layer 350 on the first and second bit line spacers 112 and 113 are removed. In this process, the first bit line spacer layer 340 and the second bit line spacer layer 350 on the upper surface of the bit line 300 are all removed so that the upper surface of the bit line hard mask layer pattern 330 is exposed Although some of the first bit line spacer layer 340 and the second bit line spacer layer 350 may remain, as the case may be. Next, an interlayer insulating layer (not shown) is formed on the entire surface, and an interlayer insulating layer disposed between the second bit line spacer layers 350 is removed using a predetermined mask layer pattern, for example, a photoresist layer pattern. Thereby forming a first storage node contact hole 510 exposing the active regions 112 and 113 between the second bit line spacer layers 350. [ The second storage node contact holes 520 are formed by performing isotropic etching on the exposed active regions 112 and 113 to increase the exposed areas of the active regions 112 and 113. The storage node contact hole 500 includes a first storage node contact hole 510 between the adjacent bit lines 300 and a second storage node contact hole 510 which contacts the active regions 112 and 113, And a second storage node contact hole 520 having a width that is relatively larger than the width of the second storage node contact hole 510. The active regions 112 and 113 exposed at the bottom of the second storage node contact hole 520 may be an impurity diffusion region doped with an impurity although not separately shown in the drawing. In one example, as shown in FIG. 1, the storage node contact hole 500 may be circular or may be oval shaped to extend further in one direction.

Referring to FIG. 7, the first storage node contact hole 510 and the second storage node contact hole 520 are filled with a conductive layer, for example, a polysilicon layer 600. Due to the narrow width of the first storage node contact hole 510 and the second storage node contact hole 520, the voids 710 and 720 may be formed in the polysilicon layer 600. Although the voids 710 and 720 can be formed in various forms, in this example, as shown in the figure, a relatively large and deep deep second storage node contact hole 520 has a relatively large size A first void 710 is created and a relatively small second void 720 is created in the first storage node contact hole 510 having a relatively narrow width and a shallow depth.

The polysilicon layer 600 includes a first polysilicon layer 610 doped with a different impurity concentration, a second polysilicon layer 620, a third polysilicon layer 630, and a fourth polysilicon layer 640), and an undoped fifth polysilicon layer without doping. More specifically, a first polysilicon layer 610 having a first impurity doping concentration is first deposited in the first storage node contact hole 510 and the second storage node contact hole 520. In one example, the first dopant concentration is 8.0 × 10 ²⁰ to 9.0 × 10 ²⁰ atoms / cm 3, and the thickness of the first polysilicon layer 610 is approximately 40-60 Å. Next, a second polysilicon layer 620 having a second impurity doping concentration lower than the first impurity doping concentration is deposited on the first polysilicon layer 610. In one example, the second impurity doping concentration is 6.0 ㅧ 10 ²⁰ to 7.0 ㅧ 10 ²⁰ atoms / cm 3, and the thickness of the second polysilicon layer 620 is approximately 40-60 Å. A third polysilicon layer 630 is then deposited over the second polysilicon layer 620 with a third impurity doping concentration that is less than the second impurity doping concentration. In one example, the third dopant doping concentration is 5.0 ㅧ 10 ²⁰ to 6.0 ㅧ 10 ²⁰ atoms / cm 3, and the thickness of the third polysilicon layer 630 is approximately 40-60 Å. In this example, the first polysilicon layer 610, the second polysilicon layer 620, and the third polysilicon layer 630 define a portion of the first storage node contact hole 510, A hole 520 is buried. In this process, as shown in the figure, a first void 710 may be generated in the second storage node contact hole 520.

A fourth polysilicon layer 640 is then deposited over the third polysilicon layer 630 with a fourth impurity doping concentration that is less than the third impurity doping concentration. In one example, the fourth dopant doping concentration is 4.0 × 10 ²⁰ to 5.0 × 10 ²⁰ atoms / cm 3, and the thickness of the second polysilicon layer 640 is approximately 100-600 Å. A fifth polysilicon layer 650 is then deposited over the fourth polysilicon layer 650 without doping the impurity. In this process, as shown in the figure, a second void 720 may be generated in the first storage node contact hole 520. As the fourth polysilicon layer 640 and the fifth polysilicon layer 650 are deposited, the first storage node contact holes 510 are also filled. In one example, the thickness of the fifth polysilicon layer 650 is approximately 50-100 ANGSTROM. In one example, the impurities doped in the first, second, third, and fourth polysilicon layers 610, 620, 630, 640 are phosphorous (P) Impurities may also be doped.

Referring to FIG. 8, an anisotropic etching process, such as an etch back process, is performed on the polysilicon layer 600 to remove the polysilicon layer 600 to a predetermined depth from the surface of the first storage node contact hole 510. In one example, the thickness D of the polysilicon layer 600 to be removed is approximately 500 ANGSTROM to 700 ANGSTROM from the top surface of the bit line hardmask layer pattern 330. By this etching process, the polysilicon layer 600 on the upper surface of the bit line hard mask layer pattern 330 is all removed, exposing the upper surface of the bit line hard mask layer pattern 330.

Referring to FIG. 9, a N-implant is performed on polysilicon layer 600, as indicated by arrow 800 in the figure. Nitrogen pre-implant is performed in two stages. First, a first NL pre-implant step is performed to form a first NL pre-implant region 810 at the interface between the first storage node contact hole 510 and the second storage node contact hole 520. Next, a second Nitrogen pre-implant step is performed to form a second Nitrogen pre-implant region 820 on the surface of the polysilicon layer 600. In one example, the first Nitrogen pre-implant step is performed in a state where the implant energy is set at about 15 KeV to 20 KeV and the dose is set at about 3.0 10 ¹⁵ atoms / cm 2 to 5.0 10 ¹⁵ atoms / cm 2 . The Rp (Projected Range) is set to a depth of about 400 ANGSTROM to 500 ANGSTROM so that the first NL pre-implant region 810 is formed at the boundary between the first storage node contact hole 510 and the second storage node contact hole 520 do. In one example, the second Nitrogen pre-implant step is performed with the implant energy set at about 3 KeV to 5 KeV and the dose set at about 5.0 10 ¹⁵ atoms / cm 2. And the Rp (Projected Range) is set to a depth of about 100 ANGSTROM to 200 ANGSTROM so that the second NITROELECTRIC IMPLANT region 820 is formed on the surface of the polysilicon layer 600. [

Although the first NL pre-implant step of forming the first NL pre-implant region 810 at the interface between the first storage node contact hole 510 and the second storage node contact hole 520 is performed first, Although a second nitroelectric pre-implant step is performed later to form a second pre-implant region 820 on the surface of the layer 600, the second nitro pre-implant step may be performed first, The first nitro furnace pre-implant step may be performed later. The first Nitrogen pre-implant region 810 is formed such that the first void 710 in the second storage node contact hole 520 is moved to the polysilicon layer 600 in the first storage node contact hole 510 in a subsequent step . The second Nitrogen pre-implant region 820 inhibits void formation in the subsequent metal silicide layer formation process and increases the thermal stability of the metal silicide layer.

Referring to FIG. 10, a metal silicide layer is formed on the polysilicon layer 600 in the first storage node contact hole 510. In this example, the metal silicide layer is formed of a cobalt silicide layer 910. To form the cobalt silicide layer 910, first a cobalt (Co) layer is formed on the front surface. In some cases, a titanium / titanium nitride (Ti / TiN) layer may be further formed on the cobalt (Co) layer. Next, heat treatment is performed to induce a silicide reaction. In this example, the heat treatment is performed using a rapid thermal processing (RTP) method, and is performed in two stages. Specifically, the first rapid thermal annealing (RTP) is performed at about 500 ° C to 550 ° C. The polysilicon layer 600 and the cobalt (Co) layer undergo a silicide reaction by the first rapid thermal processing (RTP) to form a cobalt silicide layer 910. Next, the unreacted cobalt (Co) layer and the titanium / titanium nitride (Ti / TiN) layer are removed and a second rapid thermal anneal (RTP) is performed at approximately 750 ° C to 800 ° C.

In the process of forming the metal silicide layer, the polysilicon layer 600 has a concentration gradient such that the impurity doping concentration becomes higher toward the side, so that the second void 720 is prevented from moving in the horizontal direction. And the presence of the first Nitrogen implant region 810 in Figure 9 causes the first void 710 in the second storage node contact hole 520 to be in contact with the polysilicon layer 600 in the first storage node contact hole 510 As shown in Fig. The impurities doped in the polysilicon layer 600 and the nitrides in the first and second Nitrogen pre-implant regions 810 and 820 are subjected to the first rapid thermal annealing (RTP) and the second rapid thermal annealing (RTP) The electroluminescence is diffused in the polysilicon layer 600 so that the polysilicon layer 600 has a uniformly uniform doping concentration.

11, a titanium / titanium nitride (Ti / TiN) layer 920 is formed as a barrier metal layer to a thickness of about 30 A to 50 A, and a metal layer such as a tungsten (W) layer 930 is formed to a thickness of about 300 A to 500 A So that the remaining empty space of the first storage node contact hole 510 is filled. And planarization is performed so that adjacent tungsten (W) layers 930 are separated from each other. This results in a storage node contact made up of a polysilicon layer 600, a cobalt silicide layer 910, and a tungsten (W) layer 930.

111, 112, 113 ... active area
200 ... word line
300 ... bit line
400 ... bit line contact hole
500 ... storage node contact hole
600 ... a polysilicon layer having an impurity concentration gradient
710, 720 ... Boyd
810, 820 ... First and second nitro furnace front implant regions
910 ... metal silicide layer
920 ... barrier metal layer
930 ... metal layer

Claims (13)

Forming a storage node contact hole exposing a surface of the active region over a substrate having an active region;
Forming a conductive layer in a lower portion of the storage node contact hole, the conductive layer having a concentration gradient in which impurity doping is performed at a lower concentration from an edge to a center;
Performing a nitroelectric pre-implant for the conductive layer; And
And forming a metal silicide layer on the conductive layer doped with the nitride. The method according to claim 1,
Wherein the storage node contact hole is formed in a bulb structure having a width at a lower portion in contact with the active region that is larger than a width at an upper portion. The method according to claim 1,
Wherein the storage node contact hole is defined by a bit line spacer layer covering the bit line and the bit line. The method according to claim 1,
Wherein the conductive layer is formed of a polysilicon layer. 5. The method of claim 4, wherein forming the conductive layer comprises:
Forming a first polysilicon layer having a first impurity-undoped concentration;
Forming a second polysilicon layer on the first polysilicon layer having a second impurity doping concentration lower than the first impurity doping concentration;
Forming a third polysilicon layer having a third impurity doping concentration below the second impurity doping concentration on the second polysilicon layer;
Forming a fourth polysilicon layer having a fourth impurity doping concentration below the third impurity doping concentration on the third polysilicon layer; And
And forming a fifth polysilicon layer on the fourth polysilicon layer that is not doped with impurities. 6. The method of claim 5,
Wherein the first impurity doping concentration is 8.0 to 10 ²⁰ to 9.0 10 ²⁰ atom / cm 3, the second impurity doping concentration is 6.0 to 10 ²⁰ to 7.0 10 ²⁰ atom / cm 3, the third impurity doping concentration is 5.0 10 ²⁰ to 6.0 10 ²⁰ atoms / cm 3, and the fourth impurity doping concentration is 4.0 10 ²⁰ to 5.0 10 ²⁰ atoms / cm 3. 6. The method of claim 5,
Wherein the first polysilicon layer, the second polysilicon layer, and the third polysilicon layer are each formed to a thickness of 40-60 angstroms, the fourth polysilicon layer is formed to a thickness of 100-600 angstroms, Wherein the polysilicon layer is formed to a thickness of 50-100 ANGSTROM. 2. The method of claim 1, wherein performing the pre-
A first nitro furnace implant step performed on top of the conductive layer; And
And performing a second nitroelectric pre-implant step on the lower portion of the conductive layer. 9. The method of claim 8,
Wherein the first Nitrogen pre-implant step is performed under the condition that Rp is set to a depth of 400 ANGSTROM to 500 ANGSTROM. 9. The method of claim 8,
Wherein the second NL pre-implant step is performed under the condition that Rp is set to a depth of 100 ANGSTROM to 200 ANGSTROM. The method according to claim 1,
Wherein the metal silicide layer is formed of a cobalt silicide layer. The method according to claim 1,
And forming a metal layer on the metal silicide layer. 13. The method of claim 12,
Wherein the metal layer is formed of a tungsten layer.

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