KR20130142521A - Vertical type memory device and fabrication method thereof - Google Patents

Abstract

A vertical memory device capable of minimizing cell size and improving current driving capability and a method of manufacturing the same are provided.
The vertical memory device according to an embodiment of the present technology is a common source region, a source region formed on the common source region and extending in the first direction, formed on the source region, extending in the first direction, and at predetermined intervals. A channel region having a trench having a specified depth, a drain region formed on the channel region except the trench, a conductive layer extending in the first direction at a predetermined interval on both sides of the channel region, and a data storage material formed on the drain region It may include.

Description

Vertical Type Memory Device and Fabrication Method Thereof}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a vertical memory device and a manufacturing method thereof.

Portable digital devices are not only increasing in popularity, but also demanding ultra-high integration, ultra-high speed, and ultra-low power of embedded memory devices to process large amounts of data at high speeds within a limited size.

In response to this demand, vertical memory devices have been actively researched. Recently, a vertical type memory device has been introduced into a resistive memory device that is exposed to a next generation memory device.

The resistive memory device selects a cell through an access device and changes the resistance state of a data storage material electrically connected thereto. The resistive memory device stores data by, for example, a phase change memory device, a resistive memory device, or a magnetoresistive memory device. Can be mentioned.

The access element of the resistive memory element may be a diode or a transistor. Particularly, since a transistor has an advantage that a threshold voltage can be controlled to be lower than that of a diode, an operation voltage can be reduced, and verticalization of a transistor becomes possible.

That is, since the diode needs to be supplied with a voltage of 1.1 V or more, there is a limit in lowering the operating voltage. In addition, when a diode is formed on the word line, the word line resistance is varied according to the position of each cell, and a word line bouncing phenomenon occurs.

In the past, transistors were formed in a horizontal structure and thus had limitations on the reduction ratio. However, vertical transistors provide advantages such as sufficient current driving force in a limited channel area.

Embodiments of the present invention provide a vertical memory device capable of suppressing a voltage drop caused by an external resistor and improving a word line bouncing phenomenon, and a method of manufacturing the same.

Another embodiment of the present invention provides a vertical memory device capable of ensuring a sufficient current driving force and a method of manufacturing the same.

In an embodiment, a vertical memory device may include a common source region; A source region formed on the common source region and extending in a first direction; A channel region formed on the source region and extending in the first direction, the channel region having a trench having a predetermined depth at predetermined intervals; A drain region formed on the channel region except for the trench; A conductive layer extending in the first direction spaced apart from each other by a predetermined interval on both sides of the channel region; And a data storage material formed on the drain region.

On the other hand, the vertical memory device manufacturing method according to an embodiment of the present invention comprises the steps of sequentially forming a first junction region, a channel region and a second junction region on the semiconductor substrate; Forming a line patterning structure by line patterning the second junction region, the channel region, and a portion of the first junction region in a first direction; Forming a first insulating film spacer and a conductive layer on an outer wall of the line patterning structure; Forming a second insulating film on the entire structure and planarizing the second bonding region and the conductive layer to expose the second insulating layer; Removing the exposed conductive layer to a specified depth and embedding a third insulating film; And patterning a portion of the second junction region and the channel region in a second direction perpendicular to the first direction.

In another aspect, a method of manufacturing a vertical memory device according to an embodiment of the present invention may include sequentially forming a first junction region, a channel region, a second junction region, a heating material, and a sacrificial layer on a semiconductor substrate; Forming a line patterning structure by line patterning a portion of the sacrificial layer, the heating material, the second junction region, the channel region, and the first junction region in a first direction; Forming a first insulating film spacer and a conductive layer on an outer wall of the line patterning structure; Forming a second insulating film on the entire structure and planarizing the exposed portion of the sacrificial layer and the conductive layer; Removing the exposed conductive layer to a specified depth and embedding a third insulating film; Patterning a portion of the sacrificial layer, the heating material, the second junction region and the channel region in a second direction perpendicular to the first direction; And forming a data storage material at a location where the sacrificial layer is removed.

According to this technology, a vertical transistor can be introduced to reduce the operating voltage while minimizing the cell size.

In addition, the adoption of the common source structure not only suppresses the voltage drop caused by the external resistor but also reduces the source resistance, thereby solving the word line bouncing phenomenon.

In addition, as the adjacent cells controlled by the same word line share the channel region, the current driving force can be sufficiently secured while the transistor is turned on.

1 to 7 are views for explaining a method of manufacturing a vertical memory device according to an embodiment of the present invention;
8 to 11 are perspective views of the vertical memory device shown in FIG.
12 is a cross-sectional view of a vertical memory device according to another embodiment of the present invention;
13 is a cross-sectional view of a vertical memory device according to still another embodiment of the present invention;
14 is a circuit diagram of a vertical memory device according to an embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. In each drawing, (a) is a cross-sectional view in a first direction (X direction), for example, a word line direction, (b) is a cross-sectional view in a second direction (Y direction), for example, a bit line direction, (c) Is a layout diagram.

1 to 7 are views for explaining a method of manufacturing a vertical memory device according to an embodiment of the present invention.

As shown in FIG. 1, the first junction regions 101 and 101A, the channel region 103, the second junction region 105, the heating material 107, and the sacrificial layer 109 are formed on the semiconductor substrate 100. To form sequentially. A portion of the sacrificial layer 109, the heating material 107, the second junction region 105, the channel region 103, and a portion of the first junction regions 101 and 101A is line-patterned in a first direction to form a line patterning structure. To form.

The semiconductor substrate 100 may be formed of a semiconductor material such as Si, SiGe, GaAs, and the like, and may be used as a structure of the same or a composite layer thereof.

In one embodiment of the present invention, the first junction regions 101 and 101A may be removed to a specified depth to form a common source region 101 and a switching source region 101A. In addition, the second junction region 105 may be a drain region.

In addition, according to the type of impurities to be injected into the first junction region 101 and 101A, the channel region 103 and the second junction region 105, the access element is divided into NMOS, PMOS, and I-MOS (Impact-ionization MOS) types. That is, a transistor can be formed. Particularly, it is preferable to form a transistor in the NMOS type in consideration of a threshold voltage and the like.

When forming an NMOS type transistor, N-type ions may be implanted into the first and second junction regions 101 / 101A and 105, and P-type ions may be implanted into the channel region 103. In the case of forming a PMOS transistor, P-type ions may be implanted into the first and second junction regions 101 / 101A and 105, and N-type ions may be implanted into the channel region 103.

On the other hand, when forming an I-MOS transistor, N + ions are implanted into the first junction regions 101 and 101A, P + ions are implanted into the second junction region 105, and P is implanted into the channel region 103. Implanting ions in which N-, P- and N- are combined, or injecting P + ions into the first junction regions 101 and 101A, and implanting N + ions into the second junction region 105, the channel region It is possible to implant ions in which P-, N-, P- and N- are combined into 103.

In addition, the first junction regions 101 and 101A may be divided into a common junction region 101 and a switching junction region 101A. In the present invention, the first junction regions 101 and 101A operate as the common source region 101 and the switching source region 101A.

In addition, the sacrificial layer 109 may be formed as a hard mask, and is removed in a subsequent process and replaced with a data storage material, for example, a resistance change material.

The heating material 107 may be formed using a metal, an alloy, a metal oxynitride, or a conductive carbon compound, for example, W, Cu, TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN , WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN, TaAlN, Ti, W, Mo, Ta, TiSi, TaSi, TiW, TiON, TiAlON, WON, TaON and the like, but is not limited thereto.

Although not shown, a silicide layer may be further formed on the heating material 107, and the heating material 107 may be formed of two or more conductive layers.

The silicide layer may be formed using, for example, a material such as Ti, Co, Ni, W, Pt, Pb, Mo, Ta, but is not limited thereto.

FIG. 1C shows a layout diagram of the portion of the second bonding region 105.

Next, the gate oxide film 111 and the conductive layer 113 are formed on the entire structure where the line patterning structure is formed. The conductive layer 113 operates as a gate electrode, that is, a word line.

In an embodiment of the present invention, the gate oxide layer 111 may be formed of a single layer or a composite layer of oxides or nitrides such as Si, Ta, Ti, BaTi, BaZr, Zr, Hf, La, Al, Y, ZrSi, or the like. Can be.

In addition, the conductive layer 113 may include W, Cu, TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN, TaAlN, Ti, W, Mo, It may be formed of Ta, TiSi, TaSi, TiW, TiON, TiAlON, WON, TaON and the like, but is not limited thereto.

As shown in FIG. 2C, it can be seen that the conductive layer 113 serving as the gate electrode material is formed on both sides of the second junction region 105.

Next, as shown in FIG. 3, the gate oxide layer 111 and the conductive layer 113 are left on the sidewalls of the line patterning structure by the spacer etching process, and the second insulating layer 115 is formed on the entire structure. Planarization is performed so that the tops of the sacrificial layer 109 and the conductive layer 113 are exposed.

In FIG. 4, the exposed conductive layer 113 is recessed to a predetermined depth, preferably, above the height of the channel region 103, and then the third insulating film 117 is embedded in the recess portion.

When the conductive layer 113 is recessed, the first junction regions 101 and 101A, the channel region 103 and the second junction region 105 are controlled by controlling the channel regions 103 to a height that may overlap each other. And the conductive layer 113 operates as a vertical transistor.

Next, as shown in FIG. 5, a portion of the sacrificial layer 109, the heating material 107, the second bonding region 105, and the channel region 103 in the second direction is patterned, and the cell in the second direction is patterned. Insulate the liver. After the fourth insulating film 119 is formed over the entire structure, the top of the sacrificial layer 109 is planarized to be exposed.

At this time, since the channel region 103 is not fully patterned and etched to a predetermined depth, cells sharing the word line can also share the channel region 103. Therefore, when the word line is in the off state, neighboring cells may be electrically shorted, and when the transistor connected to the specific word line is turned on, the channel resistance may be reduced to improve the current driving capability.

6 illustrates a state in which the sacrificial layer 109 is removed and the data storage material 123 is formed on the removed portion.

In one embodiment of the present invention, after removing the sacrificial layer 109, the spacer 121 may be formed on the inner wall of the recessed portion, and then the inside thereof may be filled with the data storage material 123.

As the data storage material 123, materials applicable to a phase change memory device (PCRAM), a resistive memory device (ReRAM), a spin transfer memory device (STT-RAM), and a polymer memory device (PoRAM) may be used. For example, a material selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, As, S, Si, P, O, N, .

Thereafter, as shown in FIG. 7, the bit line 125 is formed on the data resistance material 123.

8 to 11 are structural views of the vertical memory device shown in FIG. 7, wherein FIG. 8 is a bird's eye view, FIG. 9 is a front perspective view, FIG. 10 is a side perspective view, and FIG. 11 is a plan view.

As shown in Figs. 8 to 11, all of the memory cells share the first junction regions 101 and 101A, that is, the source region. In addition, memory cells connected to the same word line 113 share the channel region 103.

Therefore, when the word line 113 and the bit line 125 are selected according to an externally input address and a specific transistor is turned on, the resistance component formed through the drain-channel-source can be reduced, so that even with a low current driving force. Reliable operation can be ensured.

At this time, the unselected bit lines can be controlled in a floating state to prevent current leakage through the unselected bit lines.

12 is a cross-sectional view of a vertical memory device according to another embodiment of the present invention.

The vertical memory device shown in FIG. 12 has a structure substantially the same as the vertical memory device shown in FIG. 7 except for the first junction regions 201 and 201A formed on the semiconductor substrate 200.

However, the present embodiment has shown an example in which the common junction region 201 and the switching junction region 201A constituting the first junction regions 201 and 201A are formed of different materials.

In addition, the common junction region 201 may be line-patterned in a second direction, that is, in a bit line direction perpendicular to the word line in the first direction.

13 is a cross-sectional view of a vertical memory device according to still another embodiment of the present invention.

As shown in FIG. 13, after the first junction regions 101 and 101A, the channel region 103 and the second junction region 105 are sequentially formed on the semiconductor substrate 100, the first direction (word Line patterning) to form a line patterning structure.

Thereafter, the first insulating layer 111 and the conductive layer 113 are formed on the entire structure, and then a spacer etching process is performed to leave the first insulating layer 111 and the conductive layer 113 only on the sidewalls of the line patterning structure. . Then, the second insulating film 115 is formed on the entire structure and planarized to expose the upper ends of the second bonding region 105 and the conductive layer 113.

The exposed conductive layer 113 is recessed to a predetermined depth, preferably the depth that the conductive layer 113 can cover the channel region 103, and the third insulating layer 117 is buried in the recess portion.

In addition, a portion of the second junction region 105 and the channel region 103 is etched in the second direction (bit line direction), and the fourth insulating layer 119 is embedded in the etching portion.

The structure so far is similar to the structure of the vertical memory element shown in FIG.

However, in the present embodiment, after forming the vertical structure transistors sharing the source regions 101 and 101A and the channel region 103 in the above-described manner, the transistors and the data storage materials are connected through the contacts. The explanation is as follows.

Referring to FIG. 13 again, an insulating layer 301 is formed on the entire structure, and contact holes having a specified diameter are formed to expose the upper end of the second junction region 105.

Thereafter, the conductive material layers 303 and 305 and the data storage material 307 having a predetermined depth are buried in the contact hole, and then a bit line 309 is formed on the data storage material 307.

Here, the conductive material layers 303 and 305 may include a contact plug 303 and a heating material 305. In addition, the data storage material 307 may be configured such that a spacer is formed on the outer circumference thereof.

Although the above-described vertical memory devices having various structures have a structure in which bit lines are patterned in line type, the bit lines can be patterned in island type, and in this case, interference between cells can be suppressed. There is an advantage.

14 is a circuit diagram of a vertical memory device according to an embodiment of the present invention.

Referring to FIG. 14, it can be seen that a plurality of memory cells are formed to be connected between a bit line and a word line. In addition, each memory cell is formed to have a common source line CSL.

When the specific word line WLn and the bit line BLn are selected and the transistor A is selected, the unselected bit line is controlled to the floating state. Since each memory cell shares a channel region, when the unselected bit line is controlled to the ground potential, leakage current may occur through the unselected bit line. However, as shown in FIG. 14, the floating state control enables a reliable operation even with a low current driving force without sharing current while sharing a channel region.

As described above, in the present invention, a transistor is used as an access element in manufacturing a vertical memory element. In addition, source resistance can be reduced by allowing all cells, or at least cells connected to the same bit line, to share the source line.

In addition, by allowing the cells connected to the same word line to share the channel region, a stable and reliable operation is possible even with a low current driving force, thereby lowering the operating voltage.

Meanwhile, the case in which the vertical memory device is formed as a single layer has been described. However, the vertical memory device according to the present invention may be formed in a stacked type, that is, a multi level stack (MLS) structure. In this case, the cell structures shown in FIG. 7, 12, or 13 may be sequentially stacked in the same order, may be mirror-symmetrically stacked with respect to the bit lines, or may be mirror-symmetrically formed with respect to the source lines. Its structure allows for application and modification.

Thus, those skilled in the art will appreciate that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100: semiconductor substrate
101, 101A, 201, 201A: first junction region
103: channel area
105: second junction region
107, 305: heating material
109: sacrificial layer
111: first insulating film
113: conductive layer
115: second insulating film
117: third insulating film
119: fourth insulating film
121: Spacer
123, 307: data storage materials
125, 309: bit line
301: insulation layer
303: Contact Plug

Claims (23)

Common source region;
A source region formed on the common source region and extending in a first direction;
A channel region formed on the source region and extending in the first direction, the channel region having a trench having a predetermined depth at predetermined intervals;
A drain region formed on the channel region except for the trench;
A conductive layer extending in the first direction spaced apart from each other by a predetermined interval on both sides of the channel region; And
A data storage material formed on the drain region;
Vertical memory device comprising a. The method of claim 1,
The common source region may be a layer type extending in the first direction and a second direction perpendicular to the first direction. The method of claim 1,
The common source region may have a structure in which the common source region is line-patterned in a second direction perpendicular to the first direction. The method of claim 1,
And a heating material interposed between the drain region and the data storage material. 5. The method of claim 4,
And a contact plug interposed between the drain region and the heating material. The method of claim 1,
And a bit line interposed on the data storage material. The method according to claim 6,
And the vertical memory device is stacked at least twice on the bit line. The method according to claim 6,
The vertical memory device may be stacked in a symmetrical structure with respect to the bit line. The method according to claim 6,
The vertical memory device may be stacked in a symmetrical structure with respect to the common source region. The method of claim 1,
The data storage material is a vertical memory device that is a resistance change material. Sequentially forming a first junction region, a channel region, and a second junction region on the semiconductor substrate;
Forming a line patterning structure by line patterning the second junction region, the channel region, and a portion of the first junction region in a first direction;
Forming a first insulating film spacer and a conductive layer on an outer wall of the line patterning structure;
Forming a second insulating film on the entire structure and planarizing the second bonding region and the conductive layer to expose the second insulating layer;
Removing the exposed conductive layer to a specified depth and embedding a third insulating film; And
Patterning a portion of the second junction region and the channel region in a second direction perpendicular to the first direction;
Vertical memory device manufacturing method comprising a. The method of claim 11,
And the first junction region includes a common junction region and a switching junction region extending in the first direction by the line patterning. 13. The method of claim 12,
And the common junction region is formed as a layer type extending in the first direction and the second direction. 13. The method of claim 12,
The common junction region is formed by line patterning in the second direction. The method of claim 11,
And removing the conductive layer to a predetermined depth removes the remaining conductive layer so as to overlap the channel region. The method of claim 11,
And further comprising forming a data storage material electrically connected to the second junction region after patterning the second junction region and a portion of the channel region in a second direction perpendicular to the first direction. Type memory device manufacturing method. 17. The method of claim 16,
The data storage material is a vertical memory device manufacturing method is formed using a resistance change material. Sequentially forming a first junction region, a channel region, a second junction region, a heating material, and a sacrificial layer on the semiconductor substrate;
Forming a line patterning structure by line patterning a portion of the sacrificial layer, the heating material, the second junction region, the channel region, and the first junction region in a first direction;
Forming a first insulating film spacer and a conductive layer on an outer wall of the line patterning structure;
Forming a second insulating film on the entire structure and planarizing the exposed portion of the sacrificial layer and the conductive layer;
Removing the exposed conductive layer to a specified depth and embedding a third insulating film;
Patterning a portion of the sacrificial layer, the heating material, the second junction region and the channel region in a second direction perpendicular to the first direction; And
Forming a data storage material at a location where the sacrificial layer is removed;
Vertical memory device manufacturing method comprising a. The method of claim 18,
And the first junction region includes a common junction region and a switching junction region extending in the first direction by the line patterning. The method of claim 19,
And the common junction region is formed as a layer type extending in the first direction and the second direction. The method of claim 19,
The common junction region is formed by line patterning in the second direction. The method of claim 18,
And removing the conductive layer to a predetermined depth removes the remaining conductive layer so as to overlap the channel region. The method of claim 18,
The data storage material is a vertical memory device manufacturing method is formed using a resistance change material.

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