KR20130135632A - Light emitting diode having reliability improved electrode structure and method for fabricating the same - Google Patents

Abstract

A light emitting diode and a method of manufacturing the same are provided. The light emitting diode has a light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer. A first electrode is electrically connected to the first conductive semiconductor layer. A second electrode is electrically connected to the second conductive semiconductor layer. The second electrode includes a conductive laminate and a low resistance pattern formed on an upper surface and sidewalls of the conductive laminate.

Description

Light Emitting Diode Having Reliability Improved Electrode structure and Method for Fabricating the Same

The present invention relates to a semiconductor device, and more particularly, to a light emitting diode.

The light emitting diode includes an n-type semiconductor layer, a p-type semiconductor layer, and an active layer disposed between the n-type and p-type semiconductor layers, wherein when a forward electric field is applied to the n- Electrons and holes are injected into the active layer, and electrons injected into the active layer recombine with holes to emit light.

Some of the materials forming the electrodes connected to the n-type semiconductor layer and the p-type semiconductor layer may be oxidized in contact with oxygen in the air. In this case, deterioration of device reliability can be caused.

An object of the present invention is to provide a light emitting diode having an improved electrode structure and a method of manufacturing the same.

According to an aspect of the present invention, there is provided a light emitting diode. The light emitting diode has a light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer. A first electrode is electrically connected to the first conductive semiconductor layer. A second electrode is electrically connected to the second conductive semiconductor layer. The second electrode includes a conductive laminate and a low resistance pattern formed on an upper surface and sidewalls of the conductive laminate.

According to an aspect of the present invention, there is provided an LED according to another aspect of the present invention. The light emitting diode has a light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer. A first electrode is electrically connected to the first conductive semiconductor layer. A second electrode is electrically connected to the second conductive semiconductor layer. The second electrode includes a conductive laminate and a low resistance pattern, which are sequentially stacked, and the low resistance pattern has a width larger than the largest width of the conductive laminate.

According to another aspect of the present invention, there is provided a method of manufacturing a light emitting diode. The manufacturing method includes forming a light emitting structure having a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer. A first electrode electrically connected to the first conductive semiconductor layer is formed. A second electrode electrically connected to the second conductive semiconductor layer is formed. Forming the second electrode includes forming a conductive laminate and forming a low resistance pattern on an upper surface and sidewalls of the conductive laminate. Forming the low resistance pattern may be performed using an electroless plating method.

According to the present invention, the low resistance pattern may be formed on the sidewalls of the conductive laminate as well as the top of the conductive laminate. In this case, at least a part of the sidewall of the conductive laminate including a material vulnerable to oxidation can be prevented from being oxidized, thereby improving device reliability. In addition, when the electroless plating method is used, the low resistance pattern can be formed only in a limited region.

1 is a layout showing a light emitting diode according to an embodiment of the present invention.
2A and 2B are cross-sectional views taken step by step along the cutting line II ′ of FIG. 1.
3A and 3B are cross-sectional views taken step by step along the cutting line II-II ′ of FIG. 1.
4 is a cross-sectional view illustrating a method of manufacturing a light emitting diode according to another embodiment of the present invention.
5 is a cross-sectional view illustrating a method of manufacturing a light emitting diode according to another embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms.

When a layer is referred to herein as being "on" another layer or substrate, it may be formed directly on another layer or substrate, or a third layer may be interposed therebetween. In the present specification, directional expressions of the upper side, the upper side, the upper side, and the like can be understood as meaning lower, lower (lower), lower, and the like. That is, the expression of the spatial direction should be understood in a relative direction, and it should not be construed as definitively as an absolute direction. In addition, in this specification, "first" or "second" should not be construed as limiting the elements, but merely as terms for distinguishing the elements.

Further, in the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like reference numerals designate like elements throughout the specification.

1 is a layout showing a light emitting diode according to an embodiment of the present invention. 2A and 2B are cross-sectional views taken step by step along the cutting line II ′ of FIG. 1. 3A and 3B are cross-sectional views taken step by step along the cutting line II-II ′ of FIG. 1.

1, 2A, and 3A, a substrate 10 is provided. The substrate 10 may be formed of a material such as sapphire (Al ₂ O ₃ ), silicon carbide (SiC), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum nitride ₂ O ₃ ), or a silicon substrate. As an example, the substrate 10 may be a sapphire substrate. The substrate pattern 10a may be located in an upper surface of the substrate 10. The substrate pattern 10a may be formed by etching the upper surface of the substrate 10.

A buffer layer 21 may be formed on the substrate 10. In the case where the substrate 10 has a lattice constant different from that of the first conductivity type semiconductor layer, which will be described later, the buffer layer 21 is a layer formed to mitigate lattice mismatch between the substrate 10 and undoped GaN ) Layer.

The first conductive semiconductor layer 23 may be formed on the buffer layer 21. The first conductive semiconductor layer 23 may be a nitride-based semiconductor layer doped with an n-type dopant. For example, the first conductivity type semiconductor layer 23 may include a plurality of In _x Al _y Ga _1-xy N (0? X? 1, 0? _Y? 1, x + y? 1) . Thereafter, the active layer 25 may be formed on the first conductivity type semiconductor layer 23. The active layer 25 may be a layer of In _x Al _y Ga _1-xy N (0 x 1, 0 y 1, 0 x + y 1), and may be a single quantum well structure or a multiple quantum well structure multi-quantum well (MQW). As an example, the active layer 25 may have a single quantum well structure of an InGaN layer or an AlGaN layer, or a multiple quantum well structure of a multilayer structure of InGaN / GaN, AlGaN / (In) GaN, or InAlGaN / . The second conductive semiconductor layer 27 may be formed on the active layer 25. The second conductive semiconductor layer 27 may also be a nitride semiconductor layer or a layer doped with a p-type dopant. As an example, the second conductivity-type semiconductor layer 27 is a p-type diagram in an In _x Al _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1) layer. It may be a layer doped with Mg or Zn as a fund. In contrast, the second conductivity-type semiconductor layer 27 may include a plurality of In _x Al _y Ga _1-xy Ns having different compositions (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). It may be provided with layers.

The buffer layer 21, the first conductivity type semiconductor layer 23, the active layer 25, and the second conductivity type semiconductor layer 27 may form a light emitting structure, and they may be formed of a metal organic chemical vapor deposition method (Metal). Organic Chemical Vapor Deposition (MOCVD), Chemical Vapor Deposition (CVD), Plasma-Enhanced Chemical Vapor Deposition (PECVD), Molecular Beam Epitaxy (MBE), Hydride Vapor Growth It can be formed using various deposition or growth methods, including (Hydride Vapor Phase Epitaxy; HVPE).

A mesa etched region (MR) may be formed in the light emitting structure to expose the first conductive semiconductor layer 23. Thereafter, an insulating reflective layer 31 may be formed on the second conductive semiconductor layer 27. A current spreading conductive layer 35 may be formed on the second conductive semiconductor layer 27 to cover the insulating reflective layer 31. The current spreading conductive layer 35 may be a light transmissive conductive layer. As an example, ITO (Indium Tin Oxide), Ni / Au, or Cu / Au may be used.

An ohmic contact layer, a conductive reflection layer, a barrier layer, and a low resistance seed layer are formed on the first conductive semiconductor layer 23 and the current spreading conductive layer 35 exposed in the mesa etching region MR. After etching, the first conductive semiconductor layer CS1 and the second conductive laminate CS2 may be formed on the first conductive semiconductor layer 23 and the current spreading conductive layer 35, respectively. . The first conductive laminate CS1 includes a first ohmic contact pattern 41, a first reflective pattern 43, a first barrier pattern 45, and a first low resistance seed pattern 47a that are sequentially stacked. can do. The second conductive laminate CS2 includes a second ohmic contact pattern 51, a second reflective pattern 53, a second barrier pattern 55, and a second low resistance seed pattern 57a that are sequentially stacked. can do.

1, 2B, and 3B, first and second low resistance patterns 47b and 57b may be formed on the first and second conductive laminates CS1 and CS2, respectively. . Accordingly, a first electrode 40 and a first extension wiring 40e extending from the first electrode 40 are formed on the first conductive semiconductor layer 23 exposed in the mesa etching region MR. At the same time, a second electrode 50 and a second extension wiring 50e extending from the second electrode 50 can be formed on the current spreading conductive film 35. The first electrode 40 and the first extension line 40e may include the first conductive laminate CS1 and the first low resistance pattern 47b, and the second electrode 50 and The second extension wiring 50e may include the second conductive laminate CS2 and the second low resistance pattern 57b.

The low resistance patterns 47b and 57b may be formed on the sidewalls of the conductive stacks CS1 and CS2 as well as the top of the conductive stacks CS1 and CS2. In this case, at least a part of the sidewalls of the conductive stacks CS1 and CS2 including a material vulnerable to oxidation may be prevented from being oxidized, thereby improving device reliability. Also, in this case, since the cross-sectional areas of the low resistance patterns 47b and 57b are increased, the sheet resistance is reduced, and thus an improvement in current spreading can be expected. When the thickness Th1 of the low resistance patterns 47b and 57b on the conductive laminates CS1 and CS2 is set to 1, the low sidewalls of the conductive laminates CS1 and CS2 are reduced. The thickness Th2 of the resistance patterns 47b and 57b may have a ratio of about 0.3 to about 1.2, specifically about 0.5 to about 1. In addition, the width of each of the low resistance patterns 47b and 57b may be larger than the width of each of the conductive laminates CS1 and CS2.

In addition, the low resistance patterns 47b and 57b may be formed on sidewalls of the reflective patterns 43 and 53 included in the conductive stacks CS1 and CS2. In addition, the low resistance patterns 47b and 57b may cover the entire sidewalls of the conductive stacks CS1 and CS2 and may be formed on the current spreading conductive layer 35 or the first conductivity type semiconductor layer 23. Can be contacted. In this case, the voltage applied to the second electrode 50 and the second extension wiring 50e may be directly transmitted to the current spreading conductive layer 35 through the second low resistance pattern 57b. Therefore, current spreading can be further improved.

Meanwhile, the low resistance patterns 47b and 57b may absorb light emitted from the active layer 25. In order to solve this problem, the insulating reflective layer 31 has a width of the second electrode 50 below the second electrode 50, that is, a width W1 of the second low resistance pattern 57b provided therein. It may have a larger width W2. In addition, the insulating reflective layer 31 may extend below the second extension wiring 50e, that is, the width of the second extension wiring 50e, that is, the second low resistance pattern 57b of the second extension wiring 50e. It may have a width greater than the width. The insulating reflective layer 31 reflects the light emitted from the active layer 25, so that the light emitted from the active layer 25 is the second electrode 50 or the second extension wire 50e. 2 can be prevented from being absorbed by the low resistance pattern 57b. In addition, the light reflected from the insulating reflective layer 31 may be more likely to be emitted to a region where the second electrode 50 and the second extension wiring 50e are not formed, thereby improving light extraction efficiency. Can be.

As described above, the insulating reflective layer 31 may be positioned in the vertical lower region of the second electrode 50 and the vertical lower region of the second extension line 50e. At this time, the insulating reflective layer 31 may block an electric field in the vertically downward direction of the second electrode 50 and the second extension wiring 50e due to its insulating property. As a result, current crowding can be relaxed and current spreading can be improved.

The insulating reflective layer 31 may be a distributed bragg reflector (DBR), in which a pair of insulating films having different refractive indices are alternately stacked. In this case, the refractive index and the optical thickness of each of the insulating layers constituting the DBR may be adjusted to effectively reflect the light emitted from the active layer 25. The insulating layers constituting the DBR include SiO ₂ (n = 1.4), Al ₂ O ₃ (n = 1.6), SiN _x (0.5 <x <1.8, n = 2.05 to 2.25), and TiO ₂ (n = 2.1). It may be a pair of insulating films selected from the group consisting of.

Forming the low resistance patterns 47b and 57b may be performed by using the low resistance seed patterns 47a and 57a as a seed layer and using an electroless plating method. For example, the substrate on which the low resistance seed patterns 47a and 57a are formed may be disposed in an aqueous metal salt solution, and metal ions in the aqueous metal salt solution may be reduced to form a metal layer on the low resistance seed patterns 47a and 57a. The low resistance patterns 47b and 57b may be deposited.

The reflective patterns 43 and 53 are layers having a higher reflectance than the low resistance patterns 47b and 57b and may be Al, Al alloys, Ag, Ag alloys, or a composite layer thereof. As an example, the reflective patterns 43 and 53 may be layers having a higher reflectance than the low resistance patterns 47b and 57b in the visible and ultraviolet regions. In detail, the reflective patterns 43 and 53 may be Al layers. The low resistance patterns 47b and 57b are layers having a lower resistance than the reflective patterns 43 and 53 and may be Au or Au alloy layers. The low resistance seed patterns 47a and 57a may also be Au or Au alloy layers. When the low resistance patterns 47b and 57b are Au or Au alloy layers of a noble metal, the electroless plating method may be used to form the low resistance patterns 47b and 57b only in a limited region as described above. The consumption of Au can be greatly reduced, resulting in lower process costs.

The ohmic contact patterns 41 and 51 are layers for ohmic contact with the first conductive semiconductor layer 23 and / or the second conductive semiconductor layer 27 below. , Ti, Ti alloy, Rh, Rh alloy, W, W alloy, Pt, Pt alloy, or a composite layer thereof. As an example, the ohmic contact patterns 41 and 51 may be a Cr layer. The ohmic contact patterns 41 and 51 may be formed to a thickness of about 1 to 50 nm. For example, the ohmic contact patterns 41 and 51 may be formed to a thickness of about 10 nm. The ohmic contact patterns 41 and 51 may serve as an adhesion layer for stably bonding the reflective patterns 43 and 53 on the lower layer.

The barrier patterns 45 and 55 may reduce agglomeration or void formation due to particle migration between the reflective patterns 43 and 53 and the low resistance patterns 47b and 57b. Therefore, the reflective characteristics of the reflective patterns 43 and 53 may be maintained in a good state. The barrier patterns 45 and 55 are high melting point metal films having higher melting points than the reflective patterns 43 and 53, and include Ti, Ti alloys, W, W alloys, Cr, Cr alloys, Ni, Ni alloys, Mo, Mo alloy, Pt, Pt alloy, or a composite layer thereof. As an example, the first barrier pattern 45 may include a first lower barrier pattern 45a and a first upper barrier pattern 45b, and the second barrier pattern 55 may include a second lower barrier pattern. 55a and the second upper barrier pattern 55b may be provided. As such, when the barrier patterns 45 and 55 are multiple layers, film peeling due to tension may be suppressed. In detail, the lower barrier patterns 45a and 55a may be Cr layers, and the upper barrier patterns 45b and 55b may be Ni layers.

In some cases, the ohmic contact patterns 41 and 51 and the barrier patterns 45 and 55 may be omitted. In addition, although the first electrode 40 and the second electrode 50 have been described as having the same layer structure for the convenience of the process, the present invention is not limited thereto and may have different structures.

4 is a cross-sectional view illustrating a method of manufacturing a light emitting diode according to another embodiment of the present invention. The manufacturing method according to the present embodiment is similar to the manufacturing method described with reference to FIGS. 1, 2A, 2B, 3A, and 3B except as described below.

Referring to FIG. 4, an ohmic contact layer, a conductive reflective layer, a barrier layer, and a low layer are formed on the first conductive semiconductor layer 23 and the current spreading conductive layer 35 exposed in the mesa etching region MR. After the resistance seed layer is formed, it is etched to form a first conductive laminate CS1 and a second conductive laminate CS2 on the first conductive semiconductor layer 23 and the current spreading conductive layer 35. Each can be formed. The first conductive laminate CS1 includes a first ohmic contact pattern 41, a first reflective pattern 43, a first barrier pattern 45, and a first low resistance seed pattern 47a that are sequentially stacked. can do. The second conductive laminate CS2 includes a second ohmic contact pattern 51, a second reflective pattern 53, a second barrier pattern 55, and a second low resistance seed pattern 57a that are sequentially stacked. can do.

The first and second conductive laminates CS1 and CS2 form a positive photoresist pattern on the first conductive semiconductor layer 23 and the current spreading conductive layer 35, and then The ohmic contact layer, the conductive reflective layer, the barrier layer, and the low resistance seed layer may be sequentially stacked, and then lifted off the photoresist pattern. As a result, lower surfaces of the first and second conductive laminates CS1 and CS2 may be formed to have a smaller width than upper surfaces. In detail, the cross-sections of the conductive stacks CS1 and CS2 may be inverted trapezoids similar to those shown. Next, first and second conductive stacks CS1 and CS2 may be formed on the first and second conductive stacks CS1 and CS2. Second low resistance patterns 47b and 57b may be formed, respectively. The low resistance patterns 47b and 57b may be formed on the sidewalls of the conductive stacks CS1 and CS2 as well as the top of the conductive stacks CS1 and CS2. In this case, the low resistance patterns 47b and 57b may be formed on the lower sidewalls of the first and second conductive stacks CS1 and CS2 as compared with the upper sidewalls. As a result, the widths W1 of the first and second electrodes 40 and 50 may be reduced compared to those described with reference to FIGS. 1, 2A, 2B, 3A, and 3B. Accordingly, the width W2 of the insulating reflective film 31 can also be reduced compared to that described with reference to FIGS. 1, 2A, 2B, 3A, and 3B. Accordingly, the light emitting region can be relatively large, and thus the light emitting efficiency can be improved. In this case, the width of each of the low resistance patterns 47b and 57b may be larger than that of each of the conductive laminates CS1 and CS2.

5 is a cross-sectional view illustrating a method of manufacturing a light emitting diode according to another embodiment of the present invention. The manufacturing method according to the present embodiment is similar to the manufacturing method described with reference to FIGS. 1, 2A, 2B, 3A, and 3B except as described below.

Referring to FIG. 5, in the first electrode 40, the upper surface 43_u of the first reflective pattern 43 may have the same level as or higher than the upper surface 25_u of the active layer. In addition, the upper surface 43_u of the first reflective pattern may have the same level as or higher than the upper surface 27_u of the second conductive semiconductor layer, and further, the upper surface 30_u of the current spreading conductive layer.

As such, by forming a large portion of the first electrode 40 as the first reflective pattern 43, the ratio of the first low resistance pattern 47b to the first electrode 40 may be reduced. . As a result, the amount of Au or Au alloy forming the first low resistance pattern 47b can be reduced, which can be advantageous for reducing manufacturing costs.

In this case, the first low resistance pattern 47b may expose at least a portion of the sidewall of the first conductive laminate CS1. In detail, at least a lower sidewall of the first reflective pattern 43 may be exposed. As a result, the light traveling from the active layer 25 toward the first electrode 40 may be increased to be reflected to the outside of the exposed sidewall of the first reflective pattern 43. In addition, the light traveling from the active layer 25 toward the first electrode 40 decreases the probability of encountering the first low resistance pattern 47b and thus absorbs light due to the first low resistance pattern 47b. It can be reduced so that the light emission efficiency can be further improved.

In the present exemplary embodiment, the second electrode 50 may have the same structure as the first electrode 40.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, This is possible.

10: substrate 10a: substrate pattern
21: buffer layer 23: first conductive semiconductor layer
25: active layer 27: second conductive semiconductor layer
30: current spreading conductive film 40, 50: electrode
41, 51: ohmic contact pattern 43, 53: reflection pattern
45, 55: barrier pattern 47a, 57a: low resistance seed pattern
47b, 57b: low resistance pattern MR: mesa etching region

Claims (29)

A light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer;
A first electrode electrically connected to the first conductive semiconductor layer; And
A second electrode electrically connected to the second conductivity type semiconductor layer,
The second electrode includes a conductive laminate and a low resistance pattern formed on an upper surface and sidewalls of the conductive laminate. The method of claim 1,
And an insulating reflective layer disposed between the second electrode and the second conductive semiconductor layer, wherein the insulating reflective layer has a width equal to or greater than the width of the second electrode. 3. The method of claim 2,
An extension wiring extending from the second electrode onto the second conductivity type semiconductor layer;
The insulating reflective layer extends between the extension wiring and the second conductivity type semiconductor layer and has a width equal to or greater than the width of the extension wiring. 3. The method of claim 2,
The insulating reflective layer is a light emitting diode DBR. The method of claim 1,
When the thickness of the low resistance pattern on the conductive laminate is set to 1, the thickness of the low resistance pattern on the sidewall of the conductive laminate is 0.3 to 1.2. The method of claim 1,
The conductive laminate is a light emitting diode having a low resistance seed pattern. The method according to claim 6,
The low resistance seed pattern and the low resistance pattern is a light emitting diode of the same material. The method of claim 7, wherein
The low resistance seed pattern and the low resistance pattern is a light emitting diode of Au or Au alloy layer. The method according to claim 6,
The conductive laminate further comprises a reflective pattern positioned below the low resistance seed pattern. 10. The method of claim 9,
The conductive laminate further comprises an ohmic contact pattern positioned below the reflective pattern. 11. The method according to claim 9 or 10,
The conductive laminate further comprises a barrier pattern positioned between the reflective pattern and the low resistance pattern. The method of claim 1,
The light emitting structure includes a mesa etching region exposing the first conductivity type semiconductor layer,
The first electrode is electrically connected to the first conductive semiconductor layer exposed in the mesa etching region, and has a first low resistance formed on a top surface and sidewalls of the first conductive laminate and the first conductive laminate. With a pattern,
The second electrode is electrically connected on the second conductivity type semiconductor layer, and includes a second conductive laminate and a second low resistance pattern formed on an upper surface and sidewalls of the second conductive laminate;
The first conductive laminate has a first reflective pattern and a first low resistance seed pattern stacked in sequence,
The second conductive laminate has a second reflective pattern and a second low resistance seed pattern sequentially stacked, and an upper surface of the first reflective pattern has a level equal to or higher than an upper surface of the second conductive semiconductor layer. Light emitting diode. The method of claim 12,
The light emitting structure further includes a current spreading conductive film disposed between the second conductivity type semiconductor layer and the second electrode,
The upper surface of the first reflective pattern has the same level as or higher than the upper surface of the current spreading conductive film. The method according to claim 12 or 13,
The first low resistance pattern is not disposed on at least a lower sidewall of the first reflective pattern. The method of claim 1,
The conductive laminate has a light emitting diode having a larger upper surface than a lower surface thereof. A light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer;
A first electrode electrically connected to the first conductive semiconductor layer; And
A second electrode electrically connected to the second conductivity type semiconductor layer,
The second electrode includes a conductive laminate and a low resistance pattern, which are sequentially stacked, and the low resistance pattern has a width larger than the largest width of the conductive laminate. 17. The method of claim 16,
An insulating reflective layer disposed between the second electrode and the second conductive semiconductor layer; And
A current spreading layer disposed between the insulating reflective layer and the second electrode and extending onto the second conductive semiconductor layer,
The width of the insulating reflective layer is larger than the width of the low resistance pattern. 17. The method of claim 16,
The conductive laminate is a light emitting diode having an ohmic contact pattern, a reflection pattern, a barrier pattern and a low resistance seed pattern stacked in sequence. 17. The method of claim 16,
The light emitting structure includes a mesa etching region exposing the first conductivity type semiconductor layer,
The first electrode is electrically connected to the first conductive semiconductor layer exposed in the mesa etching region, and has a first low resistance formed on a top surface and sidewalls of the first conductive laminate and the first conductive laminate. With a pattern,
The second electrode is electrically connected on the second conductivity type semiconductor layer, and includes a second conductive laminate and a second low resistance pattern formed on an upper surface and sidewalls of the second conductive laminate;
The first conductive laminate has a first reflective pattern and a first low resistance seed pattern stacked in sequence,
The second conductive laminate has a second reflective pattern and a second low resistance seed pattern stacked in sequence,
The upper surface of the first reflective pattern has the same level as or higher than the upper surface of the second conductive semiconductor layer. 20. The method of claim 19,
The first low resistance pattern is not disposed on at least a lower sidewall of the first reflective pattern. 17. The method of claim 16,
The conductive laminate has a light emitting diode having a larger upper surface than a lower surface thereof. Providing a light emitting structure comprising a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer;
Forming a first electrode electrically connected on the first conductivity type semiconductor layer; And
Forming a second electrode electrically connected to the second conductivity type semiconductor layer,
The forming of the second electrode includes forming a conductive laminate and forming a low resistance pattern on an upper surface and sidewalls of the conductive laminate. The method of claim 22,
Forming the low resistance pattern is performed using an electroless plating method. 24. The method of claim 23,
The low resistance pattern is a light emitting diode manufacturing method of Au or Au alloy layer. The method of claim 22,
Before forming the conductive laminate, further comprising forming an insulating reflective layer on the second conductive semiconductor layer,
The insulating reflective layer is formed to have a larger width than the width of the second electrode light emitting diode manufacturing method. The method of claim 22,
The conductive laminate is a light emitting diode manufacturing method comprising an ohmic contact pattern, a reflection pattern, a barrier pattern and a low resistance seed pattern stacked in sequence. The method of claim 22,
Forming a mesa etching region exposing the first conductivity type semiconductor layer in the light emitting structure,
A first conductive laminate and a second conductive laminate are respectively formed on the first conductive semiconductor layer and the second conductive semiconductor layer exposed in the mesa etching region,
Forming a first low resistance pattern on the top surface and sidewalls of the first conductive laminate to form the first electrode, and forming a second low resistance pattern on the top surface and the sidewalls of the second conductive laminate Forming the second electrode, the first conductive laminate has a first reflective pattern and a first low resistance seed pattern stacked in sequence,
The second conductive laminate has a second reflective pattern and a second low resistance seed pattern stacked in sequence,
The upper surface of the first reflective pattern has a level equal to or higher than the upper surface of the second conductive semiconductor layer. 28. The method of claim 27,
And forming the first low resistance pattern such that the first low resistance pattern is not positioned on at least a lower sidewall of the first reflective pattern. The method of claim 22,
The conductive laminate is a light emitting diode manufacturing method of the lower surface thereof is formed narrower than the upper surface thereof.

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