KR20130053018A - Method for manufacturing semiconductor device - Google Patents

Abstract

The present invention provides a storage node contact plug and an active area by making the area of the active area in contact with the storage node contact plug wider than the area of the active area in contact with the bitline contact plug in order to increase the contact area between the active area and the storage node contact plug. Provided is a method of manufacturing a semiconductor device that reduces resistance failure of the liver.

Description

Method for Manufacturing Semiconductor Device {Method for Manufacturing Semiconductor Device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of improving resistance failure of a cell transistor.

A semiconductor memory device is a device for storing information such as data and instructions of a program. The semiconductor memory device is largely divided into a DRAM and an SRAM. A DRAM is an abbreviation of Dynamic Random Access Memory, which is a memory capable of reading stored information and storing other information. It can read and write information, but it can be periodically Is a memory in which the stored contents disappear unless the information is rewritten. As such, the DRAM needs to keep refreshing, but it is widely used as a large-capacity memory because the price per memory cell is low and the degree of integration can be increased.

A semiconductor memory device is a device for storing information such as data and instructions of a program. The semiconductor memory device is largely divided into a DRAM and an SRAM. A DRAM is an abbreviation of Dynamic Random Access Memory, which is a memory capable of reading stored information and storing other information. It can read and write information, but it can be periodically Is a memory in which the stored contents disappear unless the information is rewritten. As such, the DRAM needs to keep refreshing, but it is widely used as a large-capacity memory because the price per memory cell is low and the degree of integration can be increased.

As semiconductor devices have been increasingly integrated, semiconductor chip sizes have been reduced, thereby reducing the size of semiconductor devices formed in chips. Particularly, the reduction in the size of the active area and the gate is affecting the process of forming a semiconductor device such as a capacitor and a bit line. Particularly, the area of the storage node and the bit line contact formed in the active region between the gates is gradually reduced to cause a difficulty in forming a contact and a problem of deteriorating electrical characteristics.

1 and 2 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

1 and 2, an isolation layer 110 defining an active region 100 is formed on a semiconductor substrate. Specifically, the active region 100 is defined by being arranged in an island type having a bar shape in an oblique direction, and forms the device isolation layer 110 in an area between the active regions 100.

The gate 120 intersecting in the direction perpendicular to the length direction of the active region 110 is formed. The gate 120 divides one active region 100 into three parts, and each SNC 130 is formed at both outer regions of the active region 100 exposed between the gates 120. In the center of the active region 100, a BLC 140 is formed.

In addition, the BLC 140 is connected to form a bit line 150 of a line type perpendicular to the gate 120. Here, when the active region 100 having the 6F2 structure is arranged in an oblique line, misalignment defects between the BLC 140 and the bit line 150 formed on the active region 100 (FIG. 1A) Region) and a contact area with the SNC 130 formed on the upper portion of the active region 100 is reduced, resulting in poor resistance (region B in FIG. 2).

In order to solve the above-mentioned problems, the present invention provides an area of the active area in contact with the storage node contact plug to be larger than the area of the active area in contact with the bitline contact plug in order to increase the contact area between the active area and the storage node contact plug. The present invention provides a method of manufacturing a semiconductor device that reduces the resistance resistance between the storage node contact plug and the active region by making it wide.

The present invention provides a method of forming a silicon oxynitride layer pattern and a first polysilicon layer pattern on a semiconductor substrate including a lower layer, and forming an SOC layer and a SION layer on the semiconductor substrate, the first polysilicon layer pattern, and a silicon oxynitride layer pattern. Forming a second polysilicon layer pattern by etching the SION layer, the SOC layer, the silicon oxynitride layer pattern, and the first polysilicon layer pattern using a cutting mask; and forming the second polysilicon layer pattern. The method may further include forming an active region by etching the lower layer and the semiconductor substrate.

Preferably, the lower layer includes a pad oxide film, a pad nitride film, a carbon film, a silicon oxynitride film, and a polysilicon film.

Preferably, the cutting mask is characterized in that it comprises an oval exposure area to separate the pattern of the first polysilicon film.

Preferably, the elliptical exposure area is characterized in that the diagonal direction.

Preferably, the area or size of the active area connected to the storage node contact plug is wider or larger than the area of the active area connected to the bit line contact plug.

The present invention provides a storage node contact plug and an active area by making the area of the active area in contact with the storage node contact plug wider than the area of the active area in contact with the bitline contact plug in order to increase the contact area between the active area and the storage node contact plug. It has the advantage of reducing poor resistance to liver.

1 and 2 are a plan view and a photograph showing a method of manufacturing a semiconductor device according to the prior art.
3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
4 to 7 are plan views illustrating a method of manufacturing a semiconductor device according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Referring to FIG. 3A, the pad oxide layer 310, the pad nitride layer 320, the pad nitride layer 320, the carbon layer 330, the silicon oxynitride layer SION, and the polysilicon layer are formed on the semiconductor substrate 300. ) Are stacked sequentially.

Next, the polysilicon film and the silicon oxynitride film are etched by an exposure and development process using an etching mask defining an active region to form the first polysilicon film pattern 350 and the silicon oxynitride film pattern 340. Here, the first polysilicon film pattern 350 and the silicon oxynitride film pattern 340 have a 6F2 structure arranged in a bar shape in an oblique direction, and it is preferable to refer to FIG. 4 for a specific shape.

Referring to FIG. 3B, an SOC (360, Spin On Carbon) film and a SION film 370 are sequentially formed on the first polysilicon film pattern 350 and the first silicon oxynitride film pattern 340.

Referring to FIG. 3C, after the photosensitive film is formed on the SION film 370, the photosensitive film pattern 380 is formed by an exposure and development process using a cutting mask. Using the photoresist pattern 380 as an etch mask, the SION layer 370, the SOC layer 360, the first polysilicon layer pattern 350, and the first silicon oxynitride layer pattern 340 are etched to form a SION layer pattern (not shown). , An SOC film pattern (not shown), a second polysilicon film pattern 355, and a second silicon oxynitride film pattern 345 are formed. Thereafter, the SION film pattern and the SOC film pattern are removed. Here, the cutting mask includes an elliptic exposure area C (open area) separating the first polysilicon layer pattern 350 as shown in FIG. 5.

Referring to FIG. 3D, a carbon film (330 of FIG. 3C), a pad nitride film (320 of FIG. 3C), and a pad oxide film are formed by using the second polysilicon film pattern 355 and the second silicon oxynitride film pattern 345 as etching masks. (310 in FIG. 3C) and the semiconductor substrate (300 in FIG. 3C) are etched to form a carbon film pattern 335, a pad nitride film pattern 325, a pad oxide film pattern 315, and an active region 300 ', 350' of FIG. To complete. Here, it is preferable to refer to FIG. 6 for a specific shape of the active region 350 ′, and the contact area of the active region 350 ′ connected to the storage node contact plug SNC is larger than that of the related art. It is preferable.

Referring to FIG. 7, an isolation layer 350 ″ defining an active region 350 ′ is provided on a semiconductor substrate, where the active region 350 ′ is an island having a bar shape in an oblique direction. Element arrangement film 350 " is provided in a region between the active regions 350 '. In this case, the contact area of the active region 350 ′ connected to the storage node contact plug may be larger than that of the conventional active region.

A buried gate 390 intersecting in the direction perpendicular to the longitudinal direction of the active region 350 ′ is provided. The buried gate 390 divides one active region 350 'into three parts, and each storage node contact plug 400 is formed at both outer regions of the active region 350' exposed between the buried gates 390. SNC) and a bit line contact plug 410 (BLC) is provided at the center of the active region 350 '.

The bit line 420 is connected to the bit line contact plug 410 and is formed in a line type in a direction perpendicular to the buried gate 390.

As described above, the present invention provides a storage node by making the area of the active area in contact with the storage node contact plug wider than the area of the active area in contact with the bitline contact plug in order to increase the contact area between the active area and the storage node contact plug. It has the advantage of reducing the poor resistance between the contact plug and the active region.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

Claims (5)

Forming a silicon oxynitride layer pattern and a first polysilicon layer pattern on a semiconductor substrate including a lower layer;
Forming an SOC film and a SION film on the semiconductor substrate, the first polysilicon film pattern, and the silicon oxynitride film pattern;
Etching the SION film, the SOC film, the silicon oxynitride film pattern, and the first polysilicon film pattern using a cutting mask to form a second polysilicon film pattern; And
Etching the lower layer and the semiconductor substrate using the second polysilicon layer pattern as an etching mask to form an active region
And forming a second insulating film on the semiconductor substrate. The method according to claim 1,
The lower layer may include a pad oxide film, a pad nitride film, a carbon film, a silicon oxynitride film, and a polysilicon film. The method according to claim 1,
And the cutting mask comprises an elliptical exposure area to separate the pattern of the first polysilicon film. The method according to claim 3,
The elliptical exposure area is a diagonal direction, the manufacturing method of a semiconductor device. The method according to claim 1,
The area or size of the active area connected to the storage node contact plug is wider or larger than the area of the active area connected to the bit line contact plug.

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