KR20130046675A - Printed circuit board and semiconductor package using thereof and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a base substrate, a die pad portion and a bonding pad portion formed on the base layer, a circuit board having a thin film plating layer formed of surface roughness, Ag or Pd on the bonding pad portion, a semiconductor package using the same, and a method of manufacturing the same. In addition, it is possible to reduce the manufacturing cost of the semiconductor package by not using the precious metal gold when forming the thin film plating layer, and to reduce the manufacturing cost by reducing the raw material and the time required for the plating process by forming the thin film plating layer. And it can achieve the effect of improving the process availability. In addition, as the surface roughness is formed, the surface area of the bonding pad portion is increased, thereby providing a semiconductor package having an effect of excellent bonding, molding material adhesion, solderability, and lamination quality during wire bonding.

Description

Printed circuit board and semiconductor package using same and manufacturing method

The present invention relates to a circuit board, a semiconductor package using the same, and a method of manufacturing the same.

Semiconductor packaging refers to a process in which individual chips made by a wafer process are electrically connected to be used as actual electronic components, and are sealed and packaged to protect against external shocks. It is called a package.

Typically, a single wafer is made of dozens or even hundreds of chips printed with the same electrical circuit. These individual chips cannot, by themselves, serve as electronic components. Therefore, it is necessary to make an electric cable connected to the outside in order to receive the electrical signal from the outside to deliver the electrical signal running inside the chip. In addition, chips contain very fine circuitry, which can be easily damaged by moisture, dust and external shocks. After all, the chip itself formed on the wafer surface is not a complete product until it is mounted on a circuit board (PCB) as an electronic component. Therefore, the packaging process is to finalize the chip to make electrical connections to the chip on the wafer and seal the packaging to withstand external shocks so that the chip can serve as a complete individual electronic device.

In a conventional semiconductor package, gold (Au) is used as a bonding wire when performing a wire bonding process for connecting a semiconductor chip and a lead frame. Accordingly, conventionally, as described in Korean Patent Application Publication No. 10-2009-0128983, No. 11, nickel (Ni) plating and gold (Au) plating are performed on the bonding surface of the substrate to bond the bonding wires with gold. Maintained.

However, the conventional semiconductor package having such a structure has a problem in that the manufacturing cost is increased due to the use of gold (Au), which is a precious metal, when the plating layer is formed on the bonding wire and the bonding surface.

Publication No. 10-2009-0128983

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to form a surface roughness on a bonding pad portion of a circuit board and to form a thin film plating layer made of Ag or Pd, thereby improving bonding strength with bonding wires. The present invention provides a circuit board, a semiconductor package using the same, and a method of manufacturing the same, which can improve and reduce manufacturing costs.

The circuit board of the present invention for solving the above problems, the base layer; A die pad part and a bonding pad part formed on the base layer; A thin film plating layer formed on the bonding pad part and made of Ag or Pd may be included, and surface roughness may be formed on an upper surface of the bonding pad part.

In the circuit board of the present invention, the roughness of the surface roughness is preferably formed in the range of 0.25 to 0.40 micrometers.

In the circuit board of the present invention, when the thin film plating layer is formed of Ag, the thickness thereof is preferably formed in the range of 0.005 to 2.000 micrometers.

In the circuit board of the present invention, when the thin film plating layer is formed of Pd, the thickness thereof is preferably formed in the range of 0.005 to 0.150 micrometers.

The circuit board of the present invention may further include a Ni thin film plating layer formed between the bonding pad portion and the thin film plating layer.

In the circuit board of the present invention, the Ni thin film plating layer is preferably formed to a thickness of 0.005 to 0.300 micrometers.

In the circuit board of the present invention described above, the die pad portion and the bonding pad portion may be formed including Cu.

The circuit board of the present invention, the solder ball pad formed on the base layer; The semiconductor device may further include a conductive via hole formed through the base layer, and at least one of the die pad part and the bonding pad part may be electrically connected to the solder ball pad through the conductive via hole.

The semiconductor package of the present invention for solving the above problems, the circuit board formed with a die pad portion and a bonding pad portion on the base layer; A semiconductor chip mounted on the die pad unit; Bonding wires connecting the semiconductor chip and the bonding pad unit; A molding part molding the semiconductor chip; It is formed on the bonding pad portion, and includes a thin film plating layer made of Ag or Pd, the surface roughness may be formed on the bonding pad upper surface.

In the semiconductor package of the present invention, the roughness of the surface roughness is preferably formed in the range of 0.25 to 0.40 micrometers.

In the semiconductor package of the present invention, when the thin film plating layer is formed of Ag, the thickness thereof is preferably formed in the range of 0.005 to 2.000 micrometers.

In the semiconductor package of the present invention, when the thin film plating layer is formed of Pd, the thickness thereof is preferably formed in the range of 0.005 to 0.150 micrometers.

The semiconductor package of the present invention may further include a Ni thin film plating layer formed between the bonding pad unit and the thin film plating layer.

In the semiconductor package of the present invention, the Ni thin film plating layer may be formed to a thickness of 0.005 to 0.300 micrometers.

In the semiconductor package of the present invention, the Pd thin film plating layer may be formed to a thickness of 0.005 to 0.150 micrometers.

In the above-described semiconductor package of the present invention, the bonding wire may be formed including Cu, and the die pad part and the bonding pad part may be formed including Cu.

In the semiconductor package of the present invention, the circuit board, a solder ball pad formed on the other surface of the base layer; The semiconductor device may further include a conductive via hole formed through the base layer and electrically connecting at least one of the die pad portion and the bonding pad portion to the solder ball pad.

In the circuit board manufacturing method of the present invention for solving the above problems, a die pad portion and a bonding pad portion are formed on a base layer, and the surface roughness is formed on the bonding pad portion, and the surface roughness is formed on the bonding pad portion. Ag or Pd in the plating may be formed, including forming a thin film plating layer.

In the circuit board manufacturing method of the present invention, the roughness of the surface roughness is preferably formed in the range of 0.25 to 0.40 micrometers.

In the circuit board manufacturing method of the present invention, when Ag is plated to form the thin film plating layer, the thickness thereof is preferably formed in the range of 0.005 to 2.000 micrometers.

In the circuit board manufacturing method of the present invention, in the case of forming the thin film plating layer by plating Pd, the thickness thereof is preferably formed in the range of 0.005 to 0.150 micrometers.

The circuit board manufacturing method of the present invention may further comprise forming a Ni thin film plating layer by plating Ni on the bonding pad portion between forming the surface roughness and forming the thin film plating layer.

In the circuit board manufacturing method of the present invention, the Ni thin film plating layer is preferably formed to a thickness of 0.005 to 0.300 micrometers.

In the circuit board manufacturing method of the present invention described above, forming the die pad portion and the bonding pad portion may include laminating a Cu layer on the base layer and patterning the Cu layer.

In the semiconductor package manufacturing method of the present invention for solving the above problems, the die pad portion and the bonding pad portion is formed on the base layer, the surface roughness is formed on the upper surface of the bonding pad portion, the bonding pad portion formed on the surface roughness Plated Ag or Pd to form a thin film plating layer, mounting a semiconductor chip on the die pad part, wire-bonding a bonding pad part on which the semiconductor chip and the thin film plating layer are formed, and wire-bonding the die pad part and the bonding. And molding a pad part, the semiconductor chip, and the bonding wire with a molding material. The method may further include forming a Ni thin film plating layer by plating Ni on the bonding pad portion between forming the surface roughness and forming the thin film plating layer.

In the method of manufacturing a semiconductor package of the present invention, the bonding wire may be formed including Cu.

In the method of manufacturing a semiconductor package of the present invention, forming the die pad portion and the bonding pad portion on the base layer may include laminating a Cu layer on the base layer and patterning the Cu layer.

According to the present invention, when the plating layer is formed on the bonding pad portion, gold (Au), which is an expensive precious metal, is not used, thereby reducing the manufacturing cost according to cost reduction.

In addition, according to the present invention, it is possible to use a bonding wire formed of copper (Cu) at the time of wire bonding, thereby further reducing the manufacturing cost.

In addition, according to the present invention, as the thin film plating layer formed on the bonding pad portion is formed thin, the plating process time can be shortened, the amount of raw materials can be reduced, and manufacturing cost reduction and process operation rate can be improved. It can be effective.

In addition, according to the present invention, by forming a thin film plating layer on the bonding pad portion, it is possible to suppress surface oxidation of the bonding pad portion due to heat applied during wire bonding, thereby providing an effect of providing a highly reliable semiconductor package. .

In addition, according to the present invention, by forming the surface roughness of the bonding pad portion, it is possible to increase the wire bonding bonding area, accordingly, the semiconductor package excellent in bonding, molding material adhesion, solderability, lamination quality during wire bonding It will also be able to provide an effect.

1 is a cross-sectional view showing a circuit board according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view of a semiconductor package manufactured using the circuit board of FIG. 1.
3 is a flowchart illustrating a method of manufacturing a circuit board and a semiconductor package according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it is to be understood that the contents described herein are only exemplary embodiments of the present invention, and that various equivalents and modifications may be substituted for them at the time of the present application. DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, well-known functions or constructions are not described in detail to avoid obscuring the subject matter of the present invention. The following terms are terms defined in consideration of functions in the present invention, and the meaning of each term should be interpreted based on the contents throughout the present specification. The same reference numerals are used for parts having similar functions and functions throughout the drawings.

1 is a cross-sectional view showing a circuit board according to an embodiment of the present invention.

Referring to FIG. 1, a circuit board 100 according to the present invention may be formed on a base layer 110, a die pad part 130, a bonding pad part 150, and a bonding pad part 150 formed on the base layer 110. It is formed including a plating layer 160 formed on. Here, the surface roughness 151 is formed on the upper surface of the bonding pad part 150, and the plating layer 160 is formed of the Ni thin film plating layer 161 and Ag or Pd on the bonding pad part 150 on which the surface roughness 151 is formed. The thin film plating layer 163 may be formed of a double layer structure sequentially formed. Meanwhile, although not shown in the drawing, the plating layer 160 of the present invention may have a structure in which the aforementioned Ni thin film plating layer 161 is omitted, that is, a single layer structure in which only a thin film plating layer made of Ag or Pd is formed.

In addition, the circuit board 100 of the present invention may be soldered with at least one of the soldering pad 190, the soldering pad 190, the die pad part 130, and the bonding pad part 150 formed under the base layer 110. The pad 190 may further include a conductive via hole 170 for electrically connecting the pad 190, and the surface roughness and the plating layer described above may be further formed on a surface exposed to the outside of the soldering pad 190.

The base layer 110 forms a body of the circuit board 100 and is preferably formed of an insulating material.

A copper foil layer may be formed on one or both surfaces of the base layer 110, and the die pad part 130 and the bonding pad part 150 may be formed by patterning the copper foil layer through a photolithography process. In addition, when the copper foil layer is formed not only on the upper portion of the base layer 110 but also on the lower portion, the soldering pad 190 may also be formed through the photolithography process described above.

The surface roughness 151 is formed on the bonding pad part 150, and the roughness Ra of the surface roughness 151 is preferably formed in the range of 0.25 to 0.40 micrometers. When the roughness Ra of the surface roughness 151 is formed to be less than 0.25 micrometer, the surface roughness loses its original purpose. For example, when the surface roughness Ra is formed to be small, the surface area is also reduced. As a result, the bonding force with the molding part is lowered in the semiconductor package manufacturing process, and as a result, the reliability of the semiconductor package is reduced. . On the other hand, when the surface roughness is formed to be larger than 0.49 micrometers, excessive roughness causes the molding material (for example, epoxy resin) to form the molding part in the package manufacturing process to spread on the surface of the circuit board, thereby degrading the wire bonding adhesion. . In addition, when the surface roughness is formed to be greater than 0.40 micrometers level, the grains forming the surface roughness to the side of the circuit board fall off in the form of a powder to cause contamination in the circuit board manufacturing process and semiconductor package manufacturing process. Therefore, the roughness Ra of the surface roughness 151 formed on the bonding pad part 150 is preferably formed in the range of 0.25 to 0.40 micrometers.

Meanwhile, the above-described surface roughness may be formed through a rough copper plating process, and copper sulfate plating process may be used as the plating process. The copper sulfate plating process is formed by electroplating in a copper sulfate (CuSO4 · H2O) solution. For example, the electroplating is performed in a copper sulfate plating solution having a copper ion concentration of 35 to 75 g / l and a sulfuric acid concentration of 90 to 150 g / l. Proceed by applying a current of 10 to 40 seconds to the bonding pad unit 150 with a current density of 7 to 15 ASD, wherein copper ions of copper sulfate plating are reduced to the bonding pad unit 150 to form the above-described surface roughness. Can be. However, this is just one example, and the surface roughness 151 may be formed on the bonding pad unit 150 of the present invention through all methods that are currently developed and commercialized or may be implemented according to future technology development.

When the surface roughness 151 is formed in the above-described bonding pad unit 150, as a result, as shown in FIG. 1, the surface roughness 151 is reflected in the plating layer 160 having a single layer structure or a double layer structure. do. Accordingly, it is possible to increase the wire bonding joint area in the future semiconductor package manufacturing, and as a result, it is possible to improve the bonding, molding material adhesion, solderability during wire bonding, and improve the lamination quality (lamination). .

Meanwhile, the circuit board 100 of the present invention may further include a conductive via hole 170 having a structure in which a conductive material is filled in a hole penetrating the base layer 110. The conductive via hole 170 of the present invention serves to electrically connect at least one of the die pad unit 130 and the bonding pad unit 150 with the soldering pad 190. The conductive via hole 170 may be formed by, for example, forming a hole in the base layer 110 through mechanical processing, laser drilling, or punching, and plating the inside of the hole. Alternatively, the hole may be formed in the base layer 110 and filled with a conductive material such as a conductive paste, but is not limited thereto.

The plating layer 160 is formed on the bonding pad unit 150 having the surface roughness 151 of the present invention, and the plating layer 160 is a plating layer replacing the conventional Au plating layer, and a wire bonding process in the subsequent semiconductor package manufacturing. Serves to prevent oxidation of the bonding pad portion 150 formed of Cu. In addition, when manufacturing a semiconductor package in the future, the bonding wire made of copper (Cu) and the bonding pad unit 150 serves to perform more firmly.

The plating layer 160 of the present invention may have a single layer structure in the form of a thin film plating layer made of Ag or Pd, or a double layer structure in which a Ni thin film plating layer 161 and a thin film plating layer 163 made of Ag or Pd are sequentially formed.

1. Plating layer 160 has a single layer structure

When the plating layer 160 is made of a thin film plating layer having a single layer structure made of Ag, the thickness thereof is preferably formed in the range of 0.005 to 2 micrometers. When the thickness of the thin film plating layer made of Ag is less than 0.005 micrometers, it is impossible to prevent oxidation of Cu, which is generally used in the bonding pad part 150, and as a result, the reliability of wire bonding in manufacturing a semiconductor package and thus the semiconductor This reduces the reliability of the package. Therefore, in consideration of the antioxidant effect and economic efficiency, the thickness of the single-layer thin film plating layer made of Ag is preferably formed within the range of 0.005 to 2 micrometers. Accordingly, by lowering the plating thickness of the plating layer 160, it is possible to further reduce the use of precious metal (Ag), thereby reducing the manufacturing cost.

When the plating layer 160 of the present invention is formed by plating Ag, the formation method may be made by a known method. That is, it will be said that those skilled in the art can select appropriately according to the characteristics of a manufacturing environment, such as a silver cyanide plating process and a well-known silver oxide plating process. For example, when the silver cyanide is formed through the plating process, the silver cyanide, an acidic silver plating solution, and other silver plating solutions and additives for the purpose of adjusting the plating solution are combined to combine the plating solutions, and the bonding pad unit 150 is formed. If the base layer 110 is partially or completely immersed in the plating solution and a constant current is applied, the plating layer 160 having a thickness of 0.005 to 2.0 micrometers can be formed. At this time, the plating thickness can be adjusted by the plating time and the amount of current applied. However, this is just one example and it can be said that a single layer structured thin film plating layer made of Ag can be formed by any method that is currently developed and commercialized or can be implemented according to future technological developments.

On the other hand, when the plating layer 160 is formed of a thin film plating layer having a single layer structure made of Pd, the thickness thereof is preferably thinly formed to a thickness of 0.005 to 0.150 micrometer. When the thickness of the thin film plating layer formed by plating Pd is less than 0.005 micrometer, it is impossible to prevent oxidation of Cu, which is generally used in the bonding pad part 150, and as a result, the reliability of wire bonding in manufacturing a semiconductor package may decrease. The reliability of the semiconductor package is reduced. Therefore, considering the antioxidant effect and economical efficiency, the thickness of the thin film plating layer 163 made of Pd is 0.005 to 0.150 micrometers. It is preferable to form in the range similar to the case of forming a thin film plating layer with Ag. Accordingly, by lowering the plating thickness of the plating layer 160, it is possible to further reduce the amount of precious metal (Pd) used, thereby reducing the manufacturing cost.

When Pd is plated to form a thin film plating layer, the formation method may be made by a known method. For example, Pd metal as a main component, conductive salt for stable plating, and other additives are put in a plating bath, and a current is applied while the base layer 110 on which the bonding pad part 150 is formed is partially or completely immersed in the plating bath. It can form by doing. In this case, the concentration of Pd is preferably 1.5 to 5.0 g / l, and a thin film plating layer made of Pd may be formed by applying a current for 10 to 50 seconds at 0.5 to 5 ASD. The thickness of the thin film plating layer formed at this time is formed in the range of about 0.005 to 0.150 micrometers, the thickness may be adjusted by adjusting the current or plating time. However, the above-described method is just one example, and it may be said that the thin film plating layer of the present invention may be formed of Pd by any method that is currently developed and commercialized or may be implemented according to future technology development.

2. Plating layer 160 has a double layer structure

As shown in the drawing, the plating layer 160 of the present invention may have a double layer structure in which a Ni thin film plating layer 161 and a thin film plating layer 163 made of Ag or Pd are sequentially formed.

The Ni thin film plating layer 161 is moved to the thin film plating layer 163 made of Ag or Pd due to diffusion of copper (Cu) constituting the bonding pad unit 150 by the heat applied during the wire bonding process during the semiconductor package manufacturing. It prevents the phenomenon. This is because when copper (Cu) is diffused into the thin film plating layer 163 described above, wire bonding adhesion may be impaired as the oxide is formed by reacting with oxygen in the air on the surface. At this time, when the thickness of the Ni thin film plating layer 161 is less than 0.005 micrometer, copper (Cu) generally used in the bonding pad unit 150 cannot be prevented from being diffused into the thin film plating layer 163 made of Ag or Pd. As a result, when the semiconductor package is manufactured, the reliability of bonding bonding property is lowered and thus the reliability of the semiconductor package is reduced. Therefore, in consideration of the antioxidant effect and economical efficiency, the thickness of the Ni thin film plating layer 161 is preferably formed in the range of 0.005 to 0.300 micrometers. In the circuit board 100 of the present invention, the Ni thin film plating layer 161 is formed to prevent oxide formation due to copper (Cu) diffusion, thereby improving wire bonding bonding property of a semiconductor package to be manufactured later. In addition, by forming the Ni thin film plating layer 161 between the bonding pad unit 150 and the thin film plating layer 163 made of Ag or Pd, the adhesion between the layers can be increased, and as a result, the reliability of the semiconductor package can be improved. do.

The Ni thin film plating layer 161 of the present invention can be formed through a known electroless plating or electroplating process. As an example, the Ni thin film plating layer may be formed through an electroplating or electroless plating process using a nickel sulfamate plating solution, nickel chloride, or various plating solutions. At this time, in the case of electroplating, the thickness of the Ni thin film plating layer may be mainly controlled by adjusting a current range and a plating time allowed by each plating solution. At this time, the concentration of the chemicals used, the current to be applied, the plating time can be said to be appropriate design change depending on the characteristics of the chemicals. For example, in the case of using a nickel sulfamate plating solution, various additives are added in order to stabilize plating appearance and plating solution at a Ni concentration of 60 to 90 g / l, and the present invention is applied by applying a current at a current density of 5 to 15 ASD. Ni thin film plating layer can be formed. In this case, the thickness of the Ni thin film plating layer may be adjusted by appropriately adjusting the current density and the plating time in consideration of the plating precipitation rate.

On the Ni thin film plating layer 161, a thin film plating layer 163 made of Ag or Pd is formed. Here, when the thin film plating layer 163 is made of Ag, the thickness thereof is preferably formed in the range of 0.005 to 2.000 micrometers, and when the thin film plating layer 163 is made of Pd, the thickness thereof is in the range of 0.005 to 0.150 micrometers. It is preferably formed. The other details are the same as in the case of forming the plating layer 160 in a single layer structure, and thus will be omitted.

In the circuit board 100 of the present invention having the above-described configuration, when the plating layer 160 is formed on the bonding pad unit 150, the manufacturing cost can be reduced by not using gold (Au), which is an expensive precious metal. As a result, the manufacturing cost and process efficiency of the semiconductor package can be improved. In addition, as the surface roughness 151 is formed on the bonding pad unit 150, the bonding area with the bonding wire increases as the bonding area of the wire increases. Therefore, as a result, there is an effect of providing an excellent circuit board and a semiconductor package using the same, which improves bonding properties, improves adhesion of molding materials, improves solderability, and improves lamination during wire bonding.

FIG. 2 is a cross-sectional view of a semiconductor package manufactured using the circuit board of FIG. 1.

1 and 2, the semiconductor package 10 according to the present invention includes a circuit board (100 of FIG. 1), a semiconductor chip 300, a bonding wire 500, and a molding part 700. do.

The circuit board (100 in FIG. 1) includes a base layer 110, a die pad unit 130 formed on the base layer 110, a bonding pad unit 150, and a plating layer 160 formed on the bonding pad unit 150. It is formed to include. Here, the surface roughness 151 is formed on the upper surface of the bonding pad part 150, and the plating layer 160 is formed of the Ni thin film plating layer 161 and Ag or Pd on the bonding pad part 150 on which the surface roughness 151 is formed. The thin film plating layer 163 may be formed of a double layer structure sequentially formed, and in addition, although not shown in the drawings, the thin film plating layer 163 may be formed of a single layer structure in which only a thin film plating layer made of Ag or Pd is formed. .

In addition, the circuit board 100 of the present invention is formed in the lower portion of the base layer 110, the soldering pads 190 and soldering pads 190 and the soldering pads 190, the die pad portion 130 and the bonding pad portion ( The semiconductor device may further include a conductive via hole 170 that electrically connects at least one of the 150 and the soldering pad 190. Details of each configuration are the same as described above in the description of FIG. 1, and thus will be omitted.

The semiconductor chip 300 is mounted on the die pad portion 130 of the circuit board 100 of FIG. 1. The semiconductor chip 300 of the present invention is a multilayer ceramic capacitor (MLCC), chip inductors, chip resistors, components such as chip switches, circuit elements such as diodes, various filters, integrated circuits, printed resistors, thin films. Various components such as capacitors, inductors, and flash memories may be included. The semiconductor chip 300 of the present invention may be mounted on the die pad unit 130 via the adhesive member 310 by a die attach method, but is not limited thereto.

The bonding wire 500 connects the semiconductor chip 300 and the bonding pad unit 150 to each other to perform electrical connection. In general, the bonding wire 500 connecting the semiconductor chip 300 and the bonding pad unit 150 is mainly made of gold (Au) wire, but recently, due to economic reasons, a cheaper copper (Cu) wire is substituted for gold. It is used a lot. When wire bonding is performed to connect the semiconductor chip 300 and the bonding pad unit 150 to the bonding wire 500, heat is applied to about 200 ° C. so that bonding between different metals is performed well. The oxide layer is formed on the surface by exposure to a high temperature environment. Accordingly, a phenomenon in which the circuit board 100 (of FIG. 1) is easily peeled off from the molding part 700 may occur, resulting in a problem of lowering the reliability of the semiconductor package. In addition, when the wire bonding is performed with copper (Cu) wires, the bonding property with the bonding pad 150 may be degraded due to the formation of the oxide layer.

However, in the semiconductor package according to the embodiment of the present invention, the surface roughness 151 is formed on the surface of the bonding pad unit 150, and the plating layer 160 is sequentially formed, thereby bonding pads due to heat applied during wire bonding. By suppressing the surface oxidation of the unit 150, it is possible to provide a highly reliable semiconductor package. In addition, as the surface area of the bonding pad 150 is increased due to the surface roughness 151 formed on the bonding pad unit 150, the bonding area with the bonding wire 500 and the bonding area with the molding unit 700 are increased. In addition, when the plating layer 160 is formed in a double layer structure, adhesion between the bonding pad part 150 and the thin film plating layer 163 made of Ag or Pd is increased due to the Ni thin film plating layer 161. As a result, it is possible to provide an excellent semiconductor package with improved bonding properties, improved adhesion of molding materials, improved solderability, and improved lamination during wire bonding.

In addition, in the semiconductor package according to the embodiment of the present invention, the surface roughness is formed on the bonding pad unit 150 and the plating layer 160 is formed on the bonding pad unit 150 on which the surface roughness is formed, thereby providing copper (Cu). Even when the wire bonding wire 500 is used, the bonding wire 500 and the bonding pad unit 150 can be firmly bonded. Accordingly, it is possible to obtain a reduction in manufacturing cost by not forming a gold (Au) plating layer, which is conventionally used, a reduction in the plating time required by forming a thin film plating layer, and an improvement in the operation rate by shortening the process time. Will be. In addition, it is possible to provide highly reliable semiconductor packages at low cost, resulting in economic advantages of price competitiveness. Further details are the same as described above in the description of FIG. 1, and thus will be omitted.

The molding part 700 serves to insulate and protect from the external environment by molding and sealing the semiconductor chip 300, the bonding wire 500, and the bonding pad part 150. As a molding material constituting the molding part 700, any one of an epoxy molding compound, a poly phenylene oxide, an epoxy sheet molding (ESM), and silicon may be used. It doesn't happen.

3 is a flowchart illustrating a method of manufacturing a circuit board and a semiconductor package according to an embodiment of the present invention.

In the present embodiment, the circuit board and the semiconductor package manufacturing method may be performed in a reel-to-reel process or in an individual product unit in a strip unit, and may be performed in an in-line process. It is also possible to manufacture.

1 to 3, a method of manufacturing a circuit board and a semiconductor package may be performed as follows. First, a circuit board is manufactured (S10), and a semiconductor chip is mounted on the die pad portion of the manufactured circuit board (S30). The semiconductor chip and the bonding pad unit are wire-bonded (S50) and molding is performed (S70).

The above-described step S10 may be performed as follows. First, a die pad portion and a bonding pad portion are formed on the base layer (S11). More specifically, the die pad portion and the bonding pad portion can be formed by laminating a copper foil layer on one surface or both surfaces of the base layer and patterning the copper foil layer through a photolithography process. In this case, when the copper foil layer is formed not only on the upper portion but also on the lower portion of the base layer, the soldering pad may be additionally formed through the above-described photolithography process as described above in FIG. 1.

Then, the surface roughness is formed on the bonding pad portion (S13). At this time, the roughness of the surface roughness is preferably formed within the range of 0.25 to 0.40 micrometers. Surface roughness may be formed through a rough copper plating process, and copper sulfate plating may be used as the plating process. Further details are the same as described above in the description of FIG. 1, and thus will be omitted.

On the other hand, it is preferable to go through a plating pretreatment process before performing the process of forming the surface roughness, the plating pretreatment process may be, for example, including a chemical / electrolytic degreasing process, pickling process.

In addition, after the surface roughness forming process is preferably carried out a cleaning process is not limited thereto. Here, the washing process may include, for example, a chemical / electrolytic degreasing process and a pickling process, and may be performed only by the pickling process.

Thereafter, Ni may be plated on the bonding pad to form a Ni thin film plating layer (S15). At this time, the thickness of the Ni thin film plating layer is preferably formed to a thickness of 0.005 to 0.300 micrometers, it can be formed through a known electroless plating or electroplating process is as described above in the description of FIGS. However, step S15 described above may be omitted when forming the plating layer in a single layer structure.

After Ag or Pd is plated to form a Pd thin film plating layer (S17). In this case, the thin film plating layer formed in step S17 is formed on the Ni thin film plating layer when the above-described step S15 is performed, and is formed on the bonding pad part when the above-mentioned step S15 is omitted.

On the other hand, when Ag is plated to form a thin film plating layer, the thickness is preferably formed in the range of 0.005 to 2.000 micrometers. Here, the method of forming the thin film plating layer with Ag may be performed by a known method. For example, silver cyanide, an acidic silver plating solution, and other silver plating solutions and additives for the purpose of adjusting the plating solution are combined, and the plating solution is combined, and the amount of current applied to the plating time with the bonding pad part partially or completely immersed in the plating solution is controlled. This may be accomplished by, but is not limited to, the same as described above with reference to FIG. 1.

On the other hand, when the Pd is plated to form a thin film plating layer, the thickness is preferably formed in the range of 0.005 to 0.150 micrometers. Here, the method for forming a thin film plating layer with Pd, for example, a palladium (Pd) metal as a main component, a conductive salt and other additives for stable plating in a plating bath, and the bonding pad portion is partially or completely immersed in the plating bath described above. It may be made by a method of applying a current, but is not limited thereto as described above in the description of FIG.

On the other hand, after the thin film plated layer formed of Ag or Pd in step S17 is preferably further cleaning process. Here, the washing process may be performed including a chemical / electrolytic degreasing process and a pickling process, and may also be performed by only a pickling process.

After the circuit board is manufactured by the above-described method, the semiconductor chip is mounted on the die pad portion of the circuit board (S30). In this case, the semiconductor chip may be mounted on the die pad part through an adhesive member by a die attach method, and may be mounted in various ways according to the characteristics of the semiconductor chip.

Thereafter, wire bonding is performed with a bonding wire in order to electrically connect the semiconductor chip and the bonding pad unit (S50). At this time, a heat of about 200 ° C. is applied to facilitate the bonding between the dissimilar metals. In the present invention, surface roughness is formed on the bonding pad, and a thin film plating layer including Ag or Pd is sequentially formed to perform wire bonding. Surface oxidation of the bonding pad portion due to the applied heat can be suppressed, and the wire bonding bonding property can be improved according to the increase of the bonding area to provide a highly reliable semiconductor package, as described above with reference to FIGS. 1 and 2.

After performing the wire bonding process, the die pad part, the bonding pad part, the semiconductor chip, and the bonding wire are molded with a molding material (S70) to form a molding part. At this time, the molding method is currently developed and commercialized, such as transfer molding using epoxy molding compound, a method of molding by molding an epoxy sheet by thermocompression molding, a method of discharging heat treatment by ejecting a liquid molding material, and a method of injection molding molding material. It can be done in any way that can be implemented or implemented according to future technological advances.

When the semiconductor package is manufactured by the above-described method, since gold (Au) is not used in the thin film plating layer and the bonding wire, manufacturing cost may be reduced due to cost reduction. In addition, the thin film plating layer formed on the bonding pad portion is formed of two layers, and the thickness thereof is made thin so that the plating process time is shortened and the process efficiency is improved. In addition, the semiconductor package manufactured according to the present invention, by forming a surface roughness, and forming a thin film plating layer on the surface roughness, the effect of improving the bonding, molding material adhesion, solderability, lamination quality during wire bonding In addition, by suppressing oxidation of the bonding pad part due to the high temperature applied during wire bonding, the effect of ensuring the reliability of the semiconductor package is as described above with reference to FIG. 1.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, Those skilled in the art will appreciate that many suitable modifications and variations are possible in light of the present invention. Accordingly, all such suitable modifications and variations and equivalents should be considered to be within the scope of the present invention.

10: semiconductor package
100: circuit board
110: base layer
130: die pad portion
150: bonding pad portion
151: surface roughness
160: plating layer
161: Ni thin film plating layer
163: thin film plating layer made of Ag or Pd
170: conductive via hole
190: solder ball pads
300: semiconductor chip
310: adhesive member
500: bonding wire
700: molding part
900: solder ball

Claims (28)

Base layer;
A die pad part and a bonding pad part formed on the base layer;
A thin film plating layer formed on the bonding pad part and made of Ag or Pd; Including,
A circuit board having a surface roughness formed on the bonding pad portion.
The method according to claim 1,
Roughness of the surface roughness,
Circuit board formed in the range of 0.25 to 0.40 micrometers.
The method according to claim 1,
When the thin film plating layer is formed of Ag,
The thickness of the thin film plating layer is a circuit board formed in the range of 0.005 to 2.000 micrometers.
The method according to claim 1,
When the thin film plating layer is formed of Pd,
The thickness of the thin film plating layer is a circuit board formed to a thickness of 0.005 to 0.150 micrometers.
The method according to claim 1,
And a Ni thin film plating layer formed between the bonding pad portion and the thin film plating layer.
The method according to claim 5,
The Ni thin film plating layer,
Circuit board formed to a thickness of 0.005 to 0.150 micrometers.
7. The method according to any one of claims 1 to 6,
And the die pad portion and the bonding pad portion include Cu.
The method of claim 7,
A solder ball pad formed under the base layer;
A conductive via hole formed through the base layer; Further comprising:
At least one of the die pad portion and the bonding pad portion is electrically connected to the solder ball pad via the conductive via hole.
A circuit board having a die pad portion and a bonding pad portion formed on the base layer;
A semiconductor chip mounted on the die pad unit;
Bonding wires connecting the semiconductor chip and the bonding pad unit;
A molding part molding the semiconductor chip;
And a thin film plating layer formed on the bonding pad part and formed of Ag or Pd, wherein a surface roughness is formed on an upper surface of the bonding pad part.
The method according to claim 9,
Roughness of the surface roughness,
A semiconductor package formed in the range of 0.25 to 0.40 microns.
The method according to claim 9,
When the thin film plating layer is formed of Ag,
The thin film plating layer is a semiconductor package formed in the range of 0.005 to 2.000 micrometers.
The method according to claim 9,
When the thin film plating layer is formed of Pd,
The thin film plating layer is a semiconductor package formed to a thickness of 0.005 to 0.150 micrometers.
The method according to claim 9,
The semiconductor package further comprises a Ni thin film plating layer formed between the bonding pad portion and the thin film plating layer.
The method according to claim 13,
The Ni thin film plating layer,
A semiconductor package formed to a thickness of 0.005 to 0.150 micrometers.
The method according to any one of claims 9 to 14,
The bonding wire is formed of a semiconductor package.
The method according to claim 15,
The die pad unit and the bonding pad unit includes a Cu package.
The method according to claim 15,
The circuit board,
A solder ball pad formed on the other surface of the base layer;
A conductive via hole formed through the base layer and electrically connecting at least one of the die pad portion and the bonding pad portion to the solder ball pad; A semiconductor package further comprising.
Forming a die pad portion and a bonding pad portion on the base layer,
Surface roughness is formed on the bonding pad portion,
And forming a thin film plated layer by plating Ag or Pd on the bonding pad portion having the surface roughness.
19. The method of claim 18,
Roughness of the surface roughness,
A circuit board manufacturing method formed in the range of 0.25 to 0.40 micrometers.
19. The method of claim 18,
When plating Ag to form the thin film plating layer,
A circuit board manufacturing method for forming a thickness of the thin film plating layer in the range of 0.005 to 2.000 micrometers.
19. The method of claim 18,
When plating the Pd to form the thin film plating layer,
A circuit board manufacturing method for forming a thickness of the thin film plating layer in the range of 0.005 to 0.150 micrometers.
19. The method of claim 18,
Between forming the surface roughness and forming the thin film plating layer,
And forming a Ni thin film plating layer by plating Ni on the bonding pad part.
23. The method of claim 21,
The Ni thin film plating layer,
A method for manufacturing a circuit board having a thickness of 0.005 to 0.150 micrometers.
The method according to any one of claims 18 to 23,
Forming the die pad portion and the bonding pad portion,
Laminating a Cu layer on the base layer,
A circuit board manufacturing method comprising patterning the Cu layer.
Forming a die pad portion and a bonding pad portion on the base layer,
Surface roughness is formed on the bonding pad portion,
Ag or Pd is plated on the bonding pad to form a thin film plating layer,
A semiconductor chip is mounted on the die pad unit,
Wire-bonding the semiconductor chip and the bonding pad part with a bonding wire,
And molding the die pad unit, the bonding pad unit, the semiconductor chip, and the bonding wire with a molding material.
26. The method of claim 25,
Between forming the surface roughness and forming the thin film plating layer,
And plating Ni on the bonding pad part to form a Ni thin film plating layer.
26. The method of claim 25,
The bonding wire is a semiconductor package manufacturing method comprising Cu.
The method according to any one of claims 25 to 27,
Forming the die pad portion and the bonding pad portion on the base layer,
Laminating a Cu layer on the base layer,
A method of manufacturing a semiconductor package comprising patterning the Cu layer.

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