KR20130043562A - Data recovery circuit and adaptive equalizer coefficients methods the same - Google Patents

Abstract

PURPOSE: A data recovery circuit and an adaptive equalization coefficient controlling method is provided to efficiently remove ISI(Inter Symbol Interference) by using oversampling and an equalizer. CONSTITUTION: An oversampling receiver(10) receives a receiver input signal(RE_S) and a DFE control signal(CON_A) for outputting first through nth pre-recovery signals(PR_D(1:n)). The DFE control signal controls an equalization coefficient for outputting optimal recovered data(REC_D). The data recovery part(20) receives first through nth clock signals(CLK(1:n)) for outputting a minimum data transition signal(OUT_CL) and a maximum data transition signal(OUT_CH). A DFE control part(30) receives the minimum data transition signal and the maximum data transition signal for outputting a DFE control signal. [Reference numerals] (10) Oversampling receiver; (20) Data recovery part; (30) DFE control part;

Description

DATA RECOVERY CIRCUIT AND ADAPTIVE EQUALIZER COEFFICIENTS METHODS THE SAME}

The present invention relates to a data recovery circuit and an adaptive equalization coefficient adjusting method using the same.

The frequency spectrum of a signal generally degrades as it passes through a transmission medium such as a cable. This degradation of quality usually results in attenuation of high frequency components in the frequency spectrum of the signal. As a result of this degradation in quality, since narrow signal pulses have lower peak amplitudes than wide signal pulses, it is difficult to recover the bit information encoded in each pulse. In addition, the signal flowing into the receiver through the transmission medium may include jitter. Signals containing jitter also have difficulty recovering. Signal processing called equalization is performed to compensate for frequency degradation of the frequency. Equalization refers to a technique that reduces jitter in incoming signals and returns attenuated frequency components to near full amplitude.

In transceivers, which are commonly used in high-speed serial interfaces, serial data speeds are gradually increasing to more than a few Gbps. As such, as the transmission speed of data increases, jitter noise of the receiver becomes a major factor in recovering data without error in a data recovery block of the receiver. If long cable or PCB routing is the primary medium, add equalizers to the receiver to reduce inter-symbol-interference (ISI).

It is an object of the present invention to provide a data recovery circuit.

An object of the present invention is to provide a data recovery circuit and an adaptive equalization coefficient adjusting method using the same.

Problems to be solved by the present invention are not limited to the above-mentioned problems, and other tasks not mentioned will be clearly understood by those skilled in the art from the following description.

According to an embodiment of the inventive concept, the data recovery circuit generates a plurality of sampling signals by over-sampling a receiver input signal in response to a plurality of clock signals that are sequentially delayed, and responds to the plurality of sampling signals. An over-sampling receiver for outputting a plurality of pre recovery signals adjusted according to the DFE control signal; A data recovery unit generating a plurality of transition detection signals by the plurality of clock signals based on the plurality of prerecovery signals, and outputting a lowest data transition signal and a highest data transition signal based on the plurality of transition detection signals; And a DFE controller configured to output the DFE control signal by using any one or more of the lowest data transition signal and the highest data transition signal.

The transition detection signal may include the position of the data transition and the number of data transitions occurring in the sampling interval between the sampling time points of two adjacent clock signals during the data transition detection period.

The lowest data transition signal may include information about the position of the data transition and the number of data transitions having the least occurrence of the data transition occurring between the sampling intervals on average.

The highest data transition signal may include information about the position of the data transition in which the occurrence of the data transition occurring between the sampling intervals is on average and the number of the data transitions.

And a plurality of unit over-sampling receivers respectively corresponding to the plurality of clock signals, wherein the unit over-sampling receiver outputs the plurality of sampling signals by sampling the receiver input signal in response to the plurality of clock signals. An over-sampler portion; A DFE unit for equalizing the sampling signal according to an equalization coefficient adjusted by the DFE control signal in response to a feedback pre-recovery signal and outputting an equalizing signal; And a latch unit configured to output the plurality of prerecovery signals in response to the equalizing signal.

The DFE unit may include an equalization coefficient adjusting unit for adjusting the equalization coefficient according to the DFE control signal.

The equalization coefficient may represent a voltage drop rate of the voltage level of the sampling signal.

The data recovery unit may select any one of the plurality of prerecovery signals in response to the highest data transition signal and output the recovered signal.

The data recovery unit may include: a data transition detector configured to receive the plurality of clock signals and the plurality of prerecovery signals and detect and output the plurality of transition detection signals; A data transition comparator configured to output the lowest data transition signal and the highest data transition signal based on the plurality of transition detection signals; And a data selector configured to select any one of the plurality of prerecovery signals output from the unit oversampling receiver in response to the highest data transition signal and to output the recovered data.

The DFE controller may include: a DFE controller which receives the lowest data transition signal or the highest data transition signal and outputs an increase control signal and a decrease control signal for increasing or decreasing the control code by 1; And a counter unit configured to receive the increase control signal and the decrease control signal and output the DFE control signal.

The DFE adjustment unit may compare the first highest data transition signal in the first data transition detection period with the second highest data transition signal in the second data transition detection period to compare the highest data transition included in the first highest data transition signal. If the position and the number of the highest data transitions are changed, the increment control signal is output, and the first lowest data transition signal in the first data transition detection period and the second lowest data transition signal in the second data transition detection period are output. In comparison, when the number of the lowest data transitions included in the first lowest data transition signal decreases, the first data transition detection period is performed in the same direction as the change direction of the second control code with respect to the second data transition detection period. For changing the first control code Outputting the increase control signal or the decrease control signal and detecting the first data transition in a direction opposite to a change direction of the second control code with respect to the second data transition detection period when the number of the lowest data transitions is increased; The increase control signal or the decrease control signal for changing the first control code for a period may be output.

The DFE controller may adjust the first control code by using the lowest data transition signal when the highest data transition signal maintains the same highest sampling interval for a predetermined time.

A sampling signal is generated by receiving a clock signal and a receiver input signal, and an equalizing signal generated in response to the sampling signal and the DFE control signal is latched and output as a pre-recovery signal, wherein the pre-recovery signal is fed back. ; A data recovery unit configured to receive the clock signal and the pre-recovery signal and output recovered data, a lowest data transition signal, and a highest data transition signal; And a DFE controller configured to generate the DFE control signal in a first mode using the lowest data transition signal and to generate the DFE control signal in a second mode using the highest data transition signal. have.

In the first mode, the equalization coefficient may be increased until the first condition is satisfied, and in the second mode, the equalization coefficient may be increased or decreased according to the second condition after the first condition is satisfied. have.

The first condition may be a position of a sampling interval for the highest data transition signal for a predetermined time, and the second condition may be an increase or decrease in the number of data transitions for the lowest data transition signal.

Specific details of other embodiments are included in the detailed description and the drawings.

According to various embodiments of the inventive concept, a data recovery circuit and an adaptive equalization coefficient adjusting method using the same may effectively remove inter-symbol-interference (ISI) using over-sampling and an equalizer. In other words, by quickly reacting to noise or a change in the state of a channel, ISI can be effectively removed.

1 is a block diagram illustrating a data recovery circuit in an embodiment of the inventive concept.
FIG. 2 is a block diagram illustrating a configuration of an over-sampling receiver included in the data recovery circuit shown in FIG. 1.
FIG. 3 is a detailed circuit diagram of an embodiment of a unit over-sampling receiver of the over-sampling receiver shown in FIG. 2.
4 is a detailed circuit diagram illustrating an embodiment of a configuration of an equalization coefficient adjusting unit shown in FIG. 3.
FIG. 5 is a block diagram illustrating a configuration of a data recovery unit included in the data recovery circuit shown in FIG. 1.
6 is a timing diagram illustrating a method for adjusting an adaptive equalization coefficient using a data recovery circuit according to the inventive concept.
FIG. 7 is a block diagram illustrating a configuration of a DFE controller included in the data recovery circuit shown in FIG. 1.
8 is a flowchart illustrating a method for adjusting an adaptive equalization coefficient using a data recovery circuit according to the inventive concept.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG. The embodiments described in the specification of the present invention are provided to enable a person skilled in the art to easily transfer and implement technical ideas. Therefore, the technical spirit of the present invention is not limited to the embodiments described below, but can be modified into various forms. The shapes and sizes of the regions shown in the drawings attached to the specification of the present invention are merely illustrative for the understanding of the present invention and can be exaggerated for convenience. Thus, the regions illustrated in the figures have schematic attributes and do not limit the scope of the invention. Reference numerals in the specification of the present invention refer to the same components. Therefore, the same reference numerals or similar reference numerals can be described with reference to other drawings, even if they are not mentioned or described in the drawings. Also, although reference numerals are not indicated, they may be described with reference to other drawings.

1 is a block diagram illustrating a data recovery circuit 1 according to an embodiment of the inventive concept.

Referring to FIG. 1, the data recovery circuit 1 according to an embodiment of the present invention includes an over-sampling receiver 10, an data recovery unit 20, a data recovery unit, and a DFE controller 30. Decision Feedback Equalizer Adaptation Control Unit).

The over-sampling receiver 10 receives the receiver input signal RE_S and the DFE control signal CON_A in response to the first to n th clock signals CLK <1: n>, and the first to n th prerecovery signals. (PR_D <1: n>) can be output.

The over-sampling receiver 10 receives the first to n th clock signals CLK <1: n> and receives the first to n th sampling signals SA_S <1: n> sampled from the receiver input signal RE_S. Is equalized according to the equalization coefficient adjusted by the DFE control signal CON_A in response to the fed back first to nth pre-recovery signals PR_D <1: n>, and the first to nth pre-recovery signals PR_D <1. : n>)

At this time, the DFE control signal CON_A may adjust the equalization coefficient to output the optimal recovered data REC_D.

The data recovery unit 20 receives the first to n th clock signals CLK <1: n> and the first to n th pre recovery signals PR_D <1: n> to recover the data REC_D, which is the lowest. The data transition signal OUT_CL and the highest data transition signal OUT_CH may be output.

The DFE controller 30 may receive the lowest data transition signal OUT_CL and the highest data transition signal OUT_CH and output the DFE control signal CON_A.

FIG. 2 is a block diagram showing the configuration of the over-sampling receiver 10 included in the data recovery circuit 1 shown in FIG.

Referring to FIG. 2, the over-sampling receiver 10 may include an over-sampler unit 12, a decision feedback equalizer (DFE) 14, and a latch unit 16.

The over-sampler unit 12 synchronizes the first to nth clock signals CLK <1: n> with the receiver input signal RE_S to sample the first to nth sampling signals SA_S <1: n>. It may include the first to n th sampler (121 ~ 12n) for outputting. For example, the first sampler 121 may generate the first sampling signal SA_S <1> by synchronizing and sampling the first clock signal CLK <1> with the receiver input signal RE_S. . The second sampler 122 may generate the second sampling signal SA_S <2> by synchronizing and sampling the second clock signal CLK <2> with the receiver input signal RE_S. The third sampler 123 may generate the third sampling signal SA_S <3> by synchronizing and sampling the third clock signal CLK <3> with the receiver input signal RE_S. Finally, the n th sampler 12n may generate the n th sampling signal SA_S <n> by synchronizing and sampling the n th clock signal CLK <n> with the receiver input signal RE_S. At this time, the m th clock signal CLK <m> may be delayed in phase by 360 ° / n than the m-1 th clock signal CLK <m-1>. m may be any one of integers from 2 to n.

The DFE unit 14 receives the first to nth clock signals CLK <1: n> and receives the first to nth pre-recovery signals fed back from the first to nth sampling signals SA_S <1: n>. First to nth outputting first to nth equalizing signals ESA_D <1: n> equalized according to an equalization coefficient adjusted by the DFE control signal CON_A in response to PR_D <1: n>. It may include the DFE portion (141 ~ 14n). For example, the first DFE unit 141 receives the first clock signal CLK <1> and supplies the first sampling signal SA_S <1> to the fed back first pre-recovery signal PR_D <1>. In response, the first equalizing signal ESA_D <1> equalized according to the equalization coefficient adjusted by the DFE control signal CON_A may be output. The second DFE unit 142 receives the second clock signal CLK <2> and controls the DFE in response to the second pre-recovery signal PR_D <2> fed back to the second sampling signal SA_S <2>. The equalized second equalizing signal ESA_D <2> may be output according to the equalizing coefficient adjusted by the signal CON_A. The third DFE unit 143 receives the third clock signal CLK <3> and controls the DFE in response to the third pre-recovery signal PR_D <3> fed back to the third sampling signal SA_S <3>. The equalized third equalizing signal ESA_D <3> may be output according to the equalizing coefficient adjusted by the signal CON_A. Finally, the n th DFE unit 14n receives the n th clock signal CLK <n> and responds to the n th pre-recovery signal PR_D <n> fed back to the n th sampling signal SA_S <n>. The n th equalizing signal ESA_D <n> equalized according to the equalizing coefficient adjusted by the DFE control signal CON_A may be output.

The latch unit 16 latches the first to nth equalizing signals ESA_D <1: n> outputted from the first to nth DFE units 141 to 14n>, and thus, the first to nth prerecovery signals PR_D. And first to n-th latch parts 161 to 16n> output to <1: n>. For example, the first latch unit 161 may latch the first equalizing signal ESA_D <1> to output the first pre-recovery signal PR_D <1>. The second latch unit 162 may latch the second equalizing signal ESA_D <2> to output the second pre recovery signal PR_D <2>. The third latch unit 163 may latch the third equalizing signal ESA_D <3> to output the third pre-recovery signal PR_D <3>. Finally, the nth latch unit 16n may latch the nth equalizing signal ESA_D <n> to output the nth pre-recovery signal PR_D <n>.

FIG. 3 is a detailed circuit diagram of one embodiment of the unit over-sampling receiver 110 of the over-sampling receiver 10 shown in FIG. 2. FIG. 4 is a detailed circuit diagram illustrating an embodiment of the configuration of the equalization coefficient adjusting unit 1410 shown in FIG. 3.

Referring to FIG. 3, the unit over-sampling receiver 110 receives a receiver input signal RE_S, synchronizes and samples the first clock signal CLK <1>, and receives the first sampling signal SA_S <1>, / Generating SA <1> and controlling the DFE in response to the first pre-recovery signals PR_D <1> and / PR_D <1> fed back to the first sampling signals SA_S <1> and / SA <1>. The first equalizing signals ESA_D <1> and / ESA_D <1> generated by equalizing according to the equalization coefficient adjusted by the signal CON_A are latched to the first pre-recovery signals PR_D <1> and / PR_D. You can print

In detail, the first over-sampler 121 synchronizes and samples the first clock signal CLK <1> with the receiver input signal RE_S to sample the first sampling signals SA_S <1> and / SA <. 1>).

The first DFE unit 141 responds to the first pre-recovery signals PR_D <1> and / SAM_D <1> by feeding back the first sampling signals SA_S <1> and / SA <1>. The equalized first equalizing signals ESA_D <1> and / ESA_D <1> may be output according to the equalization coefficient adjusted by CON_A.

The equalization coefficient adjusting unit 1410 may adjust the speed of the voltage drop with respect to the voltage levels of the first sampling signals SA_S <1> and / SA <1> according to the equalization coefficient. For example, the greater the equalization coefficient, the faster the voltage drop of the voltage levels of the first sampling signals SA_S <1> and / SA <1> may be faster. In this case, the equalization coefficient may be adjusted according to the DFE control signal CON_A.

Referring to FIG. 4, the DFE control signal CON_A may be a 4-bit control code having first to fourth control codes CD1 to CD4.

The equalization coefficient adjusting unit 1410 includes first to fourth coefficient determining transistors connected in series to each of the first to fourth control transistors M1 to M4 and the first to fourth control transistors M1 to M4. M5 to M8 and a connection transistor M9 connected in parallel with the first to fourth coefficient determination transistors M5 to M8.

The size ratio between the first to fourth coefficient determination transistors M5 to M8 may be set to 8: 4: 2: 1 when the size of the fourth coefficient determination transistor M8 is one.

The current passing ratio of the first to fourth coefficient determination transistors M5 to M8 may be proportional to the size ratio of the first to fourth coefficient determination transistors M5 to M8. That is, the larger the size of the first to fourth coefficient determination transistors M5 to M8, the greater the current passing rate.

For example, when '0, 1, 0, 0' is input to the first to fourth control codes CD1 to CD4, the first control code CD1 is 0 and the second control code CD2 is 1. The third control code CD3 may be zero, and the fourth control code CD4 may be zero. Since only the second control transistor M2 is turned on according to the first to fourth control codes CD1 to CD4 of '0100', the second control transistor M2 and the second coefficient determining transistor M6 may be formed only through the paths of the second control transistor M2. A current that drops the voltage level of one sampling signal SA_S <1> and / SA <1> may flow.

In addition, when '0, 1, 0, 1' is input to the first to fourth control codes CD1 to CD4, the first control code CD1 is 0 and the second control code CD2 is 1, first. 3 The control code CD3 may be 0, and the fourth control code CD4 may be 1. Since only the second control transistor M2 and the fourth control transistor M4 are turned on according to the first to fourth control codes CD1 to CD4 of '0101', the second control transistor M2 and the second coefficient determination transistor are turned on. The voltage level of the first sampling signals SA_S <1> and / SA <1> is lowered only through the path through M6 and the paths of the fourth control transistor M4 and the fourth coefficient determination transistor M8. Current can flow.

The voltage drop adjusted by the case where 0101 is input to the first to fourth control codes CD1 to CD4 is inputted with '0, 1, 0, 0' to the first to fourth control codes CD1 to CD4. Since the voltage drop is larger than the voltage drop adjusted by the case, the speed of the voltage drop of the first sampling signals SA_S <1> and / SA <1> may be increased.

In summary, as the values of the first to fourth control codes CD1 to CD4 increase, the speed at which the first sampling signals SA_S <1> and / SA <1> drop down may increase. That is, the equalization coefficients for the first sampling signals SA_S <1> and / SA <1> may be increased.

The first latch unit 161 may latch the first equalizing signals ESA_D <1> and / ESA_D <1> and output the first equalizing signals PR_D <1> and / PR_D <1>.

FIG. 5 is a block diagram showing the configuration of the data recovery unit 20 included in the data recovery circuit 1 shown in FIG. 1. FIG. 6 is a timing diagram for explaining an adaptive equalization coefficient adjusting method using the data recovery circuit 1 according to the inventive concept.

Referring to FIG. 5, the data recovery unit 20 may include a data transition detector 22, a data transition comparator 24, and a data selector 26.

The data transition detector 22 receives the first to nth clock signals CLK <1: n> and the first to nth pre-recovery signals PR_D <1: n> to receive the first to nth transition detection signals. (FLG <1: n>) can be detected and output.

Referring to FIG. 6, in the case of 3-over-sampling, the first to third transition detection signals FLG <1: 3> may include first to third clock signals CLK <1: 3>. It may include information about the data transition generated during the data transition detection period (T _-2 -T _n ) in the third sampling interval (P ₁ ~ P ₃ ). That is, the first transition detection signal FLG <1> includes the position and the number of data transitions generated during each data transition detection period T _-2 -T _n at the first sampling interval P ₁ , The second transition detection signal FLG <2> includes the position and the number of data transitions generated during each data transition detection period T _-2 -T _n at the second sampling interval P ₂ , and the third The transition detection signal FLG <3> may include the position and the number of data transitions generated during each data transition detection period T ₋₂ -T _n in the third sampling interval P ₃ . In this case, the data transition detection period (T _-n -T _n ) is set to have a period of three clocks, respectively, but is not limited thereto, and may have a period of two clocks or a period of three clocks or more.

Between the first sampling interval (P ₁₎ is the first clock signal (CLK <1>) of the first sampling time point (S ₁₎ and the second clock signal (CLK <2>) a second sampling time point (S ₂₎ of a between a second sampling interval (P ₂₎ is the second clock signal (CLK <2>) a second sampling time point (S ₂₎ and the third clock signal (CLK <3>) a third sampling point (S ₃₎ of the and, the third sampling interval (P ₃₎ is the third clock signal (CLK <3>) 3 the first sampling time point (S ₁₎ of the sampling time (S ₃₎ and the first clock signal (CLK <1>) of May be between. In this case, each of the first to third clock signals CLK <1: 3> may be delayed by an A interval and input.

The data transition comparison unit 24 responds to the first to nth transition detection signals FLG <1: n> based on the first to nth clock signals CLK <1: n> and performs the lowest data transition signal OUT_CL) and the highest data transition signal OUT_CH.

The lowest data transition signal OUT_CL has an average data transition among information on the number of data transitions occurring in the first to nth sampling intervals P ₁ to P _n during the data transition detection period T _−n −T _n . It may include information about the location of the first to n th sampling intervals P ₁ to P _n and the number of data transitions that occur least. The highest data transition signal OUT_CH has an average data transition among information on the number of data transitions occurring in the first to nth sampling intervals P ₁ to P _n during the data transition detection period T _-n -T _n . It may include information about the position of the first to n-th sampling interval (P ₁ ~ P _n ) and the number of data transitions that occur most frequently.

The data selector 26 receives the first to nth pre-recovery signals PR_D <1: n> based on the first to nth clock signals CLK <1: n> and outputs the highest data transition signal OUT_CH. ), The recovered data REC_D may be output. The data selector 26 may select one of the first to nth pre-recovery signals PR_D <1: n> as the recovered data REC_D using the highest data transition signal OUT_CH.

FIG. 7 is a block diagram illustrating a configuration of the DFE controller 30 included in the data recovery circuit 1 shown in FIG. 1.

Referring to FIG. 7, the DFE controller 30 may include a DFE controller 32, a decision feedback equalizer adaptation controller, and a counter 34.

The DFE control unit 32 receives the lowest data transition signal OUT_CL and the highest data transition signal OUT_CH and receives the DFE control signals CON_A having the first to fourth control codes CD1 to CD4, respectively. An increase control signal CI_S and a decrease control signal CD_S that can increase or decrease can be output.

The increment control signal CI_S is included in the highest data transition signal OUT_CH between the current data transition detection period T ₀ and the previous data transition detection period T _-1 in the coarse control code setting mode, respectively. the first to n-th sampling interval (P ₁ ~ P _n) when the number of the position and the data transition of the first to n-th sampling interval (P ₁ ~ P _n) by comparing the number of positions and the data transition, fluctuation of the , And compare the number of data transitions included in the lowest data transition signal OUT_CL in the previous data transition detection period T _-1 with the current data transition detection period T ₀ in the optimal control code setting mode, respectively. When the number of data transitions is changed, the values of the first to fourth control codes CD1 to CD4 may be increased by one.

The decrement control signal CD_S corresponds to the data transition signal included in the lowest data transition signal OUT_CL in the current data transition detection period T ₀ and the previous data transition detection period T ₋₁ in the optimum control code setting mode. When the number of data transitions is changed by comparing the numbers, the values of the first to fourth control codes CD1 to CD4 may be decreased by one.

The counter 34 may receive the increase control signal CI_S and the decrease control signal CD_S and output the DFE control signal CON_A. When the counter 34 receives the increase control signal CI_S, the counter 34 outputs the DFE control signal CON_A having the first to fourth control codes CD1 to CD4 increased by one, and outputs the decrease control signal CD_S. In response to the input, the first to fourth control codes CD1 to CD4 may be output with a DFE control signal CON_A reduced by one.

8 is a flowchart illustrating an adaptive equalization coefficient adjusting method using the data recovery circuit 1 according to the inventive concept.

Referring to FIG. 8, the DFE control unit 32 may initialize the first to fourth control codes CD1 to CD4. (S2) The first to fourth control codes CD1 to CD4 may be set to '0,'. It can be initialized to 0, 0, 0 '.

Next, when performing the rough control code setting mode for setting the rough control code, the DFE controller 32 may receive the highest data transition signal OUT_CH output from the data recovery unit 20. S4)

Referring to FIG. 6, the DFE controller 32 is configured to the highest data transition signal OUT_CH in the current data transition detection period T ₀ and the previous data transition detection period T ₋₁ in the schematic control code setting mode, respectively. The presence or absence of a change may be checked by comparing the positions of the included first to nth sampling intervals P ₁ to P _n and the number of data transitions. (S6) For example, a previous data transition detection period (T ₋₁ ). In the case where the highest data transition signal OUT_CH is the highest data transition in the first sampling interval P ₁ , the highest data transition signal OUT_CH is the second sampling interval in the current data transition detection period T ₀ . Comparing the case where the data transition is the highest in P ₂ ), the DFE control unit 32 may output the increase control signal CI_S. In other words, the current data transition detection period T ₀ and the previous Data transition Ex period (T _-1) the first to third sampling interval (P ₁ ~ P ₃₎ as compared to the number of locations and data transitions, the current data transition detection period included in the maximum data transition signal (OUT_CH) between When there is a variation in the positions of the first to third sampling intervals P ₁ to P ₃ and the number of data transitions included in the highest data transition signal OUT_CH of (T ₀ ), the counter unit 34 increases the control signal. (CI_S) can be input. The counter 34 may adjust the equalization coefficient by outputting the DFE control signal CON_A having the first to fourth control codes CD1 to CD4 increased by one.

Meanwhile, the first to third signals included in the highest data transition signal OUT_CH detected in the previous data transition detection period T _-1 and the highest data transition signal OUT_CH detected in the current data transition detection period T ₀ . When there is no change in the position of the sampling intervals P ₁ to P ₃ and the number of data transitions, the first to third sampling intervals (DFE) included in the highest data transition signal OUT_CH for a predetermined period ( It may be determined whether the positions of P ₁ to P ₃ are maintained (S10).

If the positions of the first to third sampling intervals P ₁ to P ₃ included in the highest data transition signal OUT_CH are not maintained for a predetermined period, the DFE control unit 32 controls the data to set the coarse control code. The highest data transition signal OUT_CH output from the recovery unit 20 may be input.

On the other hand, when the positions of the first to third sampling intervals P ₁ to P ₃ included in the highest data transition signal OUT_CH are maintained for a predetermined period, the counter 34 may set a coarse control code. (S12)

Next, when the DFE controller 32 performs an optimal control code setting mode for setting an optimal control code, the DFE controller 32 may receive the lowest data transition signal OUT_CL output from the data recovery unit 20. (S14)

Referring to FIG. 6, the DFE control unit 32 may apply the lowest data transition signal OUT_CL between the current data transition detection period T ₀ and the previous data transition detection period T ₋₁ in an optimal control code setting mode. In operation S16, for example, the lowest data transition signal OUT_CH is ₁ in the third sampling interval P ₃ of the previous data transition detection period T ₋₁ . When the number of data transitions and the number of one data transition are included in the third sampling interval P ₃ of the current data transition detection period T ₀ , the selecting unit 34 may set an optimal control code. (S24) Accordingly, the equalization coefficient adjusting unit 1410 may adjust and output the equalization coefficient according to the DFE control signals CON_A including the first to fourth control codes CD1 to CD4.

Meanwhile, the lowest data transition signal OUT_CH has the number of one data transition in the third sampling interval P ₃ of the previous data transition detection period T ₋₁ , and the first data transition signal OUT_CH of the current data transition detection period T ₀ . In the case of having the number of two data transitions in three sampling intervals P ₃ (S18), the DFE control unit 32 may adjust the current control code.

The DFE control unit 32 may include first through fourth current data transition detection periods T _{0 in the} same direction as the change direction of the first through fourth control codes CD1 through CD4 in the previous data transition detection period T ₋₁ . The fourth control codes CD1 to CD4 may be adjusted (S20).

For example, if the first to fourth control codes CD1 to CD4 are increased in the previous data transition detection period T _-1 , the DFE controller 32 outputs an increase control signal CI_S to output the current data transition. If the first to fourth control codes CD1 to CD4 of the detection period T ₀ are increased and the first to fourth control codes CD1 to CD4 are decreased in the previous data transition detection period T- ₁ , The reduction control signal CD_S may be output to reduce the first to fourth control codes CD1 to CD4 of the current data transition detection period T ₀ . In this case, the detection period prior to the data transitions (T _-1) the first to fourth control code (CD1 ~ CD4) the first to fourth control change direction is set at the previous data transition detection period (T _-2) of from It can be determined by comparing with the codes CD1 to CD4.

On the other hand, when the number of data transitions included in the lowest data transition signal OUT_CH increases, the DFE controller 32 may control the first to fourth control codes CD1 to CD4 in the previous data transition detection period T _-1 . The first to fourth control codes CD1 to CD4 of the current data transition detection period T ₀ may be adjusted in the opposite direction to the change direction of S S22.

For example, referring to FIG. 6, the lowest data transition signal OUT_CH is the number of two data transitions and the current data transition detection in the third sampling interval P ₃ of the previous data transition detection period T ₋₁ . When the number of three data transitions is included in the third sampling interval P ₃ of the period T ₀ , the DFE controller 32 controls the first to fourth controls in the previous data transition detection period T ₋₁ . If the codes CD1 to CD4 are increased, the decrease control signal CD_S is output to decrease the first to fourth control codes CD1 to CD4 in the current data transition detection period T ₀ , and the previous data transition is detected. If the first to fourth control codes CD1 to CD4 are decreased in the period T _-1 , the increase control signal CI_S is output to output the first to fourth control codes in the current data transition detection period T ₀ . (CD1 ~ CD4) can be increased. In this case, the detection period prior to the data transitions (T _-1) the first to fourth control code (CD1 CD4 ~) the first to fourth control change direction is set at the previous data transition detection period (T _-2) of from The judgment can be made by comparing with the codes CD1 to CD4.

While the embodiments of the present invention have been schematically described with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. I can understand that you can. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

1: data recovery circuit
10: over-sampling receiver 12: over-sampler part
14: DFE section 16: latch section
1410: equalization coefficient control unit
20: data recovery unit
22: data transition detection unit 24: data comparison unit
26: data selector
30: DFE control unit
32: DFE control section 34: selection section

Claims (10)

A plurality of sampling signals are generated by over-sampling a receiver input signal in response to a plurality of clock signals that are sequentially delayed in phase, and output a plurality of pre recovery signals adjusted according to a DFE control signal in response to the plurality of sampling signals. An over-sampling receiver;
A data recovery unit generating a plurality of transition detection signals by the plurality of clock signals based on the plurality of prerecovery signals, and outputting a lowest data transition signal and a highest data transition signal based on the plurality of transition detection signals; And
And a DFE controller configured to output the DFE control signal by using any one or more of the lowest data transition signal and the highest data transition signal. The method of claim 1,
The lowest data transition signal includes information on the location of the data transition and the number of data transitions having the least average occurrence of the data transition occurring between the sampling intervals using the transition detection signal. The highest data transition signal includes information on the position of the data transition and the number of data transitions having the largest average occurrence of the data transition occurring between the sampling intervals using the transition detection signal.
And the transition detection signal includes a position of the data transition and the number of data transitions occurring at a sampling interval between sampling points by two adjacent clock signals during a data transition detection period. The method of claim 1,
A plurality of unit over-sampling receivers respectively corresponding to the plurality of clock signals;
The unit over-sampling receiver,
An over-sampler unit configured to output the plurality of sampling signals by sampling the receiver input signal in response to the plurality of clock signals;
A DFE unit for equalizing the sampling signal according to an equalization coefficient adjusted by the DFE control signal in response to a feedback pre-recovery signal and outputting an equalizing signal; And
And a latch unit configured to output the plurality of pre-recovery signals in response to the equalizing signal. The method of claim 3,
The DFE unit,
And an equalization coefficient adjusting unit for adjusting the equalization coefficient according to the DFE control signal. The method of claim 3,
The data recovery unit,
A data transition detector which receives the plurality of clock signals and the plurality of prerecovery signals and detects and outputs the plurality of transition detection signals;
A data transition comparator configured to output the lowest data transition signal and the highest data transition signal based on the plurality of transition detection signals; And
And a data selector configured to select one of the plurality of prerecovery signals output from the unit oversampling receiver in response to the highest data transition signal and to output the recovered data as the recovered data. The method of claim 1,
The DFE control unit,
A DFE controller which receives the lowest data transition signal or the highest data transition signal and outputs an increase control signal and a decrease control signal for increasing or decreasing the control code by 1; And
And a counter unit configured to receive the increase control signal and the decrease control signal and output the DFE control signal. The method according to claim 6,
The DFE control unit,
The position and the maximum data of the highest data transition included in the first highest data transition signal by comparing the first highest data transition signal in the first data transition detection period and the second highest data transition signal in the second data transition detection period. When the number of transitions is changed, the increase control signal is outputted.
When the number of lowest data transitions included in the first lowest data transition signal decreases by comparing the first lowest data transition signal in the first data transition detection period and the second lowest data transition signal in the second data transition detection period. Outputs the increase control signal or the decrease control signal for changing the first control code for the first data transition detection period in the same direction as the change direction of the second control code for the second data transition detection period; And when the number of the lowest data transitions is increased, changing the first control code for the first data transition detection period in a direction opposite to the change direction of the second control code for the second data transition detection period. The increase control signal or the decrease control signal Output data recovery circuit. The method of claim 7, wherein
The DFE control unit,
If the highest data transition signal maintains the same highest sampling interval for a predetermined time,
And a data recovery circuit for adjusting the first control code using the lowest data transition signal. A sampling signal is generated by receiving a clock signal and a receiver input signal, and an equalizing signal generated in response to the sampling signal and the DFE control signal is latched and output as a pre-recovery signal. ;
A data recovery unit configured to receive the clock signal and the pre-recovery signal and output recovered data, a lowest data transition signal, and a highest data transition signal; And
And a DFE controller configured to generate the DFE control signal in a first mode using the lowest data transition signal and to generate the DFE control signal in a second mode using the highest data transition signal. The method of claim 9,
In the first mode, the equalization coefficient is increased until a first condition is satisfied,
In the second mode, after the first condition is satisfied, the equalization coefficient is increased or decreased according to the second condition,
The first condition is that the position of the sampling interval for the highest data transition signal is maintained for a predetermined time,
The second condition is that the number of data transitions for the lowest data transition signal is increased or decreased.

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