KR20130005589A - Light emitting device, light emitting device package, light unit, and method of fabricating light emitting device - Google Patents

Abstract

PURPOSE: A light emitting device, a light emitting device package, a light unit, and a method for fabricating the light emitting device are provided to change an electric signal to light by using the property of compound semiconductor. CONSTITUTION: An active layer(43) is formed under a first conductivity type semiconductor layer(41). A second conductivity type semiconductor layer(45) is formed under the active layer. A light emitting structure(40) includes a first and a second semiconductor layer and the active layer. A first electrode is formed on the light emitting structure. A second electrode is formed under the light emitting structure.

Description

LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE, LIGHT UNIT, AND METHOD OF FABRICATING LIGHT EMITTING DEVICE}

The embodiment relates to a light emitting device, a light emitting device manufacturing method, a light emitting device package, a light unit and a light emitting device manufacturing method.

Light emitting diodes (LEDs) are widely used as one of light emitting devices. Light-emitting diodes use the properties of compound semiconductors to convert electrical signals into light, such as infrared, ultraviolet, or visible light.

Recently, as the light efficiency of the light emitting device is increased, it is used in various fields including a display device and a lighting device.

The embodiment provides a light emitting device, a light emitting device package, and a light unit having a new structure.

The embodiment provides a light emitting device, a light emitting device manufacturing method, a light emitting device package, and a light unit capable of improving light extraction efficiency and increasing manufacturing yield.

The light emitting device according to the embodiment may include a light emitting structure including a first conductive semiconductor layer, an active layer under the first conductive semiconductor layer, and a second conductive semiconductor layer under the active layer; A first electrode on the light emitting structure; A second electrode under the light emitting structure; The side surface of the light emitting structure includes a first inclined surface and a second inclined surface, and the first inclined surface and the second inclined surface are connected with a step.

The light emitting device package according to the embodiment includes a body; A light emitting element disposed on the body; A first lead electrode and a second lead electrode electrically connected to the light emitting element; The light emitting device includes: a light emitting structure including a first conductive semiconductor layer, an active layer under the first conductive semiconductor layer, and a second conductive semiconductor layer under the active layer; A first electrode on the light emitting structure; A second electrode under the light emitting structure; The side surface of the light emitting structure includes a first inclined surface and a second inclined surface, and the first inclined surface and the second inclined surface are connected with a step.

According to an embodiment, a light unit includes a substrate; A light emitting element disposed on the substrate; An optical member through which light provided from the light emitting device passes; The light emitting device includes: a light emitting structure including a first conductive semiconductor layer, an active layer under the first conductive semiconductor layer, and a second conductive semiconductor layer under the active layer; A first electrode on the light emitting structure; A second electrode under the light emitting structure; The side surface of the light emitting structure includes a first inclined surface and a second inclined surface, and the first inclined surface and the second inclined surface are connected with a step.

In accordance with another aspect of the present invention, a method of manufacturing a light emitting device includes: etching a growth substrate to form a recess between the barrier rib and the barrier rib; Forming a growth prevention layer on the partition wall; Forming a light emitting structure including a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, and a second conductive semiconductor layer on the active layer in the recess; Forming a second electrode electrically connected to the second conductive semiconductor layer of the light emitting structure; Separating the light emitting structure on which the second electrode is formed from the growth substrate and the growth prevention layer; Forming a first electrode electrically connected to the first conductivity type semiconductor layer of the light emitting structure; It includes.

The embodiment can provide a light emitting device, a light emitting device package, and a light unit having a new structure.

The embodiment can provide a light emitting device, a light emitting device manufacturing method, a light emitting device package, and a light unit capable of improving light extraction efficiency and increasing a manufacturing yield.

1 is a view showing a light emitting device according to an embodiment.
2 to 13 illustrate a method of manufacturing a light emitting device according to an embodiment.
14 is a view showing a light emitting device according to another embodiment.
15 to 29 are views illustrating a light emitting device manufacturing method according to another exemplary embodiment.
30 is a view showing a light emitting device package to which the light emitting device according to the embodiment is applied.
31 is a diagram illustrating an example of a display device to which a light emitting device is applied, according to an exemplary embodiment.
32 is a diagram illustrating another example of a display device to which a light emitting device is applied, according to an exemplary embodiment.
33 is a diagram illustrating an example of a lighting device to which a light emitting device is applied, according to an embodiment.

In the description of the embodiments, it is to be understood that each layer (film), region, pattern or structure may be referred to as being "on" or "under" a substrate, each layer It is to be understood that the terms " on "and " under" include both " directly "or" indirectly " do. In addition, the criteria for the top / bottom or bottom / bottom of each layer are described with reference to the drawings.

The thickness and size of each layer in the drawings are exaggerated, omitted, or schematically shown for convenience and clarity of explanation. In addition, the size of each component does not necessarily reflect the actual size.

Hereinafter, a light emitting device, a light emitting device package, a light unit, and a light emitting device manufacturing method according to embodiments will be described in detail with reference to the accompanying drawings.

1 is a view showing a light emitting device according to an embodiment.

As shown in FIG. 1, the light emitting device according to the embodiment may include a light emitting structure 40, an ohmic contact layer 53, a first electrode 73, and a second electrode 55.

The light emitting structure 40 may include a first conductive semiconductor layer 41, an active layer 43, and a second conductive semiconductor layer 45. For example, the first conductivity type semiconductor layer 41 is formed of an n type semiconductor layer to which an n type dopant is added as a first conductivity type dopant, and the second conductivity type semiconductor layer 45 is a second conductivity type dopant. As a p-type dopant may be formed as a p-type semiconductor layer. In addition, the first conductive semiconductor layer 41 may be formed of a p-type semiconductor layer, and the second conductive semiconductor layer 45 may be formed of an n-type semiconductor layer.

The first conductivity type semiconductor layer 41 may include, for example, an n type semiconductor layer. The first conductive semiconductor layer 41 is a semiconductor material having a compositional formula of _{In x Al y Ga 1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x + y≤1) Can be implemented. The first conductive semiconductor layer 41 may be selected from, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, and the like. N-type dopants such as Te and the like may be doped.

In the active layer 43, electrons (or holes) injected through the first conductivity type semiconductor layer 41 and holes (or electrons) injected through the second conductivity type semiconductor layer 45 meet each other. The layer emits light due to a band gap difference between energy bands of the active layer 43. The active layer 43 may be formed of any one of a single quantum well structure, a multi quantum well structure (MQW), a quantum dot structure, or a quantum line structure, but is not limited thereto.

For example, the active layer 43 may be formed of a semiconductor material having a composition formula of In _x Al _y Ga _{1 -x- y} N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). have. When the active layer 43 is implemented as the multi quantum well structure, the active layer 43 may be implemented by stacking a plurality of well layers and a plurality of barrier layers, for example, an InGaN well layer / GaN barrier layer. It can be implemented in the cycle of.

The second conductive semiconductor layer 45 may be implemented with, for example, a p-type semiconductor layer. The second conductive type semiconductor layer 45 is a semiconductor material having a compositional formula of _{In x Al y Ga 1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x + y≤1) Can be implemented. The second conductive semiconductor layer 45 may be selected from, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, and the like, and Mg, Zn, Ca, and Sr. P-type dopants, such as Ba, may be doped.

Meanwhile, the first conductive semiconductor layer 41 may include a p-type semiconductor layer, and the second conductive semiconductor layer 45 may include an n-type semiconductor layer. In addition, a semiconductor layer including an n-type or p-type semiconductor layer may be further formed below the second conductive semiconductor layer 45. Accordingly, the light emitting structure 40 may have at least one of np, pn, npn, and pnp junction structures. In addition, the doping concentrations of the impurities in the first conductive semiconductor layer 41 and the second conductive semiconductor layer 45 may be uniformly or non-uniformly formed. That is, the structure of the light emitting structure 40 may be formed in various ways, but is not limited thereto.

In addition, a first conductivity type InGaN / GaN superlattice structure or an InGaN / InGaN superlattice structure may be formed between the first conductivity type semiconductor layer 41 and the active layer 43. In addition, a second conductive AlGaN layer may be formed between the second conductive semiconductor layer 45 and the active layer 43.

The ohmic contact layer 53 and the second electrode 55 may be disposed under the light emitting structure 40. The first electrode 73 may be disposed on the light emitting structure 40. The first electrode 73 and the second electrode 55 may provide power to the light emitting structure 40. The ohmic contact layer 53 may be formed to be in ohmic contact with the light emitting structure 40. In addition, the second electrode 55 may perform a function of increasing the amount of light extracted to the outside by reflecting light incident from the light emitting structure 40.

The ohmic contact layer 53 may be formed of, for example, a transparent conductive oxide layer. The ohmic contact layer 53 may be, for example, indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide (AGZO), indium zinc tin oxide (IZTO), or indium Aluminum Zinc Oxide (IGZO), Indium Gallium Zinc Oxide (IGZO), Indium Gallium Tin Oxide (IGTO), Antimony Tin Oxide (ATO), Gallium Zinc Oxide (GZO), IZON (IZO Nitride), ZnO, IrOx, RuOx, NiO It may be formed of at least one material.

The second electrode 55 may be formed of a metal material having a high reflectance. For example, the second electrode 55 may be formed of a metal or an alloy including at least one of Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Cu, Au, and Hf. In addition, the second electrode 55 may be formed of the metal or the alloy and Indium-Tin-Oxide (ITO), Indium-Zinc-Oxide (IZO), Indium-Zinc-Tin-Oxide (IZTO), and Indium-Aluminum-IAZO. Transmissive conductive materials such as Zinc-Oxide), Indium-Gallium-Zinc-Oxide (IGZO), Indium-Gallium-Tin-Oxide (IGTO), Aluminum-Zinc-Oxide (AZO) It can be formed into a multi-layer using. For example, in an embodiment, the second electrode 55 may include at least one of Ag, Al, Ag-Pd-Cu alloy, or Ag-Cu alloy.

A current blocking layer (CBL) 51 may be disposed between the light emitting structure 40 and the ohmic contact layer 53. The current blocking layer 51 may be formed in a region where at least a portion of the current blocking layer 51 overlaps with the first electrode 73. Accordingly, the phenomenon in which current is concentrated at the shortest distance between the first electrode 73 and the second electrode 53 may be alleviated, thereby improving luminous efficiency of the light emitting device according to the embodiment.

The current blocking layer 51 may have electrical insulation or may be formed using a material for forming a schottky contact with the light emitting structure 40. The current blocking layer 51 may be formed of an oxide, nitride, or metal. The current blocking layer 51 may include, for example, at least one of SiO ₂ , SiO _x , SiO _x N _y , Si ₃ N ₄ , Al ₂ O _{3 ,} TiO _x , Ti, Al, Cr. .

The current blocking layer 51 may be disposed in a first area under the light emitting structure 40, and the ohmic contact layer 53 may include a second area under the light emitting structure 40 and the current blocking layer ( 51) can be placed below. The ohmic contact layer 53 may be disposed between the light emitting structure 40 and the second electrode 55. In addition, the ohmic contact layer 53 may be disposed between the current blocking layer 51 and the second electrode 55.

A diffusion barrier layer 57, a bonding layer 59, and a conductive support member 61 may be disposed under the second electrode 55. The diffusion barrier layer 57 may function to prevent a material included in the bonding layer 59 from being diffused toward the second electrode 55 in a process in which the bonding layer 59 is provided. . The diffusion barrier layer 57 may prevent a material such as tin (Sn) included in the bonding layer 59 from affecting the second electrode 55 or the like. The diffusion barrier layer may include at least one of Cu, Ni, Ti-W, W, and Pt materials. The bonding layer 59 may include a barrier metal or a bonding metal, and may include, for example, at least one of Ti, Au, Sn, Ni, Cr, Ga, In, Bi, Cu, Ag, or Ta. . The conductive support member 61 may support the light emitting device according to the embodiment and may be electrically connected to an external electrode to provide power to the light emitting structure 40. The conductive support member 61 may be, for example, a semiconductor substrate in which Ti, Cr, Ni, Al, Pt, Au, W, Cu, Mo, Cu-W or impurities are implanted (eg, Si, Ge, GaN, GaAs). , ZnO, SiC, SiGe, etc.). On the other hand, the conductive support member 61 may not be provided.

A protective layer 71 may be further disposed on the light emitting structure 40. The protective layer 71 may be formed of oxide or nitride. The protective layer 71 is, for example, SiO ₂ , SiO _x , SiO _x N _y , Si ₃ N ₄ , Al ₂ O ₃ It may be formed of a material having a light transmitting and insulating properties. The protective layer 71 may be provided on the side surface of the light emitting structure 40. In addition, the protective layer 71 may be provided not only on the side surface of the light emitting structure 40 but also on the upper side. First unevenness may be provided on an upper surface of the protective layer 71. As the upper surface of the protective layer 71 is provided in the uneven shape as described above, the light extraction efficiency can be improved.

In addition, the first electrode 73 may be provided with second unevenness corresponding to the first unevenness. That is, the bottom surface of the first electrode 73 may be formed with irregularities in a shape corresponding to the first irregularities.

In the light emitting device according to the embodiment, the angle θ formed between the side surface of the light emitting structure 40 and the bottom surface of the light emitting structure 40 may be provided to 35 degrees to 70 degrees. Alternatively, in the light emitting device according to the embodiment, the angle θ formed between the side surface of the light emitting structure 40 and the bottom surface of the light emitting structure 40 may be provided to 40 degrees to 50 degrees. As such, the side surface of the light emitting structure 40 is inclined, for example, about 45 degrees, thereby further improving light extraction efficiency. A method for controlling the inclination angle of the side surface of the light emitting structure 40 will be described in detail with reference to a method of manufacturing a light emitting device according to an embodiment.

Next, a method of manufacturing the light emitting device according to the embodiment will be described with reference to FIGS. 2 to 13.

According to the light emitting device manufacturing method according to the embodiment, as shown in FIG. 2, the first mask 21 for patterning is formed on the growth substrate 10. For example, the first mask 21 may be formed in a desired pattern through a photolithography process. The growth substrate 10 may be formed of, for example, at least one of sapphire substrate (Al ₂ O ₃ ), SiC, GaAs, GaN, ZnO, Si, GaP, InP, Ge, but is not limited thereto.

Subsequently, as shown in FIG. 3, etching is performed to provide a growth substrate 10a having a recess 22 formed between the partition 13 and the partitions. In this case, the etching may be performed using dry etching as an example. At this time, it is possible to control the inclination angle of the partition wall 13 of the growth substrate 10a by controlling the etching conditions. In FIG. 3, a growth substrate 10a having one recess 22 is illustrated, but a plurality of recesses 22 may be arranged in the growth substrate 10a.

Next, as shown in FIG. 4, after the first mask 21 is removed, a growth prevention layer 31 is formed on the growth substrate 10a. The growth prevention layer 31 may be formed of, for example, an oxide film. The growth prevention layer 31 may include SiO ₂ , Al ₂ O _3, or the like.

As shown in FIG. 5, a second mask 35 is formed on the growth substrate 10a and the growth prevention layer 31 and is etched to form the growth prevention layer 31 between the partitions 13. Expose The second mask 35 may be formed in a desired shape through, for example, a photolithography process. The second mask 35 may be formed of a photosensitive material.

Accordingly, as shown in FIG. 6, the growth substrate 10a is exposed on the bottom surface of the recess 22 by etching using the second mask 35, and the growth prevention layer 31a is exposed. Is present in the partition 13 of the growth substrate 10a. Thereafter, the second mask 35 is removed. Through such a process, the growth substrate 10a may have sidewalls having an inclination.

Subsequently, as shown in FIG. 7, the first conductive semiconductor layer 41, the active layer 43, and the second conductive semiconductor layer 45 are formed in the recess 22 of the growth substrate 10a. To grow. The first conductive semiconductor layer 41, the active layer 43, and the second conductive semiconductor layer 45 may be defined as a light emitting structure 40. Since the growth prevention layer 31a is present on the partition 13 of the growth substrate 10a, growth may start only on the bottom surface of the recess 22.

A buffer layer may be further formed between the first conductivity type semiconductor layer 41 and the growth substrate 10a.

For example, the first conductivity type semiconductor layer 41 is formed of an n type semiconductor layer to which an n type dopant is added as a first conductivity type dopant, and the second conductivity type semiconductor layer 45 is a second conductivity type dopant. As a p-type dopant may be formed as a p-type semiconductor layer. In addition, the first conductive semiconductor layer 41 may be formed of a p-type semiconductor layer, and the second conductive semiconductor layer 45 may be formed of an n-type semiconductor layer.

The first conductivity-type semiconductor layer 41 may include, for example, an n-type semiconductor layer. The first conductive semiconductor layer 41 is a semiconductor material having a compositional formula of _{In x Al y Ga 1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x + y≤1) Can be formed. The first conductive semiconductor layer 41 may be selected from, for example, InAlGaN, GaN, AlGaN, AlInN, InGaN, AlN, InN, or the like, and may be doped with an n-type dopant such as Si, Ge, Sn, or the like.

In the active layer 43, electrons (or holes) injected through the first conductivity type semiconductor layer 41 and holes (or electrons) injected through the second conductivity type semiconductor layer 45 meet each other. The layer emits light due to a band gap difference between energy bands of the active layer 43. The active layer 43 may be formed of any one of a single quantum well structure, a multi quantum well structure (MQW), a quantum dot structure, or a quantum line structure, but is not limited thereto.

The active layer 43 may be formed of a semiconductor material having a compositional formula of _{In x Al y Ga 1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x + y≤1). When the active layer 43 is formed of the multi quantum well structure, the active layer 43 may be formed by stacking a plurality of well layers and a plurality of barrier layers. For example, an InGaN well layer / GaN barrier layer may be formed. It may be formed in a cycle.

The second conductive semiconductor layer 45 may be implemented with, for example, a p-type semiconductor layer. The second conductive type semiconductor layer 45 is a semiconductor material having a compositional formula of _{In x Al y Ga 1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x + y≤1) Can be formed. The second conductive semiconductor layer 45 may be selected from, for example, InAlGaN, GaN, AlGaN, InGaN, AlInN, AlN, InN, and the like, and dopants such as Mg, Zn, Ca, Sr, and Ba may be doped. Can be.

Meanwhile, the first conductive semiconductor layer 41 may include a p-type semiconductor layer, and the second conductive semiconductor layer 45 may include an n-type semiconductor layer. In addition, a semiconductor layer including an n-type or p-type semiconductor layer may be further formed on the second conductivity-type semiconductor layer 45. Accordingly, the light emitting structure 40 may be np, pn, npn, or pnp junctions. It may have at least one of the structures. In addition, the doping concentrations of the impurities in the first conductive semiconductor layer 41 and the second conductive semiconductor layer 45 may be uniformly or non-uniformly formed. That is, the structure of the light emitting structure 40 may be formed in various ways, but is not limited thereto.

In addition, a first conductivity type InGaN / GaN superlattice structure or an InGaN / InGaN superlattice structure may be formed between the first conductivity type semiconductor layer 41 and the active layer 43. In addition, a second conductive AlGaN layer may be formed between the second conductive semiconductor layer 45 and the active layer 43.

Subsequently, as illustrated in FIG. 8, a current blocking layer 51, an ohmic contact layer 53, a second electrode 55, a diffusion barrier layer 57, and a bonding are formed on the second conductive semiconductor layer 13. The layer 59 and the conductive support member 61 may be formed.

The current blocking layer 51 may have electrical insulation or may be formed using a material for forming a schottky contact with the light emitting structure 40. The current blocking layer 51 may be formed of an oxide, nitride, or metal. The current blocking layer 51 may include, for example, at least one of SiO ₂ , SiO _x , SiO _x N _y , Si ₃ N ₄ , Al ₂ O _{3 ,} TiO _x , Ti, Al, Cr. .

The ohmic contact layer 53 may be formed to be in ohmic contact with the light emitting structure 40. The ohmic contact layer 53 may be formed of, for example, a transparent conductive oxide layer. The ohmic contact layer 53 may be, for example, indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide (AGZO), indium zinc tin oxide (IZTO), or indium Aluminum Zinc Oxide (IGZO), Indium Gallium Zinc Oxide (IGZO), Indium Gallium Tin Oxide (IGTO), Antimony Tin Oxide (ATO), Gallium Zinc Oxide (GZO), IZON (IZO Nitride), ZnO, IrOx, RuOx, NiO It may be formed of at least one material.

The second electrode 55 may be formed of a metal material having a high reflectance. For example, the second electrode 55 may be formed of a metal or an alloy including at least one of Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Cu, Au, and Hf. In addition, the second electrode 55 may be formed of the metal or the alloy and Indium-Tin-Oxide (ITO), Indium-Zinc-Oxide (IZO), Indium-Zinc-Tin-Oxide (IZTO), and Indium-Aluminum-IAZO. Transmissive conductive materials such as Zinc-Oxide), Indium-Gallium-Zinc-Oxide (IGZO), Indium-Gallium-Tin-Oxide (IGTO), Aluminum-Zinc-Oxide (AZO) It can be formed into a multi-layer using. For example, in an embodiment, the second electrode 55 may include at least one of Ag, Al, Ag-Pd-Cu alloy, or Ag-Cu alloy.

The diffusion barrier layer 57 may function to prevent a material included in the bonding layer 59 from being diffused toward the second electrode 55 in a process in which the bonding layer 59 is provided. . The diffusion barrier layer 57 may prevent a material such as tin (Sn) included in the bonding layer 59 from affecting the second electrode 55 or the like. The diffusion barrier layer may include at least one of Cu, Ni, Ti-W, W, and Pt materials.

The bonding layer 59 may include a barrier metal or a bonding metal, and may include, for example, at least one of Ti, Au, Sn, Ni, Cr, Ga, In, Bi, Cu, Ag, or Ta. . The conductive support member 61 may support the light emitting device according to the embodiment and may be electrically connected to an external electrode to provide power to the light emitting structure 40. The conductive support member 61 may be, for example, a carrier wafer (eg, Si, Ge, Ti, Cr, Ni, Al, Pt, Au, W, Cu, Mo, Cu-W, or a semiconductor substrate into which impurities are implanted). GaN, GaAs, ZnO, SiC, SiGe, etc.) may be formed of at least one.

Next, as shown in FIG. 9, the growth substrate 10a is removed from the light emitting structure 40. As an example, the growth substrate 10a may be removed by a laser lift off (LLO) process. The laser lift-off process (LLO) is a process of peeling the growth substrate 10a and the light emitting structure 40 from each other by irradiating a laser onto the lower surface of the growth substrate 10a.

In general, when the light emitting structure 40 and the growth substrate 10a are separated through a lift-off process, damage may occur to the light emitting structure 40 while stress is transmitted to the light emitting structure 40 during the separation process. have. The stress may be generated during the growth process of the light emitting structure 40 and may be concentrated at an interface between the growth substrate 10a and the light emitting structure 40. The stress may increase as the size of the growth substrate 10a increases. Accordingly, as the size of the growth substrate 10a increases, more light emitting structures 40 may be generated during the separation process.

On the other hand, according to the embodiment, the light emitting structure 40 and the growth substrate 10a is separated through the lift-off process, the magnitude of the stress transmitted to the light emitting structure 40 is the recess 23 It may correspond to the size of. That is, according to the embodiment, since the light emitting structure 40 grows in a chip size corresponding to the size of the recess 23, the light emitting structure 40 is generated at the interface of the growth substrate 10a as the light emitting structure 40 grows. The magnitude of the stress can be significantly reduced compared to the conventional. Accordingly, in separating the growth substrate 10a and the light emitting structure 40 through a lift-off process, damage to the light emitting structure 40 can be significantly reduced. As described above, according to the method of manufacturing the light emitting device, the manufacturing yield can be improved.

Next, as shown in FIG. 10, first unevenness is formed on an upper surface of the first conductivity-type semiconductor layer 41. Accordingly, the light extraction efficiency can be improved.

11, the passivation layer 71 and the first electrode 73 are formed in the light emitting structure 40. The protective layer 71 may be formed of oxide or nitride. The protective layer 71 is, for example, SiO ₂ , SiO _x , SiO _x N _y , Si ₃ N ₄ , Al ₂ O ₃ It may be formed of a material having a light transmitting and insulating properties. The protective layer 71 may be formed by, for example, a deposition method such as electron beam deposition, PECVD, and sputtering. The first electrode 73 is electrically connected to the light emitting structure 40. The first electrode 73 may provide power to the light emitting structure 40 together with the second electrode 55, and may be formed to overlap at least a portion of the current blocking layer 51 in a vertical direction.

Next, as shown in FIGS. 12 and 13, isolation etching is performed along the boundary of the light emitting device. Accordingly, an individual light emitting device according to the embodiment can be manufactured. The isolation etching can be performed by, for example, dry etching such as ICP (Inductively Coupled Plasma), but is not limited thereto.

In the light emitting device according to the embodiment, the angle θ formed between the side surface of the light emitting structure 40 and the bottom surface of the light emitting structure 40 may be provided to 35 degrees to 70 degrees. Alternatively, in the light emitting device according to the embodiment, the angle θ formed between the side surface of the light emitting structure 40 and the bottom surface of the light emitting structure 40 may be provided to 40 degrees to 50 degrees. As such, the side surface of the light emitting structure 40 is inclined, for example, about 45 degrees, thereby further improving light extraction efficiency.

14 is a view showing a light emitting device according to another embodiment.

As illustrated in FIG. 14, the light emitting device according to the embodiment may include a light emitting structure 40, an ohmic contact layer 53, a first electrode 73, and a second electrode 55.

The light emitting structure 40 may include a first conductive semiconductor layer 41, an active layer 43, and a second conductive semiconductor layer 45. For example, the first conductivity type semiconductor layer 41 is formed of an n type semiconductor layer to which an n type dopant is added as a first conductivity type dopant, and the second conductivity type semiconductor layer 45 is a second conductivity type dopant. As a p-type dopant may be formed as a p-type semiconductor layer. In addition, the first conductive semiconductor layer 41 may be formed of a p-type semiconductor layer, and the second conductive semiconductor layer 45 may be formed of an n-type semiconductor layer.

The first conductivity type semiconductor layer 41 may include, for example, an n type semiconductor layer. The first conductive semiconductor layer 41 is a semiconductor material having a compositional formula of _{In x Al y Ga 1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x + y≤1) Can be implemented. The first conductive semiconductor layer 41 may be selected from, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, and the like. N-type dopants such as Te and the like may be doped.

In the active layer 43, electrons (or holes) injected through the first conductivity type semiconductor layer 41 and holes (or electrons) injected through the second conductivity type semiconductor layer 45 meet each other. The layer emits light due to a band gap difference between energy bands of the active layer 43. The active layer 43 may be formed of any one of a single quantum well structure, a multi quantum well structure (MQW), a quantum dot structure, or a quantum line structure, but is not limited thereto.

For example, the active layer 43 may be formed of a semiconductor material having a composition formula of In _x Al _y Ga _{1 -x- y} N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). have. When the active layer 43 is implemented as the multi quantum well structure, the active layer 43 may be implemented by stacking a plurality of well layers and a plurality of barrier layers, for example, an InGaN well layer / GaN barrier layer. It can be implemented in the cycle of.

The second conductive semiconductor layer 45 may be implemented with, for example, a p-type semiconductor layer. The second conductive type semiconductor layer 45 is a semiconductor material having a compositional formula of _{In x Al y Ga 1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x + y≤1) Can be implemented. The second conductive semiconductor layer 45 may be selected from, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, and the like, and Mg, Zn, Ca, and Sr. P-type dopants, such as Ba, may be doped.

Meanwhile, the first conductive semiconductor layer 41 may include a p-type semiconductor layer, and the second conductive semiconductor layer 45 may include an n-type semiconductor layer. In addition, a semiconductor layer including an n-type or p-type semiconductor layer may be further formed below the second conductive semiconductor layer 45. Accordingly, the light emitting structure 40 may have at least one of np, pn, npn, and pnp junction structures. In addition, the doping concentrations of the impurities in the first conductive semiconductor layer 41 and the second conductive semiconductor layer 45 may be uniformly or non-uniformly formed. That is, the structure of the light emitting structure 40 may be formed in various ways, but is not limited thereto.

In addition, a first conductivity type InGaN / GaN superlattice structure or an InGaN / InGaN superlattice structure may be formed between the first conductivity type semiconductor layer 41 and the active layer 43. In addition, a second conductive AlGaN layer may be formed between the second conductive semiconductor layer 45 and the active layer 43.

The ohmic contact layer 53 and the second electrode 55 may be disposed under the light emitting structure 40. The first electrode 73 may be disposed on the light emitting structure 40. The first electrode 73 and the second electrode 55 may provide power to the light emitting structure 40. The ohmic contact layer 53 may be formed to be in ohmic contact with the light emitting structure 40. In addition, the second electrode 55 may perform a function of increasing the amount of light extracted to the outside by reflecting light incident from the light emitting structure 40.

The ohmic contact layer 53 may be formed of, for example, a transparent conductive oxide layer. The ohmic contact layer 53 may be, for example, indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide (AGZO), indium zinc tin oxide (IZTO), or indium Aluminum Zinc Oxide (IGZO), Indium Gallium Zinc Oxide (IGZO), Indium Gallium Tin Oxide (IGTO), Antimony Tin Oxide (ATO), Gallium Zinc Oxide (GZO), IZON (IZO Nitride), ZnO, IrOx, RuOx, NiO It may be formed of at least one material.

The second electrode 55 may be formed of a metal material having a high reflectance. For example, the second electrode 55 may be formed of a metal or an alloy including at least one of Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Cu, Au, and Hf. In addition, the second electrode 55 may be formed of the metal or the alloy and Indium-Tin-Oxide (ITO), Indium-Zinc-Oxide (IZO), Indium-Zinc-Tin-Oxide (IZTO), and Indium-Aluminum-IAZO. Transmissive conductive materials such as Zinc-Oxide), Indium-Gallium-Zinc-Oxide (IGZO), Indium-Gallium-Tin-Oxide (IGTO), Aluminum-Zinc-Oxide (AZO) It can be formed into a multi-layer using. For example, in an embodiment, the second electrode 55 may include at least one of Ag, Al, Ag-Pd-Cu alloy, or Ag-Cu alloy.

A current blocking layer (CBL) 51 may be disposed between the light emitting structure 40 and the ohmic contact layer 53. The current blocking layer 51 may be formed in a region where at least a portion of the current blocking layer 51 overlaps with the first electrode 73. Accordingly, the phenomenon in which current is concentrated at the shortest distance between the first electrode 73 and the second electrode 53 may be alleviated, thereby improving luminous efficiency of the light emitting device according to the embodiment.

The current blocking layer 51 may have electrical insulation or may be formed using a material for forming a schottky contact with the light emitting structure 40. The current blocking layer 51 may be formed of an oxide, nitride, or metal. The current blocking layer 51 may include, for example, at least one of SiO ₂ , SiO _x , SiO _x N _y , Si ₃ N ₄ , Al ₂ O _{3 ,} TiO _x , Ti, Al, Cr. .

The current blocking layer 51 may be disposed in a first area under the light emitting structure 40, and the ohmic contact layer 53 may include a second area under the light emitting structure 40 and the current blocking layer ( 51) can be placed below. The ohmic contact layer 53 may be disposed between the light emitting structure 40 and the second electrode 55. In addition, the ohmic contact layer 53 may be disposed between the current blocking layer 51 and the second electrode 55.

A diffusion barrier layer 57, a bonding layer 59, and a conductive support member 61 may be disposed under the second electrode 55. The diffusion barrier layer 57 may function to prevent a material included in the bonding layer 59 from being diffused toward the second electrode 55 in a process in which the bonding layer 59 is provided. . The diffusion barrier layer 57 may prevent a material such as tin (Sn) included in the bonding layer 59 from affecting the second electrode 55 or the like. The diffusion barrier layer may include at least one of Cu, Ni, Ti-W, W, and Pt materials. The bonding layer 59 may include a barrier metal or a bonding metal, and may include, for example, at least one of Ti, Au, Sn, Ni, Cr, Ga, In, Bi, Cu, Ag, or Ta. . The conductive support member 61 may support the light emitting device according to the embodiment and may be electrically connected to an external electrode to provide power to the light emitting structure 40. The conductive support member 61 may be, for example, a semiconductor substrate in which Ti, Cr, Ni, Al, Pt, Au, W, Cu, Mo, Cu-W or impurities are implanted (eg, Si, Ge, GaN, GaAs). , ZnO, SiC, SiGe, etc.). On the other hand, the conductive support member 61 may not be provided.

A protective layer 71 may be further disposed on the light emitting structure 40. The protective layer 71 may be formed of oxide or nitride. The protective layer 71 is, for example, SiO ₂ , SiO _x , SiO _x N _y , Si ₃ N ₄ , Al ₂ O ₃ It may be formed of a material having a light transmitting and insulating properties. The protective layer 71 may be provided on the side surface of the light emitting structure 40. In addition, the protective layer 71 may be provided not only on the side surface of the light emitting structure 40 but also on the upper side. First unevenness may be provided on an upper surface of the protective layer 71. As the upper surface of the protective layer 71 is provided in the uneven shape as described above, the light extraction efficiency can be improved.

In addition, the first electrode 73 may be provided with second unevenness corresponding to the first unevenness. That is, the bottom surface of the first electrode 73 may be formed with irregularities in a shape corresponding to the first irregularities.

In the light emitting device according to the embodiment, the angle θ formed between the side surface of the light emitting structure 40 and the bottom surface of the light emitting structure 40 may be provided to 35 degrees to 70 degrees. Alternatively, in the light emitting device according to the embodiment, the angle θ formed between the side surface of the light emitting structure 40 and the bottom surface of the light emitting structure 40 may be provided to 40 degrees to 50 degrees. As such, the side surface of the light emitting structure 40 is inclined to about 45 degrees to further improve the light extraction efficiency.

In addition, the light emitting device according to the embodiment, the side surface of the light emitting structure 40 includes a first inclined surface and the second inclined surface, is connected with a step between the first inclined surface and the second inclined surface. In this case, the first inclined surface and the second inclined surface may be provided in parallel with each other. The step between the first inclined surface and the second inclined surface may be provided within 5 micrometers. For example, the step between the first inclined surface and the second inclined surface may be provided as 1 micrometer to 5 micrometers.

A method for controlling the side inclination angle and the step of the light emitting structure 40 will be described in more detail with reference to a method of manufacturing a light emitting device according to the following embodiments.

Next, a method of manufacturing the light emitting device according to the embodiment will be described with reference to FIGS. 15 to 29.

According to the light emitting device manufacturing method according to the embodiment, as shown in FIG. 15, the first mask 21 for patterning is formed on the growth substrate 10. For example, the first mask 21 may be formed in a desired pattern through a photolithography process. The growth substrate 10 may be formed of, for example, at least one of sapphire substrate (Al ₂ O ₃ ), SiC, GaAs, GaN, ZnO, Si, GaP, InP, Ge, but is not limited thereto.

Subsequently, as shown in FIG. 16, etching is performed to provide a growth substrate 10a in which a first recess 22 is formed between the first partition wall 15 and the first partition walls. In this case, the etching may be performed using dry etching as an example. In this case, the inclination angle of the first partition wall 15 of the growth substrate 10a may be controlled by controlling the etching condition.

As shown in FIG. 17, a second mask 23 is formed in a portion of an upper portion of the first partition wall 15 of the growth substrate 10a. For example, the second mask 23 may be formed in a desired pattern through a photolithography process.

Next, as shown in FIG. 18, etching is performed to provide a growth substrate 10b having a second partition 17 and a second recess 24 formed between the second partitions. In this case, the etching may be performed using dry etching as an example. At this time, the inclination angle of the growth substrate 10b can be controlled by controlling the etching conditions.

Subsequently, as shown in FIGS. 19 and 20, a third mask 25 is formed and etched on a portion of the upper part of the second partition wall 17 of the growth substrate 10b to etch the third partition wall 19 and A growth substrate 10c having a third recess 26 formed therebetween is provided. At this time, it is possible to control the inclination angle of the growth substrate 10c by controlling the etching conditions. 20 illustrates a growth substrate 10c having one third recess 26 formed therein, but a plurality of third recesses 26 may be arranged in the growth substrate 10c.

Next, as shown in FIG. 21, after the third mask 25 is removed, a growth prevention layer 31 is formed on the growth substrate 10c. The growth prevention layer 31 may be formed of, for example, an oxide film. The growth prevention layer 31 may include SiO ₂ , Al ₂ O _3, or the like.

As shown in FIG. 21, a fourth mask 35 is formed on the growth substrate 10c and the growth prevention layer 31 and is etched to form the fourth layer 35 between the third barrier walls 19. 31). The fourth mask 35 may be formed in a desired shape through, for example, a photolithography process. The fourth mask 35 may be formed of a photosensitive material.

Accordingly, as shown in FIG. 26, the growth substrate 10c is exposed on the bottom surface of the third recess 26 by etching by using the fourth mask 35, and the growth prevention layer ( 31a) is present in the third partition wall 19 of the growth substrate 10c. Thereafter, the fourth mask 35 is removed. Through such a process, the growth substrate 10c may have sidewalls having an inclination and a step.

Subsequently, as illustrated in FIG. 23, the first conductive semiconductor layer 41, the active layer 43, and the second conductive semiconductor layer (3) are formed in the third recess 26 of the growth substrate 10c. 45) grow. The first conductive semiconductor layer 41, the active layer 43, and the second conductive semiconductor layer 45 may be defined as a light emitting structure 40. Since the growth prevention layer 31a is present on the sidewall of the growth substrate 10c, growth may be started only at the bottom surface of the third recess 26.

A buffer layer may be further formed between the first conductive semiconductor layer 41 and the growth substrate 10c.

For example, the first conductivity type semiconductor layer 41 is formed of an n type semiconductor layer to which an n type dopant is added as a first conductivity type dopant, and the second conductivity type semiconductor layer 45 is a second conductivity type dopant. As a p-type dopant may be formed as a p-type semiconductor layer. In addition, the first conductive semiconductor layer 41 may be formed of a p-type semiconductor layer, and the second conductive semiconductor layer 45 may be formed of an n-type semiconductor layer.

The first conductivity-type semiconductor layer 41 may include, for example, an n-type semiconductor layer. The first conductive semiconductor layer 41 is a semiconductor material having a compositional formula of _{In x Al y Ga 1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x + y≤1) Can be formed. The first conductive semiconductor layer 41 may be selected from, for example, InAlGaN, GaN, AlGaN, AlInN, InGaN, AlN, InN, or the like, and may be doped with an n-type dopant such as Si, Ge, Sn, or the like.

In the active layer 43, electrons (or holes) injected through the first conductivity type semiconductor layer 41 and holes (or electrons) injected through the second conductivity type semiconductor layer 45 meet each other. The layer emits light due to a band gap difference between energy bands of the active layer 43. The active layer 43 may be formed of any one of a single quantum well structure, a multi quantum well structure (MQW), a quantum dot structure, or a quantum line structure, but is not limited thereto.

The active layer 43 may be formed of a semiconductor material having a compositional formula of _{In x Al y Ga 1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x + y≤1). When the active layer 43 is formed of the multi quantum well structure, the active layer 43 may be formed by stacking a plurality of well layers and a plurality of barrier layers. For example, an InGaN well layer / GaN barrier layer may be formed. It may be formed in a cycle.

The second conductive semiconductor layer 45 may be implemented with, for example, a p-type semiconductor layer. The second conductive type semiconductor layer 45 is a semiconductor material having a compositional formula of _{In x Al y Ga 1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x + y≤1) Can be formed. The second conductive semiconductor layer 45 may be selected from, for example, InAlGaN, GaN, AlGaN, InGaN, AlInN, AlN, InN, and the like, and dopants such as Mg, Zn, Ca, Sr, and Ba may be doped. Can be.

Meanwhile, the first conductive semiconductor layer 41 may include a p-type semiconductor layer, and the second conductive semiconductor layer 45 may include an n-type semiconductor layer. In addition, a semiconductor layer including an n-type or p-type semiconductor layer may be further formed on the second conductivity-type semiconductor layer 45. Accordingly, the light emitting structure 40 may be np, pn, npn, or pnp junctions. It may have at least one of the structures. In addition, the doping concentrations of the impurities in the first conductive semiconductor layer 41 and the second conductive semiconductor layer 45 may be uniformly or non-uniformly formed. That is, the structure of the light emitting structure 40 may be formed in various ways, but is not limited thereto.

In addition, a first conductivity type InGaN / GaN superlattice structure or an InGaN / InGaN superlattice structure may be formed between the first conductivity type semiconductor layer 41 and the active layer 43. In addition, a second conductive AlGaN layer may be formed between the second conductive semiconductor layer 45 and the active layer 43.

Subsequently, as illustrated in FIG. 24, a current blocking layer 51, an ohmic contact layer 53, a second electrode 55, a diffusion barrier layer 57, and a bonding are formed on the second conductive semiconductor layer 13. The layer 59 and the conductive support member 61 may be formed.

The current blocking layer 51 may have electrical insulation or may be formed using a material for forming a schottky contact with the light emitting structure 40. The current blocking layer 51 may be formed of an oxide, nitride, or metal. The current blocking layer 51 may include, for example, at least one of SiO ₂ , SiO _x , SiO _x N _y , Si ₃ N ₄ , Al ₂ O _{3 ,} TiO _x , Ti, Al, Cr. .

The ohmic contact layer 53 may be formed to be in ohmic contact with the light emitting structure 40. The ohmic contact layer 53 may be formed of, for example, a transparent conductive oxide layer. The ohmic contact layer 53 may be, for example, indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide (AGZO), indium zinc tin oxide (IZTO), or indium Aluminum Zinc Oxide (IGZO), Indium Gallium Zinc Oxide (IGZO), Indium Gallium Tin Oxide (IGTO), Antimony Tin Oxide (ATO), Gallium Zinc Oxide (GZO), IZON (IZO Nitride), ZnO, IrOx, RuOx, NiO It may be formed of at least one material.

The second electrode 55 may be formed of a metal material having a high reflectance. For example, the second electrode 55 may be formed of a metal or an alloy including at least one of Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Cu, Au, and Hf. In addition, the second electrode 55 may be formed of the metal or the alloy and Indium-Tin-Oxide (ITO), Indium-Zinc-Oxide (IZO), Indium-Zinc-Tin-Oxide (IZTO), and Indium-Aluminum-IAZO. Transmissive conductive materials such as Zinc-Oxide), Indium-Gallium-Zinc-Oxide (IGZO), Indium-Gallium-Tin-Oxide (IGTO), Aluminum-Zinc-Oxide (AZO) It can be formed into a multi-layer using. For example, in an embodiment, the second electrode 55 may include at least one of Ag, Al, Ag-Pd-Cu alloy, or Ag-Cu alloy.

The diffusion barrier layer 57 may function to prevent a material included in the bonding layer 59 from being diffused toward the second electrode 55 in a process in which the bonding layer 59 is provided. . The diffusion barrier layer 57 may prevent a material such as tin (Sn) included in the bonding layer 59 from affecting the second electrode 55 or the like. The diffusion barrier layer may include at least one of Cu, Ni, Ti-W, W, and Pt materials.

The bonding layer 59 may include a barrier metal or a bonding metal, and may include, for example, at least one of Ti, Au, Sn, Ni, Cr, Ga, In, Bi, Cu, Ag, or Ta. . The conductive support member 61 may support the light emitting device according to the embodiment and may be electrically connected to an external electrode to provide power to the light emitting structure 40. The conductive support member 61 may be, for example, a carrier wafer (eg, Si, Ge, Ti, Cr, Ni, Al, Pt, Au, W, Cu, Mo, Cu-W, or a semiconductor substrate into which impurities are implanted). GaN, GaAs, ZnO, SiC, SiGe, etc.) may be formed of at least one.

Next, as shown in FIG. 25, the growth substrate 10c is removed from the light emitting structure 40. As one example, the growth substrate 10c may be removed by a laser lift off (LLO) process. The laser lift-off process (LLO) is a process of peeling the growth substrate 10c and the light emitting structure 40 from each other by irradiating a laser onto the lower surface of the growth substrate 10c.

In general, when the light emitting structure 40 and the growth substrate 10c are separated through a lift-off process, damage may occur to the light emitting structure 40 while stress is transmitted to the light emitting structure 40 during the separation process. have. The stress may be generated during the growth of the light emitting structure 40 and may be concentrated at an interface between the growth substrate 10c and the light emitting structure 40. The stress may increase as the size of the growth substrate 10c increases. Accordingly, as the size of the growth substrate 10c increases, more light emitting structures 40 may be generated during the separation process.

On the other hand, according to the embodiment, the light emitting structure 40 and the growth substrate 10c is separated through the lift-off process, the magnitude of the stress transmitted to the light emitting structure 40 is the third recess ( 26) may correspond to the size. That is, according to the embodiment, since the light emitting structure 40 grows in a chip size corresponding to the size of the third recess 26, the light emitting structure 40 grows at the interface of the growth substrate 10c as the light emitting structure 40 grows. The magnitude of the generated stress can be significantly reduced compared to the conventional. Accordingly, in separating the growth substrate 10c and the light emitting structure 40 through a lift-off process, damage to the light emitting structure 40 can be significantly reduced. As described above, according to the method of manufacturing the light emitting device, the manufacturing yield can be improved.

Next, as shown in FIG. 26, first unevenness is formed on an upper surface of the first conductivity-type semiconductor layer 41. Accordingly, the light extraction efficiency can be improved.

As shown in FIG. 27, the passivation layer 71 and the first electrode 73 are formed in the light emitting structure 40. The protective layer 71 may be formed of oxide or nitride. The protective layer 71 is, for example, SiO ₂ , SiO _x , SiO _x N _y , Si ₃ N ₄ , Al ₂ O ₃ It may be formed of a material having a light transmitting and insulating properties. The protective layer 71 may be formed by, for example, a deposition method such as electron beam deposition, PECVD, and sputtering. The first electrode 73 is electrically connected to the light emitting structure 40. The first electrode 73 may provide power to the light emitting structure 40 together with the second electrode 55, and may be formed to overlap at least a portion of the current blocking layer 51 in a vertical direction.

Next, as shown in FIGS. 28 and 29, isolation etching is performed along the boundary of the light emitting device. Accordingly, an individual light emitting device according to the embodiment can be manufactured. The isolation etching can be performed by, for example, dry etching such as ICP (Inductively Coupled Plasma), but is not limited thereto.

In the light emitting device according to the embodiment, the angle θ formed between the side surface of the light emitting structure 40 and the bottom surface of the light emitting structure 40 may be provided to 35 degrees to 70 degrees. Alternatively, in the light emitting device according to the embodiment, the angle θ formed between the side surface of the light emitting structure 40 and the bottom surface of the light emitting structure 40 may be provided to 40 degrees to 50 degrees. As such, the side surface of the light emitting structure 40 is inclined to about 45 degrees to further improve the light extraction efficiency.

In addition, the light emitting device according to the embodiment, the side surface of the light emitting structure 40 includes a first inclined surface and the second inclined surface, is connected with a step between the first inclined surface and the second inclined surface. In this case, the first inclined surface and the second inclined surface may be provided in parallel with each other. The step between the first inclined surface and the second inclined surface may be provided within 5 micrometers. For example, the step between the first inclined surface and the second inclined surface may be provided as 1 micrometer to 5 micrometers.

30 is a view showing a light emitting device package to which the light emitting device according to the embodiment is applied.

Referring to FIG. 30, the light emitting device package according to the embodiment may include a body 120, a first lead electrode 131 and a second lead electrode 132 disposed on the body 120, and the body 120. The light emitting device 100 according to the embodiment, which is provided to and electrically connected to the first lead electrode 31 and the second lead electrode 32, and the molding member 140 surrounding the light emitting device 100. Include.

The body 120 may include a silicon material, a synthetic resin material, or a metal material, and an inclined surface may be formed around the light emitting device 100.

The first lead electrode 131 and the second lead electrode 132 are electrically separated from each other, and provide power to the light emitting device 100. In addition, the first lead electrode 131 and the second lead electrode 132 may increase light efficiency by reflecting light generated from the light emitting device 100, and heat generated from the light emitting device 100. It may also play a role in discharging it to the outside.

The light emitting device 100 may be disposed on the body 120 or on the first lead electrode 131 or the second lead electrode 132.

The light emitting device 100 may be electrically connected to the first lead electrode 131 and the second lead electrode 132 by any one of a wire method, a flip chip method, and a die bonding method.

The molding member 140 may surround the light emitting device 100 to protect the light emitting device 100. In addition, the molding member 140 may include a phosphor to change the wavelength of light emitted from the light emitting device 100.

A plurality of light emitting devices or light emitting device packages may be arranged on a substrate, and an optical member such as a lens, a light guide plate, a prism sheet, and a diffusion sheet may be disposed on an optical path of the light emitting device package. The light emitting device package, the substrate, and the optical member may function as a light unit. The light unit may be implemented as a top view or a side view type and may be provided in a display device such as a portable terminal and a notebook computer, or may be variously applied to a lighting device and a pointing device. Another embodiment may be implemented as a lighting device including the semiconductor light emitting device or the light emitting device package described in the above embodiments. For example, the lighting device may include a lamp, a streetlight, an electric signboard, and a headlight.

The light emitting device according to the embodiment may be applied to the light unit. The light unit may include a structure in which a plurality of light emitting elements are arranged, and may include the display device illustrated in FIGS. 31 and 32 and the illumination device illustrated in FIG. 33.

Referring to FIG. 31, the display apparatus 1000 according to the exemplary embodiment may include a light guide plate 1041, a light emitting module 1031 providing light to the light guide plate 1041, and a reflective member 1022 under the light guide plate 1041. ), An optical sheet 1051 on the light guide plate 1041, a display panel 1061, a light guide plate 1041, a light emitting module 1031, and a reflective member 1022 on the optical sheet 1051. The bottom cover 1011 may be included, but is not limited thereto.

The bottom cover 1011, the reflective sheet 1022, the light guide plate 1041, and the optical sheet 1051 can be defined as a light unit 1050.

The light guide plate 1041 diffuses light to serve as a surface light source. The light guide plate 1041 is made of a transparent material, for example, acrylic resin-based such as polymethyl metaacrylate (PMMA), polyethylene terephthlate (PET), polycarbonate (PC), cycloolefin copolymer (COC), and polyethylene naphthalate (PEN). It may include one of the resins.

The light emitting module 1031 provides light to at least one side of the light guide plate 1041, and ultimately serves as a light source of the display device.

At least one light emitting module 1031 may be provided, and light may be provided directly or indirectly from one side of the light guide plate 1041. The light emitting module 1031 may include a substrate 1033 and a light emitting device 100 according to the embodiment described above. The light emitting devices 100 may be arranged on the substrate 1033 at predetermined intervals.

The substrate 1033 may be a printed circuit board (PCB) including a circuit pattern. However, the substrate 1033 may include not only a general PCB but also a metal core PCB (MCPCB, Metal Core PCB), a flexible PCB (FPCB, Flexible PCB) and the like, but is not limited thereto. When the light emitting device 100 is provided on the side surface of the bottom cover 1011 or the heat dissipation plate, the substrate 1033 may be removed. Here, a part of the heat dissipation plate may contact the upper surface of the bottom cover 1011.

The plurality of light emitting devices 100 may be mounted such that an emission surface from which light is emitted is spaced apart from the light guide plate 1041 by a predetermined distance, but is not limited thereto. The light emitting device 200 may directly or indirectly provide light to a light incident portion, which is one side of the light guide plate 1041, but is not limited thereto.

The reflective member 1022 may be disposed under the light guide plate 1041. The reflective member 1022 may improve the luminance of the light unit 1050 by reflecting light incident to the lower surface of the light guide plate 1041 and pointing upward. The reflective member 1022 may be formed of, for example, PET, PC, or PVC resin, but is not limited thereto. The reflective member 1022 may be an upper surface of the bottom cover 1011, but is not limited thereto.

The bottom cover 1011 may house the light guide plate 1041, the light emitting module 1031, the reflective member 1022, and the like. To this end, the bottom cover 1011 may be provided with a housing portion 1012 having a box-like shape with an opened upper surface, but the present invention is not limited thereto. The bottom cover 1011 may be combined with the top cover, but is not limited thereto.

The bottom cover 1011 may be formed of a metal material or a resin material, and may be manufactured using a process such as press molding or extrusion molding. In addition, the bottom cover 1011 may include a metal or a non-metal material having good thermal conductivity, but the present invention is not limited thereto.

The display panel 1061 is, for example, an LCD panel, including first and second transparent substrates facing each other, and a liquid crystal layer interposed between the first and second substrates. A polarizing plate may be attached to at least one surface of the display panel 1061, but the present invention is not limited thereto. The display panel 1061 displays information by light passing through the optical sheet 1051. The display device 1000 may be applied to various portable terminals, monitors of notebook computers, monitors of laptop computers, televisions, and the like.

The optical sheet 1051 is disposed between the display panel 1061 and the light guide plate 1041 and includes at least one light transmissive sheet. The optical sheet 1051 may include at least one of a sheet such as, for example, a diffusion sheet, a horizontal and vertical prism sheet, and a brightness enhancement sheet. The diffusion sheet diffuses the incident light, the horizontal and / or vertical prism sheet focuses the incident light into the display area, and the brightness enhancement sheet reuses the lost light to improve the brightness. A protective sheet may be disposed on the display panel 1061, but the present invention is not limited thereto.

Here, the optical path of the light emitting module 1031 may include the light guide plate 1041 and the optical sheet 1051 as an optical member, but the present invention is not limited thereto.

32 is a diagram illustrating another example of a display device according to an exemplary embodiment.

Referring to FIG. 32, the display device 1100 includes a bottom cover 1152, a substrate 1020 on which the light emitting device 100 disclosed above is arranged, an optical member 1154, and a display panel 1155.

The substrate 1020 and the light emitting device 100 may be defined as a light emitting module 1060. The bottom cover 1152, at least one light emitting module 1060, and the optical member 1154 may be defined as a light unit.

The bottom cover 1152 may include an accommodating part 1153, but is not limited thereto.

Here, the optical member 1154 may include at least one of a lens, a light guide plate, a diffusion sheet, a horizontal and vertical prism sheet, and a brightness enhancement sheet. The light guide plate may be made of a PC material or a poly methy methacrylate (PMMA) material, and the light guide plate may be removed. The diffusion sheet diffuses the incident light, the horizontal and vertical prism sheets focus the incident light onto the display area, and the brightness enhancement sheet reuses the lost light to improve the brightness.

The optical member 1154 is disposed on the light emitting module 1060, and performs surface light source, diffusion, condensing, etc. of the light emitted from the light emitting module 1060.

33 is a perspective view of a lighting apparatus according to an embodiment.

Referring to FIG. 33, the lighting device 1500 may include a case 1510, a light emitting module 1530 installed in the case 1510, and a connection terminal installed in the case 1510 and receiving power from an external power source. 1520).

The case 1510 may be formed of a material having good heat dissipation, and may be formed of, for example, a metal material or a resin material.

The light emitting module 1530 may include a substrate 1532 and a light emitting device 100 according to an embodiment provided on the substrate 1532. The plurality of light emitting devices 100 may be arranged in a matrix form or spaced apart at predetermined intervals.

The substrate 1532 may be a circuit pattern printed on an insulator. For example, a general printed circuit board (PCB), a metal core PCB, a flexible PCB, a ceramic PCB, FR-4 substrates and the like.

In addition, the substrate 1532 may be formed of a material that reflects light efficiently, or a surface may be coated with a color, for example, white or silver, in which the light is efficiently reflected.

At least one light emitting device 100 may be disposed on the substrate 1532. Each of the light emitting devices 100 may include at least one light emitting diode (LED) chip. The LED chip may include a colored light emitting diode emitting red, green, blue or white colored light, and a UV emitting diode emitting ultraviolet (UV) light.

The light emitting module 1530 may be disposed to have a combination of various light emitting devices 100 to obtain color and luminance. For example, a white light emitting diode, a red light emitting diode, and a green light emitting diode may be combined to secure high color rendering (CRI).

The connection terminal 1520 may be electrically connected to the light emitting module 1530 to supply power. The connection terminal 1520 is coupled to an external power source in a socket manner, but is not limited thereto. For example, the connection terminal 1520 may be formed in a pin shape and inserted into an external power source, or may be connected to the external power source by a wire.

According to the embodiment, after the light emitting device 200 is packaged, the light emitting device 200 may be mounted on the substrate to be implemented as a light emitting module, or may be mounted and packaged as an LED chip to be implemented as a light emitting module.

Features, structures, effects, and the like described in the above embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to only one embodiment. Further, the features, structures, effects, and the like illustrated in the embodiments can be combined and modified by other persons having ordinary skill in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

In addition, the above description has been made with reference to the embodiments, which are merely exemplary and are not intended to limit the present invention. Those skilled in the art to which the present invention pertains will be illustrated above in the range without departing from the essential characteristics of the present embodiment. It will be appreciated that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

40: light emitting structure 41: first conductive semiconductor layer
43: active layer 45: second conductive semiconductor layer
51: current blocking layer 53: ohmic contact layer
55: second electrode 57: diffusion barrier layer
59: bonding layer 71: protective layer
73: first electrode

Claims (15)

A light emitting structure including a first conductive semiconductor layer, an active layer under the first conductive semiconductor layer, and a second conductive semiconductor layer under the active layer;
A first electrode on the light emitting structure;
A second electrode under the light emitting structure; Including,
The side surface of the light emitting structure includes a first inclined surface and a second inclined surface, the first inclined surface and the second inclined surface light emitting device connected with a step. The light emitting device of claim 1, wherein the first inclined plane and the second inclined plane of the light emitting structure are parallel to each other. The light emitting device of claim 1, wherein an angle formed between the first inclined surface of the light emitting structure and the bottom surface of the light emitting structure is 35 degrees to 70 degrees. The light emitting device of claim 1, wherein the step is 1 micrometer to 5 micrometers. The light emitting device of any one of claims 1 to 4, further comprising a current blocking layer and an ohmic contact layer between the light emitting structure and the second electrode. The light emitting device according to any one of claims 1 to 4, further comprising a diffusion barrier layer and a bonding layer under the second electrode. The light emitting device of claim 6, wherein the diffusion barrier layer comprises at least one of Cu, Ni, Ti-W, W, and Pt materials. The light emitting device according to any one of claims 1 to 4, wherein first unevenness is provided on an upper surface of the first conductive semiconductor layer. The light emitting device according to claim 8, wherein the first electrode is provided with second unevenness corresponding to the first unevenness. Body;
A light emitting device disposed on the body and according to any one of claims 1 to 4;
A first lead electrode and a second lead electrode electrically connected to the light emitting element;
Light emitting device package comprising a. Board;
A light emitting element disposed on the substrate and according to any one of claims 1 to 4;
An optical member through which light provided from the light emitting device passes;
Light unit comprising a. Etching the growth substrate to form a recess between the barrier rib and the barrier rib;
Forming a growth prevention layer on the partition wall;
Forming a light emitting structure including a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, and a second conductive semiconductor layer on the active layer in the recess;
Forming a second electrode electrically connected to the second conductive semiconductor layer of the light emitting structure;
Separating the light emitting structure on which the second electrode is formed from the growth substrate and the growth prevention layer;
Forming a first electrode electrically connected to the first conductivity type semiconductor layer of the light emitting structure;
Light emitting device manufacturing method comprising a. The method of claim 12, wherein the partition includes a first inclined surface and a second inclined surface, and the first inclined surface and the second inclined surface are connected with a step difference. The method of claim 12, wherein the growth prevention layer comprises an oxide film. The method of claim 12, wherein the separating of the light emitting structure having the second electrode from the growth substrate and the growth prevention layer is performed by a laser lift-off process.

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