KR20120131115A - Multilayer connection structure and making method - Google Patents

Abstract

The method of the present invention provides electrical connections to a stack of contact levels of an interconnect area for a three dimensional stacked integrated circuit device. Each contact level includes conductive layers and insulating layers. A portion of any top layer is removed to expose the first contact level and to create contact openings for each contact level. A set of N masks is used to etch the contact openings and up to 2 ^N contact levels. Each mask is used to substantially etch half of the contact openings. When N is 3, the first mask etches one contact level, the second mask etches two contact levels, and the third mask etches four contact levels. A dielectric layer may be formed on the sidewalls of the contact openings. Electrical conductors may be formed through the contact openings having the dielectric layers that electrically insulate the electrical conductors from the sidewalls.

Description

MULTILAYER CONNECTION STRUCTURE AND MAKING METHOD}

FIELD OF THE INVENTION The present invention generally relates to high density integrated circuit devices, and more particularly to interconnect structures for multilayer three-dimensional stacked devices.

This application is a priority application of US application Ser. No. 13 / 114,931, filed May 24, 2011, which is incorporated herein by reference.

In the manufacture of high density memory devices, the amount of data per unit area on an integrated circuit can be an important factor. Thus, as critical dimensions of the memory devices approach the limitations of lithography technology, techniques for stacking multiple levels of memory cells have been proposed in order to realize higher storage density and lower cost per bit. come.

For example, "A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory" by Lai et al. (IEEE Int'l Electron Devices Meeting 2006) and "Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking" by Jung et al. Single Crystal Si layers on ILD and TANOS Structure for Beyond 30nm Node "(IEEE Int'l Electron Devices Meeting 2006) apply thin film transistor technologies to charge trapping memory.

In addition, in Johnson et al.'S "512-Mb PROM With a Three-Dimensional Array of Diode / Anti-fuse Memory Cells" (IEEE J. of Solid-State Circuits 2003), cross-point array technologies are used for anti-fuse memory. Has been applied for See also US Pat. No. 7,081,377 to Cleeves, entitled Three-Dimensional Memory.

Another structure for providing vertical NAND cells in charge trapping memory technology is described in Kim et al., "Novel 3-D Structure for Ultra-High Density Flash Memory with VRAT and PIPE" (2008 Symposium on VLSI Technology Digest of Technical Papers). .

In three dimensional stacked memory devices, the conductive interconnects used to connect the lower levels of the memory cells to the decoding circuit and the like pass through the upper level. The cost of implementing the interconnects increases with the number of lithography steps required. One method of reducing the number of lithography steps is described in Tanaka et al. "Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory" (2007 Symposium on VLSI Technology Digest of Technical Papers).

However, one of the disadvantages of conventional three dimensional stacked memory devices is that a separate mask is typically used for each contact level. Thus, for example, if there are 20 contact levels, 20 different masks are commonly required, and each contact level requires the creation of a mask for that level and the etching of that level.

It is an object of the present invention to provide an interconnect structure that can be used to implement memory circuits at various levels.

An example of a method used in a three dimensional stacked integrated circuit device having a stack of at least four contact levels in the interconnect area creates an interconnect contact area that is aligned and exposed to landing areas at the contact levels. To be used. Each contact level includes a conductive layer and an insulating layer. At least a portion of any top layer located above the interconnect area is removed to expose the first contact level and create contact openings for each contact level. A set of N (N is an integer of at least 2) etch masks is selected to produce a plurality of levels of interconnecting contact regions in the stack of contact levels. The N masks are used to etch the contact openings up to 2N contact levels. The use of the N masks comprises etching one contact level for substantially half of the contact openings with a first mask and two contacts for substantially half of the contact openings with a second mask. Etching the level. The removal, selection and use steps are performed such that the contact openings extend to the 2N contact levels. Electrical conductors may be formed to contact the landing regions at the contact levels through the contact openings. In other embodiments, the removing step is performed using an additional mask. In other embodiments, using the first mask includes etching one contact level in all other contact openings using the first mask, wherein using the second mask comprises: the second mask; Etching two contact levels in the third and fourth contact openings in the at least one set of first to fourth contact openings using a mask. In other embodiments, using the N masks comprises etching four contact levels for substantially half of the contact openings using a third mask and substantially using the fourth mask. And etching the eight contact levels for half. In other embodiments, using the third mask may etch four contact levels in fifth to eighth contact openings in at least one set of first to eighth contact openings using the third mask. And using the fourth mask to etch eight contact levels in ninth through sixteenth contact openings in at least one set of first through sixteenth contact openings using the fourth mask. Steps. In other embodiments, ground contact openings are created through the contact levels, and an electrical ground conductor is formed to electrically contact the plurality of conductive layers of the contact levels through the ground contact opening. In other embodiments, the ground contact opening has a ground opening sidewall, and portions of the insulating layers are removed from the ground contact opening sidewall prior to forming the electrical ground conductor so that the electrical ground conductor and the contact level are removed. To improve the electrical contact of the electrical ground conductor between the plurality of conductive layers.

Another example of the method provides electrical connections to landing regions in a stack of contact levels of an interconnect region of a three-dimensional stacked integrated circuit device. The integrated circuit device is of a type that includes an interconnect area. The interconnect area includes a top layer and a stack of contact levels below the top layer. Each contact level includes a conductive layer and an insulating layer. At least a portion of any top layer located above the interconnect area is removed to expose the first contact level and create contact openings for each contact level. A set of N (N is an integer of at least 2) etch masks is selected to produce a plurality of levels of interconnect contact regions in the stacks of contact levels. The N masks are used to etch the contact openings up to 2N contact levels. The use of the N masks comprises etching one contact level for substantially half of the contact openings with a first mask and two contacts for substantially half of the contact openings with a second mask. Etching the level. The removal, selection and use steps are performed to extend the contact openings to the 2N contact levels. Electrical conductors are formed through the contact openings from the contact levels to the landing regions, and the dielectric layers electrically insulate the electrical conductors from the sidewalls. In other embodiments, a ground contact opening is created through the contact levels, and an electrical ground conductor is formed to be in electrical contact with the plurality of conductive layers of the contact levels through the ground contact opening. In other embodiments, the ground contact opening has a ground contact opening sidewall, wherein portions of the insulating layers are removed from the ground contact opening sidewall prior to the electrical ground conductor forming step to adjoin the ground contact opening. As portions of the plurality of conductive layers are exposed, the electrical contact of the electrical ground conductor to the conductive layers is improved.

A first embodiment of a three dimensional stacked integrated circuit device includes a stack of at least first, second, third and fourth contact levels in an interconnect area. Each contact level includes a conductive layer and an insulating layer. First, second, third and fourth electrical conductors pass through portions of the stack of contact levels. The first, second, third and fourth electrical conductors are in electrical contact with the first, second, third and fourth conductive layers, respectively. Sidewall spacers surround the second, third and fourth electrical conductors such that only the second, third and fourth electrical conductors are electrically connected to the second, third and fourth electrical conductor layers, respectively. Contact with. In other embodiments, the first, second, third, and fourth electrical conductors have a constant pitch. In other embodiments, the positions of the first, second, third and fourth electrical conductors can be determined by a common mask. In other embodiments, the stacked integrated circuit device further comprises a ground conductor passing through portions of the stack of contact levels, the ground conductor respectively having first, second, third and fourth conductive layers. Electrical contact with the fields.

A second embodiment of a three dimensional stacked integrated device includes a stack of at least first, second, third and fourth contact levels in an interconnect area. Each contact level includes a conductive layer and an insulating layer. First, second, third and fourth electrical conductors pass through portions of the stack of contact levels. The first, second, third and fourth electrical conductors are in electrical contact with the first, second, third and fourth conductive layers, respectively. The first, second, third and fourth electrical conductors have a constant pitch. In other embodiments, the positions of the first, second, third and fourth electrical conductors can be determined by a common mask.

A third embodiment of a three-dimensional stacked integrated device includes a stack of at least first, second, third and fourth contact levels in an interconnect area. Each contact level includes a conductive layer and an insulating layer. First, second, third and fourth electrical conductors pass through portions of the stack of contact levels. The first, second, third and fourth electrical conductors are in electrical contact with the first, second, third and fourth conductive layers, respectively. A dielectric sidewall spacer surrounds the second, third and fourth electrical conductors such that the second, third and fourth electrical conductors are electrically connected to the second, third and fourth electrical conductive layers, respectively. Contact with. A ground conductor passes through portions of the stack of contact levels and is in electrical contact with the first, second, third and fourth conductive layers, respectively. The first, second, third and fourth electrical conductors have a constant pitch. The positions of the first, second, third and fourth electrical conductors can be determined by a common mask.

Other aspects and advantages of the invention will be more clearly understood with reference to the accompanying drawings, detailed description of the invention and claims.

The technique for implementing the interconnect structure according to the present invention greatly reduces the area or area required to form contacts at a plurality of levels compared to the prior art. As a result, more space at various levels can be used to implement the memory circuits. Thus, higher memory densities and lower cost per bit can be realized compared to the prior art.

1 to 16 are described in U.S. Patent Application No. 12 / 579,192, filed October 12, 2009, of the same applicant as the present application, which is incorporated herein by reference. derived from the Integrated Circuit Layer Interconnect.
1 includes a three-dimensional structure in which the conductors 180 have an interconnect structure 190 having a small footprint that extends to various levels 160-1 through 160-4 in the device. Section of the device.
2A is a plan view of level 160-1 showing landing areas.
2B is a top view of level 160-2 showing openings adjacent to the landing regions.
2C is a top view of level 160-3 showing openings adjacent to the landing regions.
2D is a top view of level 160-4 showing openings adjacent to the landing regions.
3A and 3B are vertical views of a portion of a tertiary stacked integrated circuit device having a three-dimensional interconnect structure, each having a small footprint.
4 is a top view of a layout of an apparatus having interconnect structures on the periphery on two sides of a memory array in accordance with one embodiment.
FIG. 5 is a top view of a layout of a device having interconnect structures around on four sides of a memory array in accordance with one embodiment. FIG.
FIG. 6 is a schematic diagram of a portion of a memory device having an interconnect structure described herein. FIG.
FIG. 7 is a simplified block diagram of an integrated circuit device including a three-dimensional memory array having interconnect structures described herein.
8A-8C through 15 illustrate the steps in the process sequence for manufacturing the interconnect structure described herein.
FIG. 16 is a plan view of an opening in a mask having a varying width along the longitudinal direction in a step-like manner to accommodate varying widths of landing regions on levels.
17 to 34A illustrate a structure and a manufacturing method of a 3D multilayer integrated circuit device according to another exemplary embodiment.
17 and 17A are simplified side cross-sectional views and plan views of interconnect areas of three-dimensional stacked integrated circuit devices according to different embodiments.
18 and 18A illustrate the interconnect area after forming contact openings through the top layer to expose the top conductive layer of the first contact level.
19 and 19A show a first mask on the structure of FIG. 18 exposing all other contact openings.
20 and 20A show the results of etching through a single contact level of exposed contact openings.
21 and 21A show the third and fourth contact openings open while the first and second contact openings are calculated from the left side according to removal of the first mask and formation of a second mask on the structure of FIG. 20. It shows the result covered by.
22 and 22A show the result of the downward etching through the two contact levels of the third and fourth contact openings.
23 and 23A show the structure of FIG. 22 after removal of the second mask of FIG. 22.
24 and 24A show the structure of FIG. 23 after electrically insulating contact levels from the interiors of the contact openings by forming sidewall spacers on the sidewalls of the sidewall openings.
25 and 25A show the structure of FIG. 24 with an additional cross section through the ground contact opening of FIG. 25 covered by photoresist while the ground contact openings are exposed to the left.
26 and 26A show the structure of FIG. 25 after etching through three contact levels to expose a conductive layer of a fourth contact level.
27 and 27A show the structure of FIG. 26 after removing the photoresist.
28 and 28A show that the polysilicon in the contact openings and the ground contact openings respectively form electrical conductors and electrical ground conductors, filling the contact openings and the ground contact openings and covering the top layer; The structure of FIG. 27 after depositing is shown.
29 and 29A show the structure of FIG. 28 after etching the polysilicon covering the top layer.
30 and 30A show the results of downward chemical mechanical polishing from the top surface to the charge trapping layer of the top surface.
31 and 31A show the structure of FIG. 30 after deposition of a stop layer followed by deposition of an interlayer dielectric oxide on the top layer.
32 and 32A are followed by filling with electrical conductors of vias to create electrical conductors and electrical ground conductors having first portions extending through contact levels and second portions extending through an upper layer. 31 shows the structure of FIG. 31 after formation of contact opening extensions to the electrical conductors and electrical ground conductors through the interlayer dielectric oxide and stop layer.
FIG. 33 shows a schematic illustration of a set of sixteen contact openings for four different sets of contact openings etched at four different depths to create the structure of FIG. 17.
34 and 34A are a cross-sectional view and a plan view of a three-dimensional stacked integrated circuit device.
35 shows masking and etching steps in a different manner from FIG. 33.
36 to 38 are views similar to those of FIG. 35, but involving an etching order change, a mask order change, and a position order change, respectively.
FIG. 39 is similar to FIG. 35 but combines the changes of FIGS. 36 to 38.

1 includes a three-dimensional structure in which the conductors 180 have an interconnect structure 190 having a small footprint that extends to various levels 160-1 through 160-4 in the device. Section of the device. In an exemplary embodiment, four levels 160-1 through 160-4 are shown. More generally, the small interconnect structure 190 described herein may be implemented within a structure having levels from zero to N, where N is at least two.

Conductors 180 are aligned in interconnect structure 190 to contact landing areas on various levels 160-1 through 160-4. As will be explained in more detail below, the conductors 180 for each particular level are provided for the landing regions 161-1a, 161-1b, 161-2a, 161-2b, 161-3a, 161-3b. 161-4 extends through the openings in the levels located at the top. In this embodiment, the conductors 180 are interconnect lines 185 in the wiring layer that place contact levels 160-1 through 160-4 above the levels 160-1 through 160-4. It is used to connect to.

The landing regions are portions of contact levels 160-1 through 160-4 used for a contact having conductors 180. The sizes of the landing regions allow conductors to properly connect electrically conductive landing regions within landing regions of various contact levels 160-1 to 160-4 to interconnecting lines 185 located thereon. Not only large enough to provide space for 180, but also approaches problems such as misalignment between conductors 180 and openings located above in one level for landing regions in different levels. Big enough to do.

The size of the landing regions thus depends on many factors, including the size and number of conductors used, and can vary from one embodiment to another. In addition, the number of conductors 180 may vary for each landing region.

In an exemplary embodiment, the levels 160-1 through 160-4 are formed of planar conductive material layers made of a material such as doped polysilicon and the levels 160-1 through 160-4, respectively. It consists of layers 165 of separate insulating materials. Alternatively, the levels 160-1 through 160-4 need not be planarly stacked material layers; instead, the material layers can vary in vertical dimension.

Conductors 180 in contact with other levels 160-1 through 160-4 are aligned in a direction extending along the cross section shown in FIG. 1A. Here, the direction defined by the alignment of the conductors 180 in contact with the other levels 160-1 through 160-4 is defined as a "longitudinal direction". The "transverse direction" is a direction perpendicular to the longitudinal direction and passing through the cross section shown in Figure 1A. Both the longitudinal direction and the transverse direction are "lateral dimensions" and mean the direction within the two-dimensional area of the top view of the levels 160-1-160-4. The “length” of the structures or features is the length in the longitudinal direction and the “width” of the structures or features is the width in the lateral direction.

Level 160-1 is the lowest level among the plurality of levels 160-1 through 160-4. The level 160-1 is located on the insulating layer 164.

The level 160-1 includes first and second landing regions 161-1a and 161-1b in contact with the conductors 180.

In FIG. 1, the level 160-1 includes two landing regions 161-1a and 161-1b located on opposing ends of the interconnect structure 190. In other embodiments, one of the first and second landing regions 161-1a and 161-1b is omitted.

FIG. 2A is a plan view of a portion of level 160-1 including landing areas 161-1a and 161-1b within an occupied area of interconnect structure 190. The footprint of the interconnect structure 190 may be close to the width of the via size for the conductors and may have a length longer than the width. As shown in FIG. 2A, the landing area 161-1a has a width 200 in the transverse direction and a length 201 in the longitudinal direction. Landing region 161-1b has a width 202 in the transverse direction and a length 203 in the longitudinal direction. In the embodiment of FIG. 2A, the landing regions 161-1a and 161-1b have respective rectangular cross sections. In other embodiments, the landing regions 161-1a and 161-1b may each have a circular, elliptical, square, rectangular or somewhat irregular shape.

Since level 160-1 is the lowest level, conductors 180 do not need to pass through levels located below level 160-1. Thus, in this embodiment, the level 160-1 does not have openings in the interconnect structure 190.

Referring back to FIG. 1, the level 160-2 is located above the level 160-1. The level 160-2 includes an opening 250 located above the landing area 161-1a on the level 160-1. The opening 250 has a distal longitudinal side wall and a proximal longitudinal side wall that define a length 252 of the opening 250. The length 252 of the opening 250 is at least greater than the length 201 of the landing region 161-1a located below, so that the conductors 180 for the landing region 161-1a are at the level. May pass through 160-2.

The level 160-2 also includes an opening 255 located above the landing area 161-1b. The opening 255 has distal and proximal longitudinal sidewalls 256a and 256b that define a length 257 of the opening 255. The length 257 of the opening 255 is greater than the length 203 of the landing region 161-1b located at least below, so that the conductors 180 may pass through the opening 250.

The level 160-2 also includes first and second landing regions 161-2a and 161-2b adjacent to the openings 250 and 255, respectively. The first and second landing regions 161-2a and 161-2b are portions of the level 160-2 used to contact the conductors 180.

2B is a top view of a portion of level 160-2 including first and second landing regions 161-1a, 161-1b and openings 250, 255 in interconnect structure 190.

As shown in FIG. 2B, opening 250 has longitudinal sidewalls 251a and 251b defining length 252 and transverse sidewalls 253a and 253b defining width 254 of opening 250. ). The width 254 is greater than the width 200 of the landing region 161-1a located at least below, so that the conductors 180 may pass through the opening 250.

Opening 255 has longitudinal sidewalls 256a and 256b that define length 257 and transverse sidewalls 258a and 258b that define width 259. The width 259 is greater than the width 202 of the landing region 161-1b located at least below, so that the conductors 180 may pass through the opening 255.

In the plan view of FIG. 2B, the openings 250 and 255 each have a rectangular cross section. In embodiments, the openings 250 and 255 may have a circular, elliptical, square, rectangular or somewhat irregular shape depending on the shape of the mask used to form them.

As shown in FIG. 2B, the landing region 161-2a is adjacent to the opening 250 and has a width 204 in the transverse direction and a length 205 in the longitudinal direction. Landing region 161-2b is adjacent to the opening 255, has a width 206 in the transverse direction, and has a length 207 in the longitudinal direction.

Referring back to FIG. 1, level 160-3 is located above level 160-2. The level 160-3 includes a landing area 161-1a on the level 160-1 and an opening 260 located above the landing area 161-2a on the level 160-2. The opening 260 has distal and proximal longitudinal sidewalls 261a and 261b in length of the opening 260. The length 262 of the opening 260 is greater than the sum of the lengths 201 and 205 of the landing regions 161-1a and 161-2a located at least below. Conductors 180 for 161-2a may pass through the level 160-3.

As can be seen in FIG. 1, the distal longitudinal sidewall 261a of the opening 260 is vertically aligned with the distal longitudinal sidewall 251a of the underlying opening 250. In an embodiment of the manufacturing method described in more detail below, the openings are in the single etch mask and the openings in the single etch mask, as well as the processes for the additional mask etching without a critical alignment step. It may be formed using one additional mask formed on the opening. As a result, openings are formed having distal longitudinal sidewalls 261a, 251a, ... along the periphery of a vertically aligned single etch mask.

The level 160-3 also defines an opening 265 located above the landing area 161-1b on the level 160-1 and the landing area 161-2b on the level 160-2. Include. The opening 265 has outer and inner longitudinal sidewalls 266a and 266b that define a length 267 of the opening 265. The outer longitudinal sidewall 266a of the opening 265 is aligned perpendicular to the outer longitudinal sidewall 256a of the opening 255 located thereon.

The length 267 of the opening 265 is at least greater than the sum of the lengths 203, 207 of the landing regions 161-1b and 161-2b located at the bottom, and thus the landing regions 161-1b and 161. Conductors 180 for −2b) may pass through level 160-3.

The level 160-3 also includes first and second landing regions 161-3a and 161-3b which are adjacent to the openings 260 and 265, respectively. The first and second landing regions 161-3a and 161-3b are portions of the level 160-3 used to contact the conductors 180.

FIG. 2C is a top view of a portion of level 160-3 including first and second landing regions 161-3a, 161-3b and openings 260, 265 in interconnect structure 190.

As shown in FIG. 2C, the opening 260 defines the outer and inner longitudinal sidewalls 261a, 261b and the widths 264a, 264b of the opening 260 that define the length 262 of the opening 260. Defining transverse sidewalls 263a and 263b. The width 264a is at least greater than the width 200 of the landing region 161-1a located below, so that the conductors 180 may pass through the opening 260.

In exemplary embodiments, the widths 264a and 264b are substantially the same. Alternatively, the widths 264a and 264b may be different to accommodate landing areas having different widths.

Opening 265 has longitudinal sidewalls 266a and 266b defining length 267 and transverse sidewalls 268a and 268b defining widths 269a and 269b. The width 269a is at least greater than the width 202 of the landing region 161-1b located below, and the width 269b is at least greater than the width 206 of the landing region 161-2b located below. As a result, the conductors 180 may pass through the opening 265.

As shown in FIG. 2C, the landing region 161-3a is adjacent to the opening 260 and has a width 214 in the transverse direction and a length 215 in the longitudinal direction. Landing regions 161-3b adjoin the opening 265 and have a width 216 in the transverse direction and a length 217 in the longitudinal direction.

Referring back to FIG. 1, level 160-4 is located above level 160-3. Level 160-4 is a landing area 161-1a on the level 160-1, a landing area 161-2a on the level 160-2, and a landing area on the level 160-3. 161-3a) includes an opening 270 located above. The opening 270 has longitudinal sidewalls 271a and 271b that define a length 272 of the opening 270. The length 272 of the opening 270 is greater than the sum of the lengths 201, 206, and 215 of the landing regions 161-1a, 161-2a, and 161-3a located at least below the landing region. Conductors 180 for the fields 161-1a, 161-2a, and 161-3a may pass through the level 160-4. As shown in FIG. 1, the longitudinal sidewall 271a of the opening 270 is aligned perpendicular to the longitudinal sidewall 261a of the underlying opening 260.

The level 160-4 may also include a landing area 161-1b on the level 160-1, a landing area 161-2b on the level 160-2, and a level on the level 160-3. An opening 275 positioned above the landing region 161-3b. The opening 275 has longitudinal sidewalls 276a and 276b that define a length 277 of the opening 275. The longitudinal sidewall 276a of the opening 275 is aligned perpendicular to the longitudinal sidewall 266a of the underlying opening 265.

The length 277 of the opening 275 is greater than the sum of the lengths 203, 207, and 217 of the landing regions 161-1b, 161-2b, and 161-3b at least beneath the landing region. The conductors 180 for the fields 161-1b, 161-2b, and 161-3b may pass through the level 160-4.

The level 160-4 also includes a landing area 161-4 between the openings 270, 275. The landing region 161-4 is part of the level 160-4 used to contact the conductors 180. In FIG. 1, the level 160-4 has one landing area 161-4. Alternatively, the level 160-4 may include one or more landing areas.

2D is a top view of a portion of level 160-4 including landing area 161-4 and openings 270, 275 in interconnect structure 190.

As shown in FIG. 2D, opening 270 has longitudinal sidewalls 271a and 271b defining length 272 and transverse sidewalls defining width 274a, 274b and 274c of opening 250. (273a, 273b) is provided. The widths 274a, 274b, and 274c are larger than the widths 200, 204, and 214 of the landing regions 161-1a, 161-2a, and 161-3a located at least below, so that the conductors 180 are formed. It may pass through the opening 270.

The opening 275 has longitudinal sidewalls 278a and 278b defining a length 277 and transverse sidewalls 273a and 273b defining a width 279a, 279b and 279c of the opening 250. do. The widths 279a, 279b, and 279c are larger than the widths 202, 206, and 216 of the landing regions 161-1b, 161-2b, and 161-3b located at least below, so that the conductors 180 are formed. It may pass through the opening 275.

As shown in FIG. 2D, the landing area 161-4 is located between the openings 270, 275 and has a width 224 in the transverse direction and a length 225 in the longitudinal direction.

Referring again to FIG. 1, the distal longitudinal sidewalls 271a, 261a, 251a of the openings 270, 260, 250 are vertically aligned, so that the lengths of the openings 270, 260, 250 are vertically aligned. The difference in is due to the horizontal offset of the sidewalls 271b, 261b, 251b.

In this specification, "vertically aligned" elements or features are located in a plane substantially the same height as the imaginary plane perpendicular to both the transverse and longitudinal directions. The term “substantially flush” herein refers to manufacturing tolerances in forming the openings using the openings in a plurality of etching processes causing a change in the plane of the sidewalls and the single etch mask. It is intended to be accepted.

As shown in FIG. 1, the longitudinal sidewalls 276a, 266a, 256a of the openings 275, 265, 255 are vertically aligned.

Similarly, the lateral sidewalls of the openings at the levels are also vertically aligned. 2A-2D, the lateral sidewalls 273a, 263a, 253a of the openings 270, 260, 250 are vertically aligned. The lateral sidewalls 273b, 263b and 253b are also vertically aligned. For the openings 275, 265, 255, the longitudinal sidewalls 276a, 266a, 256a are vertically aligned, and the lateral sidewalls 278b, 268b, 258b are also vertically aligned.

In an exemplary embodiment, the openings in the various levels 160-1 through 160-4 have substantially the same width along the transverse direction. Alternatively, the width of the openings can be varied along the longitudinal direction, for example in a stepwise manner, to accommodate landing areas having different widths.

As described herein, the technique for implementing the interconnect structure 190 greatly reduces the area or footprint required to form contacts at a plurality of levels 160-1 through 160-4 compared to the prior art. . As a result, more space at the various levels 160-1 through 160-4 can be used to implement the memory circuits. This enables higher memory density and lower price per bit at the top levels compared to the prior art.

In the cross-sectional view of FIG. 1, the openings in the interconnect structure 190 allow for forming the levels having a stepped pattern on both sides of the landing area 161-4 on the level 160-4. do. That is, the two openings in each level are symmetric about an axis perpendicular to both the longitudinal and transverse directions, and the two landing regions of each level are also symmetric about that axis. The term "symmetrical" as used herein is intended to accommodate manufacturing tolerances in forming the openings using the opening in a single etching mask and in a plurality of etching processes causing a change in the dimensions of the openings. Used as

According to other embodiments, where each level comprises a single opening and a single landing area, the levels have a stepped pattern on only one side.

In an exemplary embodiment, four levels 161-1 through 160-4 are shown. More typically, small interconnect structures in this specification may be implemented at levels from 0 to N, where N is at least 2. Generally, level i ((i) equals one of 1 to N values) is located on level i-1 and is adjacent to landing area i on level i. It is provided. The opening i extends over the landing area i-1 on the level i-1 and, if (i) is greater than 1, the opening i-1 adjacent to the level i-1. ) Is extended. The opening i has a distal longitudinal sidewall aligned at the level i with respect to the distal longitudinal sidewall of the opening i-1 and a proximal longitudinal sidewall defining the length of the opening i. do. The length of the opening i is, if necessary, greater than at least the length of the landing area i-1 plus the length of the opening i-1. If (i) is greater than 1, the opening (i) has transverse sidewalls aligned with the transverse sidewalls of the opening (i-1) of the level (i-1), and at least the landing area (i−). It has a width of the opening i larger than the width of 1).

Other forms of memory cells and configurations may be used in other embodiments. Examples of such other forms of memory cells that can be used include dielectric charge trapping and floating gate memory cells. For example, optional levels of the device are separated by an insulating material and implemented as planar memory cell arrays with the access devices and access lines formed within the levels using thin film transistors or related techniques. Can be. In addition, it may be implemented in other forms of three-dimensional stacked integrated circuit devices useful herein to have conductors in a small footprint that extend to various levels within the device.

3A is a cross-sectional view of a portion of a three-dimensional stacked integrated circuit device 100 including a memory array region 110 and a peripheral region 120 in an interconnect structure 190, as described herein.

In FIG. 3A, memory array region 110 is implemented with one-time programmable multi-level memory cells described in US patent application Ser. No. 12 / 430,290, filed by Lung. Is the property of the assignee of the present application and is incorporated herein by reference. Three-dimensional (3D) interconnect structures that can be implemented herein are described as representative integrated circuit structures.

The memory array region 110 includes memory including horizontal field effect transistor access devices 131a and 131b including source regions 132a and 132b and drain regions 134a and 134b in the semiconductor substrate 130. An access layer 112 is provided. Substrate 130 includes bulk silicon or other structures known as techniques for supporting silicon layers or integrated circuits on insulating layers. Trench isolation structures 135a and 136b separate regions within the substrate 130. Word lines 140a and 140b serve as gates of access devices 131a and 131b. The contact plugs 142a and 142b extend through the interlayer insulating layer 144 to connect the drain regions 134a and 134b to the bit lines 150a and 150b.

The contact pads 152a and 152b are connected to the contacts 146a and 146b disposed below and are connected to the source regions 132a and 132b of the access transistors. The contact pads 152a and 152b and the bit lines 150a and 150b are located in the interlayer insulating layer 154.

In an exemplary embodiment, the levels consist of layers of respective planar conductive materials, such as doped polysilicon. Alternatively, the levels need not be planarly stacked layers of material, but instead the layers of material may vary in their vertical dimensions.

Insulating layers 165-1 through 165-3 separate the levels 160-1 through 160-4 from the other. The insulating layer 166 is disposed on the levels 160-1 to 160-4 and the insulating layers 165-1 to 165-3.

The plurality of electrode pillars 171a and 171b are aligned with the top of the memory cell access layer 112 and extend through the levels. In the figure, the first electrode pillar 171a comprises a central conductive core 170a made of, for example, tungsten or another suitable electrode material and surrounded by a polysilicon sheath 172a. A layer 174a of anti-fuse material or other programmable memory material is formed between the polysilicon coating 172a and the plurality of levels 160-1 through 160-4. In this embodiment, the levels 160-1 through 160-4 include relatively high concentrations of doped n-type polysilicon, while polysilicon coating 172a includes relatively low concentrations of doped p-type polysilicon. do. Preferably, the thickness of the polysilicon coating 172a is greater than the depth of the depletion region formed by the p-n junction. The depth of the depletion region is determined in part by the relative doping concentration of the n-type or p-type polysilicon used to form the depletion region. The levels 160-1 through 160-4 and the cladding 172a may also be implemented using amorphous silicon. In addition, other semiconductor materials may be utilized.

The first electrode pillar 171a is connected to the pad 152a. A second electrode pillar 171b comprising a conductive core 170b, a polysilicon coating 172b and an anti-fuse material layer 174b is connected to the pad 152b.

As will be described in more detail below, the memory elements comprising series-connected programmable elements having rectifiers have interface regions between the plurality of levels 160-1 through 160-4 and the pillars 171a, 171b. Equipped with.

In its natural state, layer 174a of anti-fuse material of pillar 171a may be silicon dioxide, silicon oxynitride or other silicon oxide, and has a high resistance. Other anti-fuse materials can also be used, such as silicon nitride. After programming by applying a suitable voltage to the word lines 140, bit lines 150 and the plurality of levels 160-1 through 160-4, the layer 174a of anti-fuse material is insulated and destroyed. The active region in the anti-fuse material adjacent to the corresponding level has a low resistance state.

As shown in FIG. 3A, the plurality of conductive layers of the levels 160-1 through 160-4 extend into the peripheral region 120, and the support circuit and the conductors 180 in the peripheral region 120. These are generated at the plurality of levels 160-1 to 160-4. Various devices are implemented in the peripheral region 120 on the integrated circuit 100 to support the decoding logic and other circuits.

The conductors 180 are aligned within the interconnect structure 180 to contact the landing regions on the various levels 160-1 through 160-4. As will be described in more detail below, the conductors 180 for each level 160-1 through 160-4 include conductive interconnect lines 185 through openings in the upper levels. It extends to the wiring layer. The conductive interconnect lines 185 are provided to decode the interconnections between the levels 160-1 through 160-4 and the circuitry in the peripheral region 120.

As indicated by the dotted lines in FIG. 3A, the conductors 180 in contact with the other levels 160-1 through 160-4 are arranged longitudinally and extend inward and outward of the cross section shown in FIG. 3A.

FIG. 3B is a cross-sectional view taken along the lines of FIGS. 3B-3B through the interconnect structure 190 of FIG. 3A in the longitudinal direction, showing the interconnect structure 190 as shown in FIG. 1. As can be seen in FIG. 3B, the conductors 180 for each particular level extend through the openings in the upper levels, making contact with the landing regions.

In an exemplary embodiment, four levels 160-1 through 160-4 are shown. More generally, the small interconnect structure 190 herein may be implemented within a structure having levels from zero to N, where N is at least two.

Other forms of memory cells and configurations may be used in other embodiments. For example, optional levels of the device are separated by insulating material and may be implemented as planar memory cell arrays with the access devices and access lines formed within the levels using thin film transistors or related technologies. Can be. In addition, other forms of three-dimensional stacked integrated circuit devices with conductors extending to various levels within the device may be implemented herein. In addition, the interconnect structure herein can be implemented in other forms of three-dimensional stacked integrated circuits where it is useful to have conductors that extend to various levels in the device within a small footprint.

3A and 3B show a single interconnect structure 190. The plurality of interconnect structures may be aligned at various locations within the device, such as enclosed memory array area 110, resulting in better power dissipation. 4 shows a layout of an embodiment of an apparatus 100 comprising two series of interconnect structures including a series in regions 190-1 and 190-2 in a peripheral region 120 on respective sides of the array. Top view of the is shown. 5 illustrates an embodiment comprising four series of interconnect structures including series 190-1, 190-2, 190-3, and 190-4 in the peripheral region 120 on four sides of the array. A top view of the layout is shown. For example, an array size with as many as 1,000 columns and as many as 1,000 rows, and with a minimum wiring width that defines a word line width and a bit line width, having an array size of about 10 levels ( If the size of the landing regions in F) and the levels is about F, the length of the region occupied by one interconnection structure is about 2F times the number of levels or about 20F, and the pitch per word line Is about 2F or more, which makes the array about 2000F wide. Thus, according to exemplary embodiments, about 100 interconnect structures may be formed in series, such as series 190-3 along the array width, with a similar number of series along the array length. And may be formed in series such as the device 190-1.

In still other embodiments, one or more interconnect structures may be implemented in memory array region 110 in addition to or in place of having interconnect structures in periphery 120. In addition, the interconnect structures may extend diagonally or in a different direction than parallel to the edge of the memory array region 110.

6 is a schematic diagram of a memory device including an interconnect structure, as described herein. The first electrode pillar 171a is connected to the selected access transistor 131a using the bit line 150a and the word line 140a. The plurality of memory elements 544-1 through 544-4 are connected to the pillar 171a. Each memory element includes a programmable element 548 connected in series with a rectifier 549. Although the anti-fuse material layer is located at the p-n junction, the alignment of these series shows the structure shown in FIGS. 3A and 3B. Programmable element 548 is often indicated by a symbol used to indicate anti-fuses. However, other types of programmable resistance materials and structures can be utilized.

In addition, the rectifier 549 implemented by the p-n junction between the polysilicon in the electrode pillar and the conductive plane can be replaced by other rectifiers. For example, a rectifier based on a solid electrolyte or other suitable material, such as germanium silicide, may be used to provide the rectifier. For other exemplary solid electrolyte materials, US Pat. No. 7,382,647 is described by reference.

Each memory element 544-1 through 544-4 is connected to corresponding levels of conductivity 160-1 through 160-4. The levels 160-1 through 160-4 are connected to the plane decoder 546 through the conductors 180 and the interconnect lines 185. The plane decoder 546 applies a voltage, such as ground 547, to a selected level in response to addresses such that the rectifier within the memory element is forward biased and conductive, applying a voltage to unselected layers. Or float, the rectifier in the memory element is biased backwards or is non-conductive.

7 is a simplified block diagram of an integrated circuit device 300 including a three-dimensional memory array 360 having the interconnect structure described herein. The row decoder 361 is connected to the plurality of word lines 140 aligned along the rows in the memory array 260. A column decoder 363 for reading and erasing data from the memory cells in the array 360 is connected to a plurality of bit lines 150 arranged along the columns in the memory array 360. The planar decoder 546 is connected to the plurality of levels 160-1 through 160-4 in the memory array 360 through the conductors 180 and the interconnect lines 185. Addresses are provided on the bus 365 to the column decoder 363, the row decoder 361 and the plane decoder 546. Sense amplifiers and data-in structures in block 366 are coupled to column decoder 363, for example, via data bus 367. Data is provided to data-in structures in block 366 from input / output ports on integrated circuit 300 via data-in line 371. In an exemplary embodiment, other circuitry 374 is included on integrated circuit 300, such as a general purpose processor or dedicated application circuitry, or a combination of modules providing system-on-chip functionality. . Data is input / output ports on integrated circuit 300 or other internal or external data destinations or integrated circuit 300 from sense amplifiers in block 366 via data-out line 372. Is provided.

In such an embodiment, an implemented controller using a bias arrangement state machine 369 is generated or provided through the voltage supply or supplies in block 368, such as read and program voltages. Control the application of bias alignment supply voltages. The controller may be implemented using dedicated logic circuits known in the art. In other embodiments, the controller includes a general purpose processor that can be implemented on the same integrated circuit executing a computer program to control the operation of the device. In still other embodiments, a combination of dedicated logic and general purpose processors may be utilized for the implementation of the controller.

8A-8C through 15 illustrate the steps in an embodiment of a manufacturing process for producing an interconnect structure having the aforementioned very small footprint.

8A and 8C are cross-sectional views of the first stage of the manufacturing process, and FIG. 8B is a top view of the first stage of the manufacturing process. For the purposes of the present invention, the first step includes forming a plurality of levels 160-1 through 160-4 located above the provided memory cell access layer 112. In an exemplary embodiment, the structure shown in FIGS. 8A-8C is formed using the processes described in US patent application Ser. No. 12 / 430,290, filed by Lung, previously incorporated by reference.

In other embodiments, the levels may be formed by standard processes known in the art, and access devices such as transistors and diodes in a substrate in accordance with the device in which the interconnect structure described herein is implemented. , Word lines, bit lines, source lines, conductive plugs and doped regions.

As mentioned above, other types of memory cells and configurations for the memory array region 110 may also be used in other embodiments.

Next, a first mask 800 having openings 810 is formed on the structure shown in FIGS. 8A-8C to derive the structure shown in the top and cross-sectional views of FIGS. 9A and 9B, respectively. . The first mask 800 may be formed by depositing a layer for the first mask 800 and patterning the layer using lithographic techniques to form openings 810. The first mask 800 may include a hard mask material such as, for example, silicon nitride, silicon oxide, or silicon oxynitride.

An opening 810 of the first mask 800 surrounds a combination of landing regions on the levels 160-1 through 160-4. Thus, the width 192 of the opening 810 is at least greater than the widths of the landing regions on the levels 160-1 through 160-4 so that subsequently formed conductors 180 are in the levels. May pass through the openings. The length 194 of the opening 810 is at least greater than the sum of the lengths of the landing regions on the levels 160-1 through 160-4 so that subsequently formed conductors 180 are formed within the levels. May pass through the openings.

Next, a second etch mask 900 is formed on the structure shown in FIGS. 9A-9C and includes an opening 810, which is shown in the top and cross-sectional views of FIGS. 10A and 10B, respectively. As shown in the figures, the second etching mask 900 has a length 910 that is less than the length 194 of the opening 810 and has a width that is at least greater than the width 192 of the opening 810. .

In some example embodiments, the second etching mask 900 may include a material that is selectively etchable with respect to the material of the first mask 800, so that the second mask 900 in the opening 810 may be formed. The length can optionally be reduced in subsequent process steps described below. In other words, the material of the second mask 900 has an etch ratio greater than the etch rate of the material of the first mask 800 for the process used to reduce the length of the second mask 900. For example, in embodiments where the first mask 800 comprises a hard mask material, the second mask comprises a photoresist.

Next, an etching process is performed on the structure shown in FIGS. 10A to 10B using the first and second masks 800 and 900 as etching masks, so that the top and cross-sectional views of FIGS. 11A and 11B are performed. Each illustrated structure is brought about. The etching process may be performed through a single etching chemical reaction using, for example, timing mode etching. Alternatively, the etching process may be performed using other etching chemicals that are separately etched through the insulating layer 166, the level 160-4, the insulating material 165-3, and the level 160-3. have.

The etching process forms an opening 1000 through the level 160-4, exposing a portion of the level 160-3. The opening 1000 is located above the landing area 161-1a on the level 160-1. The opening 1000 has a length 1002 that is at least greater than the length of the landing area 161-1a and has a width 1004 that is at least greater than the width of the landing area 161-1a.

The etching process also forms an opening 1010 through the level 160-4, exposing a portion of the level 160-3. The opening 1010 is located above the landing area 161-1b on the level 160-1. The opening 1010 has a length 1012 that is at least greater than the length of the landing area 161-1b and has a width 1004 that is at least greater than the width of the landing area 161-1b.

Next, the length 910 of the mask 900 is reduced to form a reduced length mask 1100 having a length 1110, the structure shown in the top and cross-sectional views of FIGS. 12A and 12B, respectively. Is caused. In an exemplary embodiment, the mask 900 includes a photoresist and may be cut using reactive ion etching of chemicals based on, for example, chlorine (Cl ₂ ) or hydrogen bromide (HBr).

Next, an etching process using the first mask 800 and the reduced length mask 1100 as the etching masks is performed on the structure shown in FIGS. 12A to 12B, and the top view of FIGS. 13A and 13B. And structures respectively shown in the cross-sectional view.

The etching process extends the openings 1000 and 1010 through the level 160-3 to expose portions of the level 160-2 located below.

The etching process also forms openings 1200, 1210 through portions of level 160-4 that are no longer covered by mask 1100 due to a decrease in length of mask 1100, thereby reducing the level ( Expose part of 160-3). The opening 1200 is formed at a position adjacent to the opening 1000 and is positioned above the landing area 161-2a on the level 160-2. The opening 1200 has a length 1202 that is at least greater than the length of the landing area 161-2a and has a width 1204 that is at least greater than the width of the landing area 161-2a.

The opening 1210 is formed at a position adjacent to the opening 1010 and is located above the landing area 161-2b on the level 160-2. The opening 1210 has a length 1212 at least greater than the length of the landing region 161-2b and has a width 1204 at least greater than the width of the landing region 161-2b.

Next, the length 1110 of the mask 1100 is reduced to form a mask 1300 of reduced length having a length 1305. An etching process using the first mask 800 and the mask 1300 as etching masks is performed to derive the structures shown in the top and cross-sectional views of FIGS. 14A and 14B, respectively.

The etching process extends the openings 1000 and 1010 through the level 160-2 to expose the landing regions 161-1a and 161-1b on the level 160-1. The etching process also extends openings 1200 and 1210 through level 160-3, exposing landing regions 161-2a and 161-2b on level 160-2.

The etching process also forms openings 1310 and 1320 through portions of the level 160-4 that are no longer covered due to the reduction in the length of the mask 1300, thereby overlying the level 160-3. Landing regions 161-3a and 161-3b are exposed.

The opening 1310 is formed at a position adjacent to the opening 1200. The opening 1310 has a length 1312 that is at least greater than the length of the landing region 161-3a and has a width 1314 that is at least greater than the width of the landing region 161-3a.

The opening 1320 is formed at a position adjacent to the opening 1210. The opening 1320 has a length 1322 at least greater than the length of the landing region 161-3b and has a width 1324 greater than the width of the landing region 161-3b.

Next, an insulating fill material 1400 is deposited on the structure shown in FIGS. 14A-14B, and a planarization process such as chemical mechanical polishing (CMP) is performed to remove the masks 800, 1300. The structure shown in the cross section of 15 is derived.

Next, a lithographic pattern is formed to define vias in the landing regions for the conductors 180. Reactive ion etching is used to form deep, high aspect ratio vias through the insulating fill material 1400 to provide vias for the conductors 180. After the vias are open, the vias are filled with tungsten or other conductive material to form the conductors 180. Wiring processes are then applied to form interconnect lines 185 and provide interconnection between the conductors 180 and planar decoding circuitry on the device. Finally, back end of line processes are applied to complete the integrated circuit, resulting in the structure shown in FIGS. 3A-3B.

The openings in the various levels used for pass-through conductors in the landing regions on the underlying levels are defined by the openings 810 in the single etch mask 800 as well as the processes of etching additional masks without a critical alignment step. It is formed by patterning the levels using. As a result, the openings in the various levels with vertically aligned sidewalls are formed in a self-aligned manner.

In the above-described exemplary embodiments, the opening 810 in the mask 800 has a rectangular cross section in plan view. As a result, the openings in the various levels have substantially the same width along the transverse direction. Alternatively, the opening in the mask 800 may have a circular, elliptical, square, rectangular or somewhat irregular shape depending on the shape of the landing areas of the various levels.

For example, the width of the opening in the mask 800 can be changed along the longitudinal direction to accommodate landing areas having different widths. 16 is a plan view of an opening 1510 in a mask 800 having a width that varies in the longitudinal direction in the same manner as a staircase, which causes the widths of the openings in the varying levels.

The present invention will be mainly described with reference to Figs. 17 to 34A.

The following description is typical to reference specific structural embodiments and methods. It is to be understood that the specifically disclosed embodiments and methods are not intended to limit the invention and that the invention can be implemented using other features, elements, methods and embodiments. The preferred embodiments described to illustrate the invention by way of example do not limit the scope of the invention as defined by the claims. Those skilled in the art will understand various changes equivalent to those described below. In various embodiments the same elements are commonly referred to by the same reference numerals.

17-34A show a method of manufacturing another example of a three-dimensional stacked integrated circuit (IC) device having the above structure and the same reference numerals in the same structure. 17 and 17A are simplified side cross-sectional and top views of interconnection regions 17 of embodiments of three-dimensional stacked integrated circuit devices. In this embodiment, interconnect area 17 includes four interconnect levels 18, denoted 18.1 to 18.4, four electrical conductors 54 and electrical ground conductor 55, denoted 54.1 to 54.4. It includes. Electrical conductors 54 have first portions 57 passing through contact levels 18, second portions 59 passing through interlayer insulating layer 52, and charge trapping layer 27. Thereby electrically connecting one of the interconnected contact regions 14 of the contact levels 18, denoted 14.1 to 14.4, one of the conductive layers 34, and the layers 34.1 to 34.4, denoted 34.1 to 34.4. . The first portions 57 are surrounded by a dielectric sidewall spacer 61 to electrically separate the electrical conductors 54 from the conductive layers 34 so that the electrical conductors 55 are in electrical contact. Does not form. Also shown is an electrical ground conductor 55 electrically connected to each conductive layer 34 of each contact level 18.

18 and 18a show an initial stage of manufacture of the interconnection region 17. The photoresist 88 is used to etch through the top layer 24 the contact openings 33 and ground contact openings 35, denoted 33.1 to 33.4, and the ground contact openings 35 shown in FIG. 18A. The upper conductive layer 34.1 of the first contact layer 18.1 is exposed. Subsequent contact openings 33, etching of the photoresist 88 are omitted, and the first photoresist mask 89 is formed on the interconnection region 17 as shown in FIGS. 19 and 19A. In this embodiment, the first mask 89 exposes all other contact openings 33, 33.2 to 33.4. As can be seen in FIG. 19A, the mask 89 also covers the ground contact opening 36. As can be seen by comparing FIGS. 17 and 18, the position of the contact openings 33 determines the positions of the electrical conductors 54, and the ground contact openings 35 represent the ground electrical conductors ( 55 locations are determined. In this embodiment, the electrical conductors 54 and thus interconnecting contact regions have a constant pitch.

20 and 20A show the results of etching through a single contact level 18.1 under exposed contact openings 33.2 and 33.4. The first mask 89 is then removed following formation of the second photoresist mask 90 shown in FIGS. 21 and 21A. The second mask 90 is used to expose the contact openings 33.3 and 33.4, while covering the contact openings 33. 1, 33.2 and the ground contact openings 35. FIG. 21 shows the result of the removal of the first mask 89 and the formation of the second mask 90 on the structure of FIG. 20, the first and second contact openings 33. 1, 33. While covered by the second mask, the third and fourth contact openings 33.3 and 33.4 are open.

22 and 22A show the result of the downward etching through the two contact levels 18 of the third and fourth contact openings 33.3 and 33.4. That is, contact levels 18.1 and 18.2 are etched through contact opening 33.3, while contact levels 18.2 and 18.3 are etched through contact opening 33.4. 23 and 23A show the structure of FIG. 22 after removal of the second mask 90 of FIG. 22. It can be seen that the contact openings 33. 1 to 33.4 extend downward to the conductive layers 34.1 to 34.4 of the contact levels 18. 1 to 18.4.

24 and 24 show the structure of FIG. 23 after formation of sidewall spacers 61 on the sidewalls of sidewall openings 33.1 to 33.4. Sidewall spacers 61 electrically insulate contact openings 33.2, 33.3, 33.4 from the conductive layers 34 of contact levels 18 through areas through which contact openings pass.

25 and 25A show the structure of FIG. 24 with the addition of a cross section through the ground contact opening 35 in FIG. 25. All contact openings 33 are covered by photoresist 92, while ground contact openings 35 remain exposed. 26 and 26A are etched through three contact levels 18 in ground contact openings 35 to expose conductive layers 34.1 to 34.4 inside the ground contact openings 35. The structure of the 27 and 27A show the structure of FIG. 26 after removing the photoresist 92.

28 and 28A typically show the structure of FIG. 27 after depositing a conductive material 93 such as polysilicon and filling the contact openings 33. The material 93 in the contact openings 33 and ground contact openings 35 respectively form electrical conductors 54 and electrical ground conductors 55. If desired, portions of the insulating layers 36 at the ground contact opening sidewalls are removed prior to back etching or otherwise forming an electrical ground conductor 55 in the ground contact opening 35, thereby removing the electrical ground conductor. Increase electrical contact between 55 and conductive layers 34 of contact levels 18. This point is indicated in FIG. 59 by dashed lines in the insulating layers 36 surrounding the electrical ground conductor 55.

Conductive material 93 also covers dielectric layer 26 of top layer 24. The structure of FIG. 28 is then etched to remove the layer of material 93 covering the dielectric layer 26. This point is illustrated in FIGS. 29 and 29A. In the structure of FIG. 29, the structure of FIG. 30 is derived, for example, by down chemical mechanical polishing (CMP) of the charge trapping layer 27.

31 and 31A show the structure of FIG. 30 following the deposition of an interlayer insulating layer 97 on the stop layer 96, followed by deposition of a stationary layer 96, typically silicon nitride. Next, the structure of FIG. 31 is a ground formed through the interlayer insulating layer 97 and the extensions of the contact openings 33 in the electrical conductors 54 and the electrical ground conductors 55 shown in 54.1 to 54.4. Contact openings 35, stop layer 96, and the like. As shown in Figures 32 and 32A, this fills the extensions with a conductive material such as tungsten, which in turn creates electrical conductors 54 and ground electrical conductors 55. Electrical conductors 54 have first portions 57 extending through contact levels 18 and second portions 59 extending through top layer 24.

In other embodiments, layer 96 is silicon nitride, while interlayer insulating layer 97 is silicon dioxide. However, layer 96 may be other dielectric material, such as layers of alternately stacked silicon dioxide or silicon oxide and silicon nitride. Sidewall spacers 30 may be silicon nitride, but may also be other materials, such as silicon dioxide or an oxide / silicon nitride multilayer. Similarly, dielectric layer 25 is generally silicon nitride, but may also be silicon dioxide, for example. The first portion 57 of the electrical conductor 54 is generally polysilicon, but may be other conductive materials such as n + polysilicon, tungsten, titanium nitride (TiN), and the like. In addition, the overall length of the electrical conductor 54 may be the same material, such as tungsten.

33 shows sixteen contact openings showing four different sets of contact openings 33 etched at sixteen different depths to provide access to sixteen contact levels 18 using only four masks. An example of a set is shown.

34 and 34A are a cross-sectional view and a plan view of a three-dimensional stacked integrated circuit device. FIG. 34 is taken through word line 94, which is electrically isolated from stacks of semiconductor layers, for example by alternating dielectric layers and layer 95. FIG. Layer 95 may be, for example, layers of alternating layers of silicon oxide and silicon nitride that function as charge trapping layers.

The embodiment described below describes a method for providing electrical connections to landing regions 56 in a stack of contact regions 18 of interconnect regions 17 for a three-dimensional stacked integrated circuit device. In this embodiment, interconnect area 17 includes a top layer 24 having a stack of contact levels 18 below the top layer, a respective contact level comprising conductive layer 34, insulating layer 36. It includes. A portion of any top layer 24 located at least over the interconnect area 17 is removed to expose the first contact level 18.1 and create a contact opening 33 for each contact level 18. do. This point is illustrated in FIG. 18.

A set of N etch masks is used to create up to 2N levels of interconnect contact regions 14 in the stack of contact levels 18. Although most of the figures show embodiments with four contact levels 18, the number of contact levels can be increased to 16 contact levels when n = 4 in these embodiments. 33, which includes a schematic illustration of sixteen contact openings 33, may also be mentioned in this description. The masks are used in this embodiment to etch contact openings 33 comprising up to 2N contact levels, up to 16 contact levels. The steps are performed as described below.

The first mask 89 shown in FIG. 19 is used to etch one contact level 18 in all other contact openings. The contact openings not covered by the first mask 89 are indicated by eight dashed line boxes surrounding the contact openings 33.2, 33.4, etc. in FIG. 33. Next, the second mask 90 shown in FIG. 21 is used to etch two contact levels in the third and fourth contact openings in the series of first to fourth contact openings. In FIG. 33, the second mask 90 is represented by each dashed box that surrounds two adjacent contact openings 33 out of the four contact openings. In this embodiment, the etched third and fourth contact openings are the contact openings (33.5 to 33.8, etc.) for the contact opening for the set of first contact openings 33.1 through the fourth contact openings 33.4. 33.3, 33.4, and contact openings 33.7, 33.8 for a set of contact openings 33.5-33.8, and the like. As can be seen in FIG. 22, the use of the first and second masks 89, 90 provides a downward contact opening 33 at each of the four contact levels 18. 1-18.4.

This embodiment with sixteen contact levels 18, a third mask (not shown), has four contacts in the fifth through eighth contact openings 33 in a series of sets of first through eighth contact openings. Continued use to etch levels. This point is represented by two long dashed lines in FIG. 33. A fourth mask (not shown) is used to etch eight contact levels in ninth through sixteenth contact openings in at least one set of first through sixteenth contact openings. This point is represented by one solid line box in FIG. 33. Note that half of the contact openings described above are etched using the first, second, third, and fourth masks.

The dielectric layer 61 shown in FIG. 24 is formed on each sidewall of the contact openings 33. Thereafter, electrical conductors 54 are formed to pass through the contact openings 33 to the interconnect regions 14 of the contact levels 18, the dielectric layers being the electrical conductors 54. Is electrically insulated from the conductive layers 34 along the sidewalls.

As described above with reference to FIGS. 18 and 19, the ground contact opening 35 is typically formed in the same manner as the contact openings 33. However, prior to forming the electrical conductors 54 in the contact openings 33, the portions of the ground contact openings 35 in the top layer 24 are aligned with the sidewall spacers and then shown in FIG. 26. It is etched through one of the contact levels 18 and filled with a conductive material to create an electrical ground conductor 55 as shown in FIG. The electrical ground conductor 55 is in electrical contact with each conductive layer 34. On the other hand, electrical conductors 54.1 to 54.4 are in contact only with a single conductive layer 34 due to the use of dielectric sidewall spacers 61. In other examples, each electrical ground conductor 55 may not form an electrical contact with each conductive layer 34.

In the above-described embodiments, the contact openings 33 can count from left to right. If desired, the contact openings can be counted from left to right or from right to left or in other ways depending on design requirements. The point is that it always has substantially half of the contacts opened by each mask. That is, when there are even contact openings, each mask will open half of the contacts, and when there are odd contact openings such as 15, each mask will open slightly more than half, such as 7 or 8 Each mask will open slightly less than half when there are contact openings. The removal of the layers 1, 2, 4, 8 can also be expressed as the removal of 20 to 2 (n−1) layers for each step.

33 shows masking and etching steps in a different manner from FIG. 35. 36 to 39, the position of 0 appears dark when the photoresist material is provided, and the position of 1 when the photoresist material is absent, opening 8 of the 16 contact openings for each mask.

The example of the etching process of FIGS. 33 and 25 removes the layers (1, 2, 4, 8) for the masks (first to fourth), the contact located (ie etched) by the etching process. Levels are identified by assigned layer designations (0-15). The resulting level located (etched) at each location A through P is represented by the located layers (0, 1, 2, 3, etc.).

Other etching processes may be used. For example, FIG. 36 illustrates that the number of layers etched by the first mask and the fourth mask is changed to be etched by the layers 8 (etched) by the first and third masks, the second and fourth masks. The etching process changes of the layers (4), the layers etched by the third mask (4), and the layer etched by the fourth mask (1). The resulting level located (etched) at each location A to P is represented by the located layers (0th, 8th, 2nd, 10th, etc.).

Instead of (or in addition to) changing the etching process, that is, the number of layers etched by each mask shown in comparison with FIGS. 35 and 36, the mask process and the like may be changed. An embodiment of etching the layers 2 with the second mask of the embodiment of FIG. 35 and etching the layers 4 with the third mask is shown in FIG. 37. However, the point of providing a mask process for the second mask in the embodiment of FIG. 35 (0 0 1 1 0 0 1 1 etc.) becomes a mask process for the third mask in the embodiment of FIG. 0 0 0 0 1 1 1 1 0 0 0 0, etc.) may be a mask process for the fourth mask or a mask process for the second mask of FIG. The resulting level located (etched) at each location A through P is represented by location layers (0, 1, 4, 5, etc.).

38 shows what is referred to as the position change. In this embodiment, the number of layers etched with respect to the masks (first to fourth) is such that the layer (0) and the position ( 9 layers for J), the same for FIG. 35. However, the etching for the respective positions A to P for both the embodiments of FIGS. 35 and 38 is the same. The resulting level located (etched) at each location (J, B, C, etc.) is represented by the positioned layers (9, 1, 2, 3, etc.).

FIG. 39 illustrates a result of performing the first embodiment of FIG. 35, performing the etching process of FIG. 36, changing the mask process of FIG. 37, and changing the position of FIG. 38. However, this resulting structure still has 16 differently located layers for 16 different locations. The resulting level located (etched) at each location (J, B, C, etc.) is represented by the located layers (ninth, first, second, third, etc.).

Any and all patents, patent applications, and publications described above are described herein by reference.

Although the present invention has been described with reference to the above-described preferred embodiments and experimental examples, it will be understood that these embodiments have been described by way of example and not by way of limitation. Those skilled in the art can readily derive modifications and combinations, and it will be understood that such variations and combinations are within the scope of the following claims and the technical spirit of the present invention.

14, 14.1, 14.2, 14.3, 14.4: Interconnected contact areas
17: Interconnection area
18, 18.1, 18.2, 18.3, 18.4: contact levels
24: Upper floor
27: Charge trapping layer
33.1-33.16: Contact openings
34, 34.1, 34.2, 334.3, 34.4: conductive layers 35: ground contact opening
52, 97 ： interlayer dielectric
54, 54.1, 54.2, 54.3, 54.4: Conductors 55: Electrically grounded conductor
57 first portion 59 second portion 61 dielectric sidewall spacer
88, 90, 92: photoresist 89: first mask
93: conductive material 94: word line
96: stop floor
100: 3D stacked integrated circuit device 110: memory array area
120: peripheral area 112: memory cell access layer
130: Semiconductor board
131a and 131b: horizontal field effect transistors 146a and 146b: contacts
144, 154: interlayer dielectric 150a, 150b: bit lines
152a, 152b: contact pads
160-1, 160-2, 160-3, 160-4 ： Levels
161-1a, 161-1b, 161-2a, 161-2b, 161-3a, 161-3b, 161-4: landing areas
165-1, 165-2. 165-3: Insulation layers
171a and 171b: electrode pillars 180: conductors
185: interconnection lines 190: interconnection structure
250, 255, 260, 265, 270, 275 ： Openings
300: integrated circuit device 360: three-dimensional memory array
361 ： row decoder 363 ： column decoder
365: Bus 366: Block
367: Data bus 371: Data input line
372: Data output line 374: Other circuit
544-1, 544-2, 544-3, 544-4: Memory Elements
546 ： Plain decoder
800, 900, 1100, 1300 ： Masks
810, 1000, 1010, 1200, 1210, 1310, 1320: Openings
1400 ： Insulation filling material

Claims (25)

A three-dimensional stacked integrated circuit device having a stack of at least four contact levels, each of which comprises a conductive layer and an insulating layer in the interconnect area, is aligned and exposed to the landing areas at the contact levels. A method of creating interconnect contact regions, the method comprising:
Removing at least a portion of any top layer located above the interconnect area, exposing a first contact level and creating contact openings for each contact level;
Selecting a set of N (N is an integer of at least 2) etch masks to produce a plurality of levels of interconnect contact regions in the stacks of contact levels;
Etching the contact openings up to 2 ^N contact levels using the N masks, wherein using the N masks comprises:
Etching one contact level for substantially half of the contact openings using a first mask;
Etching two contact levels for substantially half of the contact openings using a second mask; And
Performing the removal, selection, and use steps to extend the contact openings to the 2 ^N contact levels,
Thereby electrical conductors can be formed to contact the landing regions at the contact levels through the contact openings. The method of claim 1, wherein said removing step is performed using an additional mask. The method of claim 1,
Using the first mask comprises etching one contact level in all other contact openings using the first mask;
Using the second mask includes etching two contact levels at third and fourth contact openings in at least one set of first to fourth contact openings using the second mask. How to. The method of claim 1, wherein using the N masks comprises:
Etching four contact levels for substantially half of the contact openings using a third mask; And
And etching eight contact levels for substantially half of the contact openings using a fourth mask. The method of claim 4, wherein
Using the third mask comprises etching four contact levels in fifth to eighth contact openings in at least one set of first to eighth contact openings using the third mask;
Using the fourth mask may be performed by using the fourth mask.
Etching eight contact levels in ninth through sixteenth contact openings in at least one set of first through sixteenth contact openings. The method of claim 4, wherein
Using the first mask is performed to etch one contact level in second, fourth, sixth, eighth, tenth, twelfth, fourteenth, and sixteenth contact openings;
Using the second mask is performed to etch two contact levels in third, fourth, seventh, eighth, eleventh, twelfth, fifteenth, and sixteenth contact openings;
Using the third mask is performed to etch four contact levels in the fifth to eighth and thirteenth to sixteenth contact openings;
Using the fourth mask is performed to etch four contact levels in ninth through sixteenth contact openings. The method of claim 4, wherein
Using the first mask is performed to etch eight contact levels in second, fourth, sixth, eighth, tenth, twelfth, fourteenth, and sixteenth contact openings;
Using the second mask is performed to etch two contact levels in the fifth, sixth, seventh, eighth, thirteenth, fourteenth, fifteenth, sixteenth contact openings;
Using the third mask is performed to etch four contact levels in third, fourth, seventh, eighth, eleven, twelfth, fifteenth, sixteenth contact openings;
Using the fourth mask is performed to etch one contact levels in ninth through sixteenth contact openings. The method of claim 1,
Creating ground contact openings through the contact levels; And
Forming an electrical ground conductor through the ground contact opening in electrical contact with the plurality of conductive layers of the contact levels. 9. The method of claim 8, wherein the ground contact opening has a ground opening sidewall,
Electrical contact of the electrical ground conductor between the electrical ground conductor and the plurality of conductive layers of the contact levels by removing a portion of the insulating layers from the ground contact opening sidewall prior to forming the electrical ground conductor. The method further comprises the step of improving. 2. The method of claim 1, wherein said using step is performed in a different order of number of etched contact levels. 2. The method of claim 1, wherein the contact openings have sidewalls, and further comprising forming a dielectric layer on the sidewalls. Wherein each contact level comprises a conductive layer and an insulating layer, and an interconnection area comprises an upper layer and the interconnection area including a stack of contact levels below the upper layer. A method of providing electrical connections to landing regions in a stack of contact levels, the method comprising:
Removing at least a portion of any top layer located above the interconnect area, exposing a first contact level and creating contact openings for each contact level;
Selecting a set of N (N is an integer of at least 2) etch masks to produce a plurality of levels of interconnect contact regions in the stack of contact levels;
Etching the contact openings to 2 ^N levels using the N masks, wherein using the N masks comprises:
Etching one contact level for substantially half of the contact openings using a first mask;
Etching two contact levels for substantially half of the contact openings using a second mask; And
Performing the removal, selection, and use steps to define the contact openings defining sidewalls and extending to 2 ^N contact levels,
Forming a dielectric layer on the sidewalls; And
Forming electrical conductors at the contact levels through the contact openings to the landing regions, wherein the dielectric layer electrically insulates the electrical conductors from the sidewalls. 13. The method of claim 12,
Creating a ground contact through the contact levels; And
Forming an electrical ground conductor through the ground contact opening in electrical contact with the plurality of conductors of the contact levels. 15. The system of claim 13, wherein the ground contact opening has a ground contact opening sidewall,
Prior to forming the electrical ground conductor, portions of the plurality of conductive layers adjacent to the ground contact opening are exposed by removing portions of the insulating layers from sidewalls of the ground contact opening, thereby electrically grounding the plurality of conductive layers. Increasing the electrical contact of the conductor. 13. The method of claim 12, further comprising forming contact opening extensions in an upper layer overlying the interconnect area, wherein forming the electrical conductors comprises: extending the electrical conductors through the contact levels. And a first portion and a second portion of the electrical conductors extending through the top layer. 16. The method of claim 15, wherein forming the electrical conductors is performed to form the first and second portions comprising different conductive materials. A stack of at least first, second, third and fourth contact levels each having a conductive layer and an insulating layer in the interconnect area;
First, second, third, and fourth electrical conductors passing through portions of the stack of contact levels and in electrical contact with first, second, third, and fourth conductive layers, respectively; And
A dielectric sidewall spacer surrounding the periphery of the second, third and fourth electrical conductors so that the second, third and fourth electrical conductors are respectively formed on the second, third and fourth electrical conductor layers. Three-dimensional stacked integrated circuit device characterized in that the electrical contact. 18. The device of claim 17, wherein the first, second, third and fourth electrical conductors have a constant pitch. 19. The device of claim 18, wherein the positions of the first, second, third and fourth electrical conductors are determined by a common mask. 18. The device of claim 17, wherein the positions of the first, second, third and fourth electrical conductors are determined by a common mask. 18. The stack of claim 17 further comprising a ground conductor passing through portions of the stack of contact levels and in electrical contact with the first, second, third and fourth conductive layers, respectively. Integrated circuit devices. 22. The device of claim 21 wherein the positions of the first, second, third and fourth electrical conductors and the ground conductors are determined by a common mask. A stack of at least first, second, third and fourth contact levels each having a conductive layer and an insulating layer in the interconnect area;
First, second, third, and fourth electrical conductors passing through portions of the stack of contact levels and in electrical contact with first, second, third, and fourth conductive layers, respectively; And
And said first, second, third and fourth electrical conductors having a constant pitch. 24. The device of claim 23, wherein the positions of the first, second, third and fourth electrical conductors are determined by a common mask. A stack of at least first, second, third and fourth contact levels each having a conductive layer and an insulating layer in the interconnect area;
First, second, third, and fourth electrical conductors passing through portions of the stack of contact levels and in electrical contact with first, second, third, and fourth conductive layers, respectively; And
Second, third, and fourth electrical contacts with second, third, and fourth electrically conductive layers, respectively, having dielectric sidewall spacers surrounding the periphery of the second, third, and fourth electrical conductors; Electrical conductors; And
A ground conductor passing through portions of the stack of contact levels and in electrical contact with first, second, third and fourth conductive layers, respectively;
And said positions of said first, second, third and fourth electrical conductors and said ground conductors having a constant pitch and which can be determined by a common mask.

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