KR20120087113A - ESD structure for low capacitance and high speed - Google Patents
ESD structure for low capacitance and high speed Download PDFInfo
- Publication number
- KR20120087113A KR20120087113A KR1020120073213A KR20120073213A KR20120087113A KR 20120087113 A KR20120087113 A KR 20120087113A KR 1020120073213 A KR1020120073213 A KR 1020120073213A KR 20120073213 A KR20120073213 A KR 20120073213A KR 20120087113 A KR20120087113 A KR 20120087113A
- Authority
- KR
- South Korea
- Prior art keywords
- esd
- well
- nmos
- gate
- pmos
- Prior art date
Links
- 239000000758 substrate Substances 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 2
- 229910021332 silicide Inorganic materials 0.000 claims 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims 1
- 230000002542 deteriorative effect Effects 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 230000005611 electricity Effects 0.000 description 4
- 230000003068 static effect Effects 0.000 description 4
- 230000006378 damage Effects 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000005283 ground state Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012421 spiking Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
- H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
적은 면적과 동시에 양호한 ESD 특성을 가지는 집적회로 및 그 제조방법이 개시되어 있다. 본 발명은 소자 기능을 수행하는 트랜지스터들 및 ESD 보호 트랜지스터들의 면적을 작게하는 것과 동시에, ESD특성이 나빠지는 것을 방지하기 위하여 ESD 보호 트랜지스터인 NMOS트랜지스터의 드레인 영역에 능동소자인 PMOS트랜지스터를 삽입한다. NMOS 와 PMOS 트랜지스터는 인버터(Inverter) 로 연결되어 있어서, 정상동작시는 NMOS 및 PMOS 가 모두 턴온(On) 상태로 되어 있으나, ESD 상황에서는 NMOS 및 PMOS트랜지스터가 턴오프(Turn-Off)되어 PMOS트랜지스터 하단의 N웰을 통한 패스(Path)가 형성되어 큰 저항을 얻는 구조이다. 따라서 ESD 상황에서는 외부에서 들어오는 전류가 N웰을 통해서 지나므로, 필요한 저항을 N웰을 통해서 얻을 수 있다. An integrated circuit and a method of manufacturing the same have a small area and good ESD characteristics. The present invention inserts a PMOS transistor, which is an active element, into a drain region of an NMOS transistor, which is an ESD protection transistor, in order to reduce the area of transistors and ESD protection transistors that perform device functions and to prevent an ESD characteristic from deteriorating. NMOS and PMOS transistors are connected to an inverter, and both NMOS and PMOS are turned on during normal operation.However, in an ESD situation, NMOS and PMOS transistors are turned off and PMOS transistors are turned off. A path through the N well at the bottom is formed to obtain a large resistance. Therefore, in an ESD situation, current from the outside passes through the N well, so the necessary resistance can be obtained through the N well.
Description
본 발명은 반도체 집적회로에 관한 것으로, 특히 정전방전(ESD; Electro static Discharge) 현상으로부터 집적회로의 내부소자를 보호하기 위한 ESD 보호 회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly, to an ESD protection circuit for protecting internal elements of an integrated circuit from an electrostatic discharge (ESD) phenomenon.
반도체 집적회로에서 집적도가 증가할수록 소스와 드레인의 채널길이는 줄어들게 되며, 그에 의한 의도하지 않은 전기적 현상이 발생하는데, 예를 들면 ESD 특성 악화, 핫 캐리어 효과(hot carrier effect), 펀치 쓰루(punch-through) 등이다.In semiconductor integrated circuits, as the degree of integration increases, the channel lengths of the source and drain decrease, resulting in unintended electrical phenomena, such as deterioration of ESD characteristics, hot carrier effects, and punch-through. through).
정전기에 의한 정전방전(Electrostatic Discharge)에는 크게 두가지 종류가 있다. 첫째가 디바이스가 패키지(Package) 형태로 어떠한 테스트 장비 등에 장착될 때 그 장비의 접지 상태가 불안정하여 발생하는 정전기로 전압은 약 200V로 낮으나 임피던스가 작아서 전하량은 상대적으로 많은 경우(Machine Model)이며, 두번째는 디바이스가 사용자의 손에 닿을 때 인체에 유기되어 있던 정전기가 방전되는 형태로 약 2000V의 고전압이나 큰 임피던스를 통해서 방전되어 낮은 전하량을 가지는 경우(Human Body Model)이다.There are two main types of electrostatic discharge. First, when the device is installed in any test equipment in the form of package, the static electricity generated by unstable ground state of the equipment is about 200V but the impedance is small, so the amount of charge is relatively high (Machine Model). The second case is when the device touches the user's body and discharges the static electricity that has been induced in the human body, and discharges it through a high voltage of about 2000V or a large impedance (Human Body Model).
이러한 정전기에 노출되면 MOS 디바이스는 게이트 옥사이드 파괴(gate oxide rupture), 접합 파괴(junction spiking) 등의 현상이 발생하여 디바이스가 완전히 파괴되거나 혹은 미세하게 데미지(damage)를 받아 소자 신뢰도(reliability)에 심각한 영향을 준다.When exposed to such static electricity, MOS devices may experience gate oxide rupture, junction spiking, or the like, resulting in complete device destruction or minor damage, resulting in severe device reliability. affect.
따라서 정전기의 유입에 따른 파괴로부터 집적회로를 보호하기 위하여 집적회로 내부와 외부와의 연결부위에 ESD 보호회로를 삽입한다. 정전기 방전은 ESD 보호회로에 의해 접지선(ground line) 또는 Vcc선을 통해 제거되며, 내부회로는 안전하게 되는 것이다.Therefore, in order to protect the integrated circuit from destruction due to the inflow of static electricity, an ESD protection circuit is inserted at the connection portion between the inside and the outside of the integrated circuit. Electrostatic discharge is removed through the ground line or the Vcc line by the ESD protection circuit, and the internal circuit is safe.
그러나, 종래의 기술로 ESD 보호회로를 구성할 경우, 단위 크기당의 ESD 특성이 좋지 않아, 전체 면적이 커지게 된다.However, when the ESD protection circuit is constructed by the conventional technology, the ESD characteristics per unit size are not good, and the total area becomes large.
위와 같이 많은 면적이 필요한 것을, 적은 면적에서 양호한 특성을 얻는 구조로 변경하여, ESD 에 안전한 집적회로를 공급하는 데 있다.In order to provide a safe integrated circuit for ESD by changing a structure requiring a large area as described above to obtain good characteristics in a small area.
상기 목적을 달성하기 위한 본 발명의 ESD 보호회로는, 자신의 게이트를 가지고, 접지전압단에 한쪽 접합이 연결된 NMOS트랜지스터, 한쪽은 NMOS트랜지스터의 게이트에 다른 출력단은 PMOS트랜지스터의 게이트로 연결이 되는 인버터(Inverter), 게이트의 한쪽은 인버터에 연결이 되고 한쪽은 NMOS에 연결이 되며 다른 한쪽은 패드에 연결이 되는 PMOS 트랜지스터를 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the ESD protection circuit of the present invention includes an NMOS transistor having its own gate and one junction connected to the ground voltage terminal, one of which is connected to the gate of the NMOS transistor and the other output terminal to the gate of the PMOS transistor. (Inverter), one side of the gate is connected to the inverter, one side is connected to the NMOS, and the other side is characterized in that it comprises a PMOS transistor connected to the pad.
또한 본 발명의 ESD 보호회로는 P형 기판; 상기 P형 기판 내의 일부영역에 형성된 N웰; 상기 P형 기판에 형성되며, 접지전도라인이 콘택되는 N+ 소스접합, N+ 드레인접합 및 게이트 폴리실리콘을 포함하는 NMOS트랜지스터; 상기 N웰영역의 기판에 형성되며, 상기 NMOS트랜지스터의 N+ 소스접합에 접하여 형성된 P+ 드레인접합, P+ 소스접합 및 게이트 폴리실리콘을 포함하는 PMOS트랜지스터; 상기 PMOS트랜지스터의 P+소스접합에 접하여 형성되며 패드 전도 라인이 콘택되는 N+ 접합; 및 상기 PMOS 및 NMOS 트랜지스터의 각 게이트 폴리실리콘과, 소스/드레인 접합으로 구성되는 것을 특징으로 한다.In addition, the ESD protection circuit of the present invention is a P-type substrate; An N well formed in a portion of the P-type substrate; An NMOS transistor formed on the P-type substrate and including an N + source junction, an N + drain junction, and a gate polysilicon to which a ground conductive line is contacted; A PMOS transistor formed on a substrate of the N well region and including a P + drain junction, a P + source junction, and a gate polysilicon formed in contact with an N + source junction of the NMOS transistor; An N + junction formed in contact with the P + source junction of the PMOS transistor and having a pad conducting line contacted thereto; And each gate polysilicon of the PMOS and NMOS transistors, and a source / drain junction.
상기와 같이 이루어진 본 발명은, ESD 보호 회로를 포함하는 집적회로가 적은 면적을 차지하면서도 좋은 ESD 보호 특성을 얻는 효과가 있다.According to the present invention, the integrated circuit including the ESD protection circuit occupies a small area and has an effect of obtaining good ESD protection characteristics.
또한, ESD보호 트랜지스터인 NMOS트랜지스터의 드레인 영역에 PMOS트랜지스터의 삽입으로 인해, 정상적인 동작상황에서 턴온(Turn-On)된 PMOS트랜지스터의 적은 저항으로 특성저하를 방지하면서도 ESD에 양호한 회로 및 구조를 얻을 수 있다.In addition, due to the insertion of the PMOS transistor into the drain region of the NMOS transistor, which is an ESD protection transistor, a low resistance of the turned-on PMOS transistor under normal operation prevents deterioration of the characteristics and provides a good circuit and structure for ESD. have.
도 1은 일반적인 NMOS트랜지스터를 이용하여 ESD 보호를 하는 하는 종래기술의 회로
도 2는 본 발명에 따른 ESD 보호회로의 구성을 개념적으로 나타낸 도면.
도 3 본 발명에 따른 EDS 보호 회로의 평면도 및 단면도.
도 4 본 발명에 따른 EDS 보호 회로의 평면도 및 단면도.1 is a circuit of the related art for ESD protection using a general NMOS transistor
2 conceptually illustrates a configuration of an ESD protection circuit according to the present invention;
3 is a plan view and a sectional view of an EDS protection circuit according to the present invention.
4 is a plan view and a sectional view of an EDS protection circuit according to the present invention.
본 발명의 EDS 보호회로에서는, PMOS트랜지스터의 게이트는 NMOS트랜지스터의 게이트에서 인버터를 통해서 연결하여, 정상적인 동작시는 PMOS트랜지스터가 턴온(Turn-On)되어 PMOS트랜지스터를 통한 작은 저항을 형성하나, ESD 상황에서는 PMOS트랜지스터가 턴오프(Turn-Off)되어 PMOS트랜지스터 하단의 N웰을 통한 패스(Path)가 형성되어 큰 저항을 얻는 구조이다. 따라서 ESD 상황에서는 외부에서 들어오는 전류가 N웰을 통해서 지나므로, 필요한 저항을 N웰을 통해서 얻을 수 있는 구조이다.In the EDS protection circuit of the present invention, the gate of the PMOS transistor is connected through the inverter at the gate of the NMOS transistor, and during normal operation, the PMOS transistor is turned on to form a small resistance through the PMOS transistor, but in an ESD situation In the PMOS transistor, the PMOS transistor is turned off to form a path through the N well at the bottom of the PMOS transistor, thereby obtaining a large resistance. Therefore, in the ESD situation, since the external current flows through the N well, the necessary resistance can be obtained through the N well.
본 발명의 기술적 사상은 살리사이드 공정에 의해 NMOS 트랜지스터(231)의 드레인영역에서 저항이 낮아지더라도 이를 PMOS트랜지스터(232)에 의해 보상하는 방식이다.The technical idea of the present invention is to compensate for this by the PMOS transistor 232 even if the resistance in the drain region of the NMOS transistor 231 is lowered by the salicide process.
PMOS 트랜지스터는 게이트가 인버터를 통해서 NMOS트랜지스터의 게이트에 접속되어 있는 바, 정상동작에서는 PMOS트랜지스터가 턴온(Turn-On) 되나, ESD 상황하에서는 PMOS트랜지스터가 턴오프(Turn-Off)되어 PMOS트랜지스터의웰을 통한 저항에 의해서 NMOS 트랜지스터의 드레인 저항은 커지게 된다.In the PMOS transistor, the gate is connected to the gate of the NMOS transistor through the inverter. In normal operation, the PMOS transistor is turned on.However, under the ESD situation, the PMOS transistor is turned off and the well of the PMOS transistor is turned off. The resistance through the NMOS transistor increases the drain resistance.
Claims (2)
입력단이 상기 NMOS트랜지스터의 게이트단에 연결되는 인버터(Inverter); 및
상기 NMOS트랜지스터와 외부 접합 패드 사이에 연결되며 게이트가 상기 인버터의 출력단에 연결되는 PMOS트랜지스터를 포함하는 것을 특징으로 하는 반도체 집적회로의 ESD 보호회로.An NMOS transistor having a gate connected to a protected integrated circuit and having one junction connected to a ground voltage terminal;
An inverter having an input terminal connected to the gate terminal of the NMOS transistor; And
And a PMOS transistor connected between the NMOS transistor and an external junction pad and whose gate is connected to an output terminal of the inverter.
상기 PMOS트랜지스터는,기판의 표면 하부에 형성된 N웰;상기 N웰 내의 기판의 표면 하부에 형성된 소스/드레인 접합;상기 N웰의 기판 상부에 형성된 게이트 폴리실리콘; 및 상기 폴리실리콘 및 상기 소스/드레인 접합 상에 형성된 실리사이드층을 포함하여 이루어짐을 특징으로 하는 반도체 집적회로의 ESD 보호회로.The method of claim 1,
The PMOS transistor includes: an N well formed under the surface of the substrate; a source / drain junction formed under the surface of the substrate in the N well; a gate polysilicon formed over the substrate of the N well; And a silicide layer formed on the polysilicon and the source / drain junction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020120073213A KR20120087113A (en) | 2012-07-05 | 2012-07-05 | ESD structure for low capacitance and high speed |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020120073213A KR20120087113A (en) | 2012-07-05 | 2012-07-05 | ESD structure for low capacitance and high speed |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020050017927A Division KR101369194B1 (en) | 2005-03-03 | 2005-03-03 | Esd protection circuit for semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20120087113A true KR20120087113A (en) | 2012-08-06 |
Family
ID=46872766
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020120073213A KR20120087113A (en) | 2012-07-05 | 2012-07-05 | ESD structure for low capacitance and high speed |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20120087113A (en) |
-
2012
- 2012-07-05 KR KR1020120073213A patent/KR20120087113A/en not_active Application Discontinuation
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10204897B2 (en) | Electrostatic discharge protection semiconductor device | |
| CN103579224B (en) | ESD protects | |
| JP4320038B2 (en) | Semiconductor integrated circuit | |
| US11239229B2 (en) | Self-biased bidirectional ESD protection circuit | |
| CN101789428A (en) | Embedded PMOS auxiliary trigger SCR structure | |
| TWI449150B (en) | Esd protection device structure | |
| CN207320106U (en) | For protecting against the equipment and integrated circuit of static discharge | |
| CN102270658A (en) | Low-trigger-voltage and low-parasitic-capacitance silicon controlled structure | |
| CN101814498A (en) | Structure with built-in NMOS auxiliary trigger controllable silicon | |
| US7843009B2 (en) | Electrostatic discharge protection device for an integrated circuit | |
| CN105405843B (en) | Electrostatic discharge protective circuit | |
| KR101369194B1 (en) | Esd protection circuit for semiconductor integrated circuit | |
| TWI538160B (en) | Electrostatic discharge protection device and applications thereof | |
| KR20120087113A (en) | ESD structure for low capacitance and high speed | |
| KR100861294B1 (en) | Electrostatic Protection Devices for Semiconductor Circuits | |
| KR100638455B1 (en) | ESD protection circuit for high voltage device and semiconductor device having same | |
| US9659921B2 (en) | Power switch device | |
| KR20060100274A (en) | Semiconductor device and design method thereof | |
| KR100917055B1 (en) | Semiconductor device for ESD protection | |
| US6781204B1 (en) | Spreading the power dissipation in MOS transistors for improved ESD protection | |
| KR100681205B1 (en) | Semiconductor device for electrostatic discharge protection circuit | |
| JP2023152286A (en) | ESD protection circuit and semiconductor device | |
| KR100713923B1 (en) | Electrostatic Protection Devices for Semiconductor Circuits | |
| KR20070052912A (en) | Electrostatic Protection Devices for Semiconductor Circuits | |
| KR100639224B1 (en) | Electrostatic discharge protection element |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A107 | Divisional application of patent | ||
| PA0107 | Divisional application |
Comment text: Divisional Application of Patent Patent event date: 20120705 Patent event code: PA01071R01D |
|
| PG1501 | Laying open of application | ||
| PC1203 | Withdrawal of no request for examination | ||
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |