KR20120025750A - Synchronous boost converter for switching voltage limit at shutdown power ic driving amoled - Google Patents

Abstract

A synchronous step-up converter circuit for implementing a switching voltage limit during shutdown of the AMOLED driving power IC of the present invention includes: a power supply 410 for generating an input voltage V _in ; An inductor 420 connected to the power source 410 to generate an inductor current I _L ; A power switching element connected to the switching node N1 that receives the inductor current I _L first and the inductor connected between the switching node N1 and the output node N2 and applied to the switching node N1. Switching transistors having a transfer switching element for delivering a current I _L to an output node N2; A boosting controller 435 for limiting a sudden rise in the switching voltage V _sw applied to the switching node N1 when a shutdown occurs in an integrated circuit (IC); A first gate driver 431 for controlling a gate voltage of the power switching element; A second gate driver 432 for controlling a gate voltage of the transfer switching device; And applying a control signal to the first gate driver 431 and the second gate driver 432 when a shutdown occurs in an integrated circuit (IC), so that the boosting controller 435 performs the switching voltage V _sw. It is a technical feature to provide a control circuit portion 433 to limit the sudden rise of the).

Description

SYNCHRONOUS BOOST CONVERTER FOR SWITCHING VOLTAGE LIMIT AT SHUTDOWN POWER IC DRIVING AMOLED}

The present invention relates to a synchronous boost converter circuit of a power integrated circuit (IC) for driving an active matrix organic light-emitting diode (AMOLED), and more particularly, a switching node when a shutdown occurs in the IC. The present invention relates to a synchronous step-up converter circuit that implements a switching voltage limit in shutdown that suppresses an IC breakdown by suppressing a rise in voltage (V _sw ).

A boost converter is a device that performs direct current-to-direct current (DC-DC) conversion that produces an output voltage greater than the supply voltage, up to a required voltage level sufficient to provide power to connected electronics. It is often used to increase the battery voltage.

1 shows a conventional synchronous boost converter circuit.

Referring to FIG. 1, the conventional synchronous boost converter circuit 100 includes a power source 110, an inductor 120, a switch element unit 130, a capacitor 140, and a load resistor 150.

The power supply 110 generates an input voltage V _in of the direct current DC, and the inductor current I _L corresponding to the input voltage V _in flows through the inductor 120.

 The switch element unit 130 includes MN1 configured as an NMOS transistor and MP2 and MP3 configured as a PMOS, and also controls gate voltages of the first gate drivers 1 and 131 for controlling the gate voltage of the MN1. It is connected to each of the second gate driver (Gate driver 2, 132), the first gate driver (Gate driver 1, 131) and the second gate driver (Gate driver 2, 132) for the first gate driver (Gate driver 1, 131) A control circuit 133 for controlling two gate drivers 2 and 132 is provided.

The control circuit 133 detects the current sensing signal ISNS for detecting the magnitude of the inductor current I _L of the switching node N1 and the output voltage Vout of the output node N2, and the first detection signal. By adjusting the feedback resistor R _F1 and the second feedback resistor R _F2 MN1 acts as a power switching element and a transfer switching element transfers the inductor current I _L applied from the switching node N1 to the output node N2 with the feedback voltage VFB which sets the target voltage as an input. By controlling the switching operation of the MP2, MP3 to adjust the amount of the inductor current (I _L ) to generate an output voltage (Vout) boosted (boosting) than the input voltage (V _in ) to the output node (N2).

The capacitors Cout and 140 charge a charge corresponding to the output voltage Vout, and the load resistance resistor R _load 150 receives an output voltage Vout boosted by more than the input voltage V _in . .

However, the conventional synchronous boost converter circuit 100 has the following problems, which will be described below with reference to FIGS. 2A to 3B.

2A and 2B show an inductor current I _L and a switching voltage V _sw of a switching node over time when an abnormal IC shutdown occurs due to a system failure during normal operation. Figures 3a and 3b show the general state of the circuit diagram, and Figs. 3a and 3b show the inductor current I _L and the switching node over time when a shutdown occurs in the IC due to a load short circuit. The graph shows the state of the switching voltage (V _sw ).

Herein, an integrated circuit (IC) refers to an integrated circuit except for a power supply 110, an inductor 120, a capacitor 140, and a load resistor 150.

3A and 3B, when the inductor current I _L rises due to a load short circuit, the internal inductor limit current I _L _limit by the internal protection circuit to protect the integrated circuit (IC). The detection circuitry automatically shuts down the IC.

However, the over current above the inductor limit current I _L _limit rapidly raises the switching voltage V _sw of the switching node N1 at the moment of shutdown to the power switch element inside the IC. Serious problems resulting in the destruction of the MN1 device used are brought about.

That is, the control circuit unit 133 constituting the conventional switch element unit 130 is a power short circuit element of the power switch element inside the IC due to a sudden rise in the switching voltage (V _sw ) when a shutdown occurs in the IC due to a load short circuit. There was a problem that could not prevent destruction.

The technical problem to be solved by the present invention is to limit the switching voltage in the shutdown (shutdown) to prevent the IC breakdown by suppressing the rise of the switching voltage (V _sw ) of the switching node when the shutdown occurs in the IC To provide a synchronous step-up converter circuit to implement the.

According to an aspect of the present invention, there is provided a synchronous step-up converter circuit for implementing a switching voltage limit when an AMOLED driving power IC is shut down, including: a power supply 410 for generating an input voltage V _in ; An inductor 420 connected to the power source 410 to generate an inductor current I _L ; A power switching element connected to the switching node N1 that receives the inductor current I _L first and the inductor connected between the switching node N1 and the output node N2 and applied to the switching node N1. Switching transistors having a transfer switching element for delivering a current I _L to an output node N2; A boosting controller 435 for limiting a sudden rise in the switching voltage V _sw applied to the switching node N1 when a shutdown occurs in an integrated circuit (IC); A first gate driver 431 for controlling a gate voltage of the power switching element; A second gate driver 432 for controlling a gate voltage of the transfer switching device; And applying a control signal to the first gate driver 431 and the second gate driver 432 when a shutdown occurs in an integrated circuit (IC), so that the boosting controller 435 performs the switching voltage V _sw. Control circuitry 433 is provided to limit the sudden rise of < RTI ID = 0.0 >

The present invention has the advantage of preventing the IC breakdown by suppressing the rise of the switching voltage (V _sw ) of the switching node (shutdown) when the shutdown occurs in the IC.

1 shows a conventional synchronous boost converter circuit.
FIG. 2A shows a state of a current I _L flowing in an inductor over time when an abnormal shutdown occurs in an IC due to a system failure during a normal synchronous step-up converter circuit. Is shown in the graph.
2B illustrates a voltage V of a switching node over time when an abnormal shutdown occurs in an IC due to a system failure during a normal synchronous step-up converter circuit. _sw ) shows the state of the graph.
FIG. 3A is a graph illustrating a state of a current I _L flowing in an inductor over time when a shutdown occurs in an IC due to a load short circuit in a conventional synchronous boost converter circuit.
FIG. 3B is a graph illustrating a state of a voltage V _sw of a switching node over time when a shutdown occurs in an IC due to a load short circuit in a conventional synchronous boost converter circuit. FIG. will be.
4 shows a synchronous boost converter circuit according to the present invention.
5A illustrates a circuit configuration and operation of the first gate driver when a shutdown occurs in the IC.
FIG. 5B illustrates a circuit configuration and operation of the second gate driver when a shutdown occurs in the IC.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

4 shows a synchronous boost converter circuit according to the present invention.

Referring to FIG. 4, the synchronous boost converter circuit 400 according to the present invention includes a power supply 410, an inductor 420, a switching and boost control processor 430, a capacitor 440, and a load resistor 450. do.

Hereinafter, a simple function of the elements constituting the synchronous boost converter circuit 400 according to the present invention will be described.

The power supply 410 generates an input voltage V _in of the direct current DC, and an inductor current I _L having a value corresponding to the input voltage V _in flows through the inductor 420.

The capacitors Cout and 440 are connected to the output node N2 to charge a charge corresponding to the output voltage Vout. The load resistor R _load 450 is connected to the output node N2 and receives an output voltage Vout boosted and boosted by more than the input voltage V _in .

 The switching and boost control processor 430 includes switching transistors, a boost controller 435, first gate drivers 1 and 431, second gate drivers 2 and 432, and a control circuit unit 433.

The switching transistors are NMOS transistors for generating an output voltage Vout boosted by more than the input voltage V _in to the output node N2 by controlling the amount of inductor current I _L by a selective switching operation. MN1 and PMOS transistors, which operate as power switching elements, include MP2 and MP3, which operate as transfer switching elements that transfer the inductor current I _L applied from the switching node N1 to the output node N2.

The booster controller 435 shuts down the IC including the MN5, MN7, and N4 transistors including the NMOS transistor, the MP4, MP6, and NAND logic circuits, the first voltage divider R1, and the second voltage divider R2. ) Prevents the destruction of the power switch element inside the IC by limiting the rapid rise of the switching voltage (V _sw ).

The control circuit 433 controls the first gate driver 1, 431 and the second gate driver 2, 432 when a shutdown occurs in the integrated circuit (IC), thereby boosting the controller 435. ) Can limit the rapid rise of the switching voltage (V _sw ).

The control circuit 433 detects the current sensing signal ISNS for detecting the magnitude of the inductor current I _L of the switching node N1 and the output voltage Vout of the output node N2, and the first detection signal is generated. By adjusting the feedback resistor R _F1 and the second feedback resistor R _F2 A signal for controlling the first and second gate drivers 431 and 432 is generated by inputting a feedback voltage VFB for setting a target voltage.

The gate voltage of the MN1 is controlled by the first gate drivers 1 and 431, and the gate voltages of the MP2 and MP3 are controlled by the second gate drivers 2 and 432.

5A illustrates a circuit configuration and operation of the first gate driver when a shutdown occurs in the IC.

Referring to FIG. 5A, the first gate drivers 1 and 431 may include a first PMOS 11, a first NMOS 12, a first inverter 13, a second inverter 14, and a third inverter 15. ).

An input voltage V _in is applied to the first inverters 13 to the third inverter 15.

The drain terminals of the first PMOS 11 and the first NMOS 12 are commonly connected to each other, and a gate voltage is applied to the MN1 through the node a1. The gate terminal of the first PMOS 11 is connected to the first inverter 13. The gate terminal of the first NMOS 12 is connected to the third inverter 15, and the third inverter 15 is sequentially connected to the second inverter 14.

The disable / enable control signal is supplied to the first PMOS 11 and the first NMOS 12 through node a2.

Hereinafter, an operation of controlling MN1 when a shutdown occurs in an integrated circuit (IC) will be described.

When a shutdown signal is generated in the integrated circuit (IC) and an enable = “low” signal is applied to the node a2, the first PMOS 11 outputs the output of the first inverter 13. This goes high and turns off.

In the same way, the gate voltage of MN1 is floating since the first NMOS 12 goes low through the second inverter 14 and the third inverter 15 to be turned off. It becomes a state.

FIG. 5B illustrates a circuit configuration and operation of the second gate driver when a shutdown occurs in the IC.

Referring to FIG. 5B, the second gate drivers 2, 432 may include a first PMOS 21, a first NMOS 22, a first inverter 23, a second inverter 24, and a third inverter 25. ), Fourth inverter 26 and fifth inverter 27.

The first inverters 23 to the fifth inverters 27 are applied with a high voltage V _in / Vout among the input voltage V _in or the output voltage Vout.

The drain terminals of the first PMOS 21 and the first NMOS 22 are commonly connected to each other, and a gate voltage is applied to the MP3 through the node b1.

The gate terminal of the first PMOS 21 is connected to the second inverter 24, and the second inverter 24 is connected to the first inverter 23 in order. The gate terminal of the first NMOS 22 is connected to the fourth inverter 26, and the fourth inverter 26 is connected to the third inverter 25.

The gate terminal of the MP2 is connected to the fifth inverter 27 to receive a voltage applied through the node b3.

The Disable / Enable control signal is supplied to MP3 through node b2 and to MP2 through node b3. In normal state, Enable = "High" is applied. When shutdown occurs, Enable = "Low", that is, Disable = "High. Is approved.

Hereinafter, an operation in which MP2 and MP3 are controlled when a shutdown occurs in an integrated circuit (IC) will be described.

If a shutdown occurs in an integrated circuit (IC) and an Enable = “Low” signal is applied to node b3, MP2 outputs the output of the fifth inverter 14 to a high state. To be turned off.

In a similar manner, the first PMOS 21 is turned on with the output low through the second inverter 14 and the third inverter 15, and the first NMOS 22 is turned on. The output is turned low through the third inverter 25 and the fourth inverter 26 to be turned off. As a result, the node b1 is applied with a high voltage to turn the MP3 off. turn off).

Hereinafter, a circuit connection relationship between the elements constituting the synchronous boost converter circuit 400 according to the present invention will be described.

Since the power source 410 and the inductor 420 are connected in series with each other, an inductor current I _L having a value corresponding to the input voltage V _in generated from the power source 410 flows through the inductor 420.

 The inductor 420 and MN1 are connected to each other with the switching node N1 as a branch point, and the drain terminal of MN1 is connected to the switching node N1 and the source terminal of MN1 to ground GND. .

MP2 and MP3 have their respective source terminals connected in common between the switching node N1 and the output node N2 in series. MP2 and MP3 each include a first parasitic diode D1 and a second parasitic diode D2.

Hereinafter, the connection relationship between the elements constituting the boost control unit 435 will be described.

The gate terminals of MP3 are connected to the gate terminals of MP4 and MN5 through nodes N4 and N5, respectively.

The first input terminal of the NAND logic circuit has a drain terminal connected to the common terminal between MP4 and MN5 through the node N8. The second input terminal of the NAND logic circuit is connected to the gate terminal of the MN7 through the node N7.

The output terminal of the NAND logic circuit is connected to the gate terminal of the MP6, and the drain terminal of the MP6 is connected in series with the first voltage divider R1 and the first voltage divider R1 and the second voltage divider. R2 and the drain terminals of the MN7 are connected in series. The source terminal of the MN7 is connected to ground (GND).

In the NAND logic circuit, a higher voltage (V _in / Vout) of an input voltage (V _in ) or an output voltage (Vout) is applied to a power source.

The gate terminal of the MN1 is connected to the node N9 which branches the first voltage divider R1 and the second voltage divider R2 through the node N10.

 The drain terminal of the MP3 is connected to the output node N2, and the capacitor 440 and the load resistor 450 are connected in parallel to each other through the output node N2.

Each of the nodes N4, N5, and N7 is connected to the gate terminals of the MP4, MN5, and MN7, and the node N6 receives a disable / enable signal, and is connected to the node N5 and the node N7.

Hereinafter, a principle and an operation of preventing IC destruction due to an increase in the switching voltage V _sw of a switching node when a shutdown occurs in the IC by the synchronous boost converter circuit 400 according to the present invention. Explain.

When a shutdown is sensed or input to the IC due to a load short circuit or a fault in the system, the control circuit 433 sets the enable signal to "Low" and the first gate driver ( Gate drivers 1 and 431 and second gate drivers 2 and 432.

 In this case, the gate voltage of the MN1 is floated because the first PMOS 11 and the first NMOS 12 of the first gate driver 431 are turned off as shown in FIG. 5A. 435 can be controlled.

On the other hand, since the gate voltages of MP2 and MP3 are turned high and turned off as described with reference to FIG. 5B, the boosting controller 435 is able to control MN1 without being affected by MP2 and MP3. do.

When the switching voltage V _sw of the switching node N1 rises and the voltage of the node N3 rises to a voltage capable of turning on the MP4, the MP4 is turned on and the node N8 is turned on. High. That is, the first input terminal of the NAND logic circuit is input high through the node N8.

The second input terminal of the NAND logic circuit has the output of the node b1 high due to the Enable = " Low " signal of the second gate driver 432, and is high through the node N7. (High) voltage is applied.

Accordingly, the output of the NAND logic circuit is changed to a low state, and accordingly, MP6 is turned on so that node N9 becomes high, and the high state through node N10 is MN1. Is applied to the gate terminal of.

This turns on MN1 acting as a power switch to form a current path of the inductor 420 to discharge the inductor current I _L. As a result, it is possible to prevent the IC from being destroyed due to the sudden rise of the switching voltage V _sw at the switching node N1.

Meanwhile, the time at which MN1 is turned on depends on the sizes of MP4 and MN5, and the limiting level of switching voltage V _sw of the switching node N1 is the first voltage divider R1 and the second voltage divider. It is realized by adjusting the size of R2) to adjust the gate voltage applied to the gate terminal of MN1.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the scope of the present invention.

410: power
420: inductor
430: switching and boost control processing unit
431: First gate driver
432: second gate driver
433: control circuit
435 step-up control
440: Capacitor
450: load resistance

Claims (7)

A power source 410 for generating an input voltage V _in ;
An inductor 420 connected to the power source 410 to generate an inductor current I _L ;
A power switching element connected to the switching node N1 that receives the inductor current I _L first and the inductor connected between the switching node N1 and the output node N2 and applied to the switching node N1. Switching transistors having a transfer switching element for delivering a current I _L to an output node N2;
A boosting controller 435 for limiting a sudden rise in the switching voltage V _sw applied to the switching node N1 when a shutdown occurs in an integrated circuit (IC);
A first gate driver 431 for controlling a gate voltage of the power switching element;
A second gate driver 432 for controlling a gate voltage of the transfer switching device; And
When a shutdown occurs in an integrated circuit (IC), a control signal is applied to the first gate driver 431 and the second gate driver 432 so that the boosting controller 435 may switch the switching voltage V _sw . A synchronous step-up converter circuit for implementing a switching voltage limit during shutdown of the AMOLED driving power IC, characterized in that it comprises a control circuit section 433 for limiting the sudden rise of the AMOLED driving power IC. The method of claim 1,
The power switching device uses a first NMOS transistor MN1,
The transfer switching device uses a second PMOS transistor MP2 and a third PMOS transistor MP3,
The second PMOS transistor MP2 and the third PMOS transistor MP3 have a source terminal connected to each other. A synchronous step-up type for implementing a switching voltage limit during shutdown of an AMOLED driving power IC. Converter circuit. The method of claim 1, wherein the boost control unit 435,
A fourth PMOS transistor MP4 connected to a common source terminal and a source terminal of a second PMOS transistor MP2 and a third PMOS transistor MP3 constituting the transfer switching device;
A first input terminal of a NAND logic circuit connected to the drain terminal of the fourth PMOS transistor MP4;
A second input terminal of the NAND logic circuit connected to the gate terminal of the seventh NMOS transistor MN7;
An output terminal of the NAND logic circuit connected to the gate terminal of the sixth PMOS transistor MP6; And
The first voltage resistor R1 and the second voltage divider R2 connected in series to the sixth PMOS transistor MP6 may include a switching voltage limit during shutdown of the AMOLED driving power IC. Synchronous boost converter circuit. The method of claim 3,
An amol being connected to a gate terminal of the first NMOS transistor MN1 which operates as the power switching element at a branch point N9 of the first voltage divider R1 and the second voltage divider R2. Synchronous step-up converter circuitry that implements switching voltage limit during shutdown of Red IC's Power IC. The method of claim 1, wherein the control circuit unit 433,
When to generate a current sense signal (ISNS) determines that detects the magnitude of the switching voltage (V _sw), and the magnitude of the switching voltage (V _sw) exceeds the value of the inductor limiting current (I _L _limit) enabled (enable ) Is applied to the first gate driver 431 and the second gate driver 432 with the signal " low " state, thereby limiting the switching voltage of the AMOLED driving power IC. Synchronous boost converter circuit. 6. The method of claim 5,
The first gate driver 431 causes the gate voltage of the power switching device to be in a floating state,
The second gate driver 432 shuts off an AMOLED driving power IC, wherein a high voltage is applied to a gate voltage of the transfer switching device so that the transfer switching device is turned off. Synchronous step-up converter circuit that implements switching voltage limit on down. The method of claim 1,
And a capacitor Cout 440 connected to the output node N2 for charging a charge corresponding to the output voltage Vout, and a load resistor R _load 450 for receiving the output voltage Vout. A synchronous step-up converter circuit that implements a switching voltage limit during shutdown of an AMOLED driving power IC.

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