KR20120005943A - Semiconductor memory device and operation method thereof - Google Patents

Abstract

The present invention provides a method for inputting data into page buffers; Comparing the number of data with a set number; As a result of the comparison, if the number of data is less than the set number, the data input to the page buffers are inverted and a program operation is performed on the selected memory cells according to the inverted data, and the number of data A first program step of performing a program operation on the selected memory cells according to the data when the number is equal to or larger than the set number; Storing data corresponding to a program voltage when a threshold voltage of at least one memory cell reaches a target level when performing the first program step, in a flag cell; And a second program step of performing a program operation by using a program voltage selected according to data corresponding to the flag cell as a start program voltage during a next program operation.

Description

Semiconductor memory device and operating method thereof

The present invention relates to a semiconductor memory device and a method of operating the same, and more particularly, to a nonvolatile memory device and a program method thereof.

The nonvolatile memory device includes a memory cell array in which data is stored, and the memory cell array is composed of a plurality of cell strings. Each cell string consists of a drain select transistor, a source select transistor, and a plurality of memory cells connected in series with each other between the drain select transistor and the source select transistor. Gates of the drain select transistors included in the different cell strings are connected to the drain select line, and gates of the source select transistors are connected to the source select line. In addition, gates of memory cells included in different cell strings are connected to word lines, respectively.

The program operation of the nonvolatile memory device described above is as follows.

1 is a diagram illustrating a conventional program method, and FIG. 2 is a diagram illustrating a change in threshold voltages of memory cells according to the program method of FIG. 1.

The program operation of the nonvolatile memory device is performed by an incremental step pulse program (ISPP) method in which a program voltage that is gradually increased is applied to the selected word line WL. The ISPP program operation includes a program step of applying a starting program voltage to a selected word line, and a verification step of applying a verification voltage Vf to a selected word line to verify whether a threshold voltage of a programmed memory cell has reached a target level. And repeating the program operation of raising the program voltage Vpgm and applying the elevated program voltage to the selected word line until the threshold voltage reaches the target level (22).

In the ISPP program operation, since the level of the starting program voltage Vpgm applied to the selected word line for the first time is set low, the threshold voltage and the target level of the memory cells are initially applied when the program voltage is applied (12 in FIG. 2). The difference between (Vt in Fig. 2) is large. That is, since the threshold voltage of the memory cells approaches the target level after applying the start program voltage and raising the program voltage several times, the program operation time T20 is unnecessarily longer due to the initial program operations. .

In addition, during a program operation, data of a specific pattern may be programmed in memory cells of a portion of the memory cell array. For example, there may be a case in which memory cells included in two or three strings adjacent to each other are both programmed or maintained in an erased state. Accordingly, there may be a problem that the stored data is changed while a potential difference occurs for each region in the memory cell array.

In order to solve this problem, a method of programming data randomly in a memory cell array has recently been developed. However, in case of random programming, the host should specify data for all columns. If there is an unspecified column, an error may occur in random operation during program or read operation, and unexpected data may be programmed or read. Can be.

The problem to be solved by the present invention, when the program operation of the ISPP method, if the number of the memory cells of the memory cells included in the selected page reaches the target level reaches the set number of the corresponding program voltage of the subsequent program operation By setting the start voltage, the program operation time is shortened.

A method of operating a semiconductor memory device according to an embodiment of the present disclosure may include performing a low bit program operation on selected memory cells while increasing a program voltage; If the threshold voltages of some of the selected memory cells reach a target level, storing data corresponding to a corresponding program voltage in a first flag cell; Performing a low bit program operation on the memory cells whose threshold voltages do not reach the target level until the threshold voltages of the selected memory cells reach the target level; And when the lower bit program operation is completed, performing a higher bit program operation of the selected memory cells by using a program voltage set according to data stored in the first flag cell as a start program voltage.

In another aspect of the present disclosure, a method of operating a semiconductor device includes performing a low bit program operation of an even page included in a first page, wherein a threshold voltage of a part of memory cells to be programmed reaches a target level. Storing first data corresponding to the in a flag cell; Performing a remaining program operation of the first page using a start program voltage set according to the first data when the threshold voltages of the memory cells included in the even page reach the target level; Selecting a second page when all program operations of the first page are completed; Performing a lower bit program operation of an even page in the second page, and storing second data corresponding to a program voltage when a threshold voltage of some of the memory cells to be programmed reaches a target level in a flag cell; And when the threshold voltages of the memory cells included in the even page of the second page reach the target level, performing the remaining program operation of the second page using the start program voltage set according to the second data. A method of operating a semiconductor memory device comprising the step.

In an embodiment, a semiconductor device may include a memory cell array in which data is stored; Page buffers connected to the memory cell array through bit lines and to which program data is input; A fail bit counter that counts the program data; And comparing the counting result with a set number, and if the number of data to be programmed is less than the set number, inverts the program data stored in the page buffers and performs a program operation according to the inverted data, or And a control circuit for maintaining the program data stored in the page buffers and controlling the page buffers according to the retained data if the number of data to be performed is equal to or larger than the set number.

According to the present invention, the program operation time can be shortened by setting the optimum program start voltage for each page.

1 is a view for explaining a program method according to the prior art.
FIG. 2 is a diagram illustrating a change in threshold voltages of memory cells according to the program method of FIG. 1.
3 is a block diagram of a semiconductor memory device for performing a program operation according to the present invention.
4 is a flowchart illustrating a program method using the semiconductor memory device of FIG. 3.
5 and 6 are flowcharts illustrating the program method of FIG. 4 in detail.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided for complete information.

3 is a block diagram of a semiconductor memory device for performing a program operation according to the present invention.

Referring to FIG. 3, a semiconductor memory device according to an embodiment of the inventive concept may include an operation circuit group 130 configured to perform a program operation or a read operation of a memory cell array 110 and memory cells included in the memory cell array 110. 140, 150, 160, 170, 180, and the operation circuit group 130, 140, for setting the threshold voltage levels of the selected memory cells to one of an erase level and one of five program levels according to the input data. Control circuitry 120 configured to control 150, 160, 170, 180.

In the case of a NAND flash memory device, the operation circuit group includes the voltage generation circuit 130, the row decoder 140, the page buffer group 150, the column select circuit 160, the input / output circuit 170, and the fail bit counter 180. ).

The memory cell array 110 includes a plurality of memory blocks. 3 shows one memory block among them. Each memory block includes a plurality of strings ST1 through STk. Some of the strings ST1 through STk are designated as normal strings, and some are defined as flag strings. Each string is configured identically to each other, and each string ST1 is connected to a source select transistor SST, a plurality of memory cells Ca0 to Can, and a bit line BL1 that are connected to a common source line CSL. The drain select transistor DST is connected. The cells included in the flag string are called flag cells, but the structure is the same as that of the memory cells. The gate of the source select transistor SST is connected to the source select line SSL, the gates of the memory cells Ca0 to Can are respectively connected to the word lines WL0 to WLn, and the gate of the drain select transistor DST. Is connected to the drain select line DSL. The strings ST1 to STk are respectively connected to the corresponding bit lines BL1 to BLk and commonly connected to the common source line CSL.

The control circuit 120 internally outputs the program operation signal PGM, the read operation signal READ, or the erase operation signal ERASE in response to the command signal CMD, and according to the type of operation, the page buffer group 150. ) Outputs control signals PB SIGNALS for controlling the page buffers included in. In addition, the control circuit 120 internally outputs the row address signal RADD and the column address signal CADD in response to the address signal ADD. The control circuit 120 checks whether the threshold voltages of the selected memory cells have increased to the target voltage according to the pass / fail signal PFS output from the fail bit counter 180 during the program verify operation, and according to the check result, Determine whether to rerun or complete. In particular, during a program operation, the control circuit 120 receives the counting result CS transmitted from the fail bit counter 180, compares the number of program data according to the counting result CS with a set number, and then compares the result. According to the determination whether to invert or maintain the data stored in the page buffer group 150, and outputs the page buffer signals (PB SIGNALS) according to the determination result.

The voltage supply circuits 130 and 140 select drain voltages of the selected memory block in response to the signals READ, PGM, ERASE, and RADD of the control circuit 120. The line DSL is supplied to the word lines WL0 to WLn and the source select line SSL. This voltage supply circuit includes a voltage generator circuit 130 and a row decoder 140.

The voltage generation circuit 130 outputs operating voltages for programming, reading, or erasing memory cells as global lines in response to the operation signals PGM, READ, and ERASE, which are internal command signals of the control circuit 120, When programming memory cells, operating voltages (eg, Vpgm, Vpass, and Vread) for programming are output as global lines.

In response to the row address signals RADD of the control circuit 120, the row decoder 140 may generate operating voltages generated by the voltage generation circuit 130 of the selected memory block of the memory blocks of the memory cell array 110. Transfer to the strings ST1 to STk. That is, operating voltages are applied to local lines DSL, WL [n: 0], SSL of the selected memory block.

The page buffer group 150 includes page buffers (not shown) connected to the bit lines BL1 to BLk, respectively. In response to the control signals PB SIGNALS of the control circuit 120, voltages necessary for storing data in the cells Ca0,..., Ck0 are applied to the bit lines BL1 to BL4, respectively. In detail, the page buffer group 150 may precharge the bit lines BL1 to BLk or may precharge the bit lines BL1 to BLk during the program operation, the erase operation, or the read operation of the cells Ca0,..., Ck0. Latches data corresponding to the threshold voltage levels of the detected memory cells Ca0,..., Ck0 according to the change in voltage. That is, the page buffer group 150 adjusts the voltages of the bit lines BL1 through BLk according to data stored in the memory cells Ca0,..., Ck0, and controls the memory cells Ca0,..., Ck0. Detects data stored in).

The column select circuit 160 selects the page buffers included in the page buffer group 150 in response to the column address signal CADD output from the control circuit 120. The latched data of the page buffer selected by the column select circuit 160 is output.

The input / output circuit 170 transfers data to the column selection circuit 160 under control of the control circuit 120 to input data input from the outside into the page buffer group 150 during a program operation. When the column selection circuit 160 transfers the transferred data to the page buffers of the page buffer group 150 in order, the page buffers store the input data in an internal latch. In addition, during the read operation, the input / output circuit 170 outputs data transferred through the column select circuit 160 from the page buffers of the page buffer group 150 to the outside.

The fail bit counter 180 checks whether an error cell having a threshold voltage lower than a target voltage occurs among the programmed memory cells in the program verifying operation performed after the program operation, and outputs the result as a pass / fail signal PFS. In addition, the fail bit counter 180 counts the number of error cells generated when an error cell occurs and outputs a counting result CS. In particular, during the program operation, the fail bit counter 180 counts '0' data among the data received from the column selection circuit 160, and counts the counting result CS output as a result to the control circuit 120. To pass.

In particular, in the present invention, during the program operation, data input to the input / output circuit 170 is transmitted to the page buffer 150 through the column select circuit 160, and the data transmitted to the page buffer 150 is stored in the column select circuit ( It is transmitted to the fail bit counter 180 through 160. The fail bit counter 180 counts the number of '0' data among the transferred data, and transmits the result CS to the control circuit 120. The control circuit 120 inverts the data stored in the page buffer group 150 when the number of '0' data, which is the counting result CS, is smaller than the set number. Keep your data. As such, after performing the operation of inverting or maintaining the data of the page buffer group 150, the control circuit 120 transmits the data stored in the page buffer group 150 to the bit lines BL1 to BLk. Allow program operations to be performed.

4 is a flowchart illustrating a program method using the semiconductor memory device of FIG. 3.

When the program operation starts, the program page is selected (step A01), and the low-bit program data of the selected page is input to the page buffer (step A02). In accordance with the program data input to the page buffer, it is determined whether the number of bits in which the program operation is to be performed is smaller than the set number of bits (step A03). In this case, the set number of bits is set to be 1/2 or more of the total number of bits of the selected page, and is preferably set to 50% to 60%. This is because the number of bits for determining the program start voltage must be representative. For example, if the total number of bits of the selected page is 100, and if the number of bits to be programmed is 2, the representative value is lowered when applied to the remaining 82 bits as a result value for the two bits. In addition, since it is determined whether the program data is inverted and the program operation is performed according to the result, it is possible to replace the program operation at random.

In step A03, if the number of bits to be programmed is equal to or greater than the set number of bits, the voltage of each bit line is set according to the program data input to the page buffer (step A06). Specifically, if the program data is '0', the corresponding bit line is discharged. If the program data is '1', the corresponding bit line is precharged to the program prohibition voltage level (power supply voltage level).

In step A03, if the number of bits to be programmed is less than the set number of bits, the program data of the selected page is inverted (step A04). Specifically, the program data input to the page buffer is inverted. In other words, when '0' is input to the first latch of the page buffer, it is inverted to be '1'. As such, when the number of bits to be programmed is smaller than the set number of bits, inverting the number of bits to be programmed and the number of bits to be prohibited to program are interchanged with each other, so that the number of bits to be programmed is representative.

In particular, when the program data is inverted, the information about the program data is stored in the flag cell of the corresponding page, and the selected page can be read according to the data stored in the flag cell during the read operation. The flag cell is programmed by performing a low bit program and a high bit program operation. The voltages of the bit lines are set according to the inverted program data (step A05).

A low-bit program operation is performed by applying a program voltage to a word line connected to the selected page (step A07). Since the program operation is performed by an incremental step pulse program (ISPP) method of gradually increasing the program voltage applied to the selected word line, the start program voltage is applied to the selected word line when the step A07 is first performed. At this time, the start program voltage is applied to a preset start program voltage.

The number of memory cells whose threshold voltage reaches the target level is counted, and it is determined whether the number of counted memory cells is less than the set number (step A08). In this case, the number of memory cells to be set may be set differently according to the memory device. For example, the number of memory cells may be set within 5% of the number of memory cells of the selected page or one of them may be set. That is, it may be determined whether at least one or more memory cells whose threshold voltage reaches the target level have occurred (step A08). If the threshold voltage is less than the set number of the memory cells to reach the target level, the program voltage is increased (step A09) and the increased program voltage is applied to the selected word line to repeat the program operation (step A07). The threshold voltage of the memory cells to be programmed in the page is increased.

When the number of memory cells having reached the target level is equal to or greater than the set number, the data corresponding to the corresponding program voltage is stored in the flag cell (step A10). The flag cell at this time is a cell different from the flag cell in which the inversion information of the program data is stored. That is, data about a program voltage having a raised level is stored in a flag cell included in the selected page. For example, the flag cells are also programmed at various levels, and data corresponding to the respective levels and the rising program voltages can be converted into data. The stored data is used to set the start program voltage in subsequent program operations. In addition, if the data for the level of the start program voltage is stored in the flag cell, it is set up to set the start program voltage using the stored data in a subsequent higher bit program operation.

The low-bit program operation of the remaining memory cells included in the selected page is performed (step A11). It is determined whether the lower bit program of the selected page is completed (step A12). If it is not completed, the lower bit program operation of the remaining memory cells is performed while gradually raising the program voltage (step A11).

When the low bit program operation of the selected page is completed, the high bit program operation of the selected page is performed. The higher bit program operation of the selected page is performed using the start program voltage set according to the data stored in the flag cells of the selected page (step A13). In this case, since the set start program voltage is a program voltage when the threshold voltages of the majority of the memory cells included in the selected page start reaching the target level, the threshold voltage of the memory cells may be increased in a short time during the upper bit program operation of the selected page. have. In addition, since the set start program voltage may be high, an offset may be given to lower the level of the set start program voltage slightly. That is, when a start program voltage of too high level is applied to the memory cells to be programmed from the beginning, the memory cells may be stressed, and thus the start program voltage may be reset to 0.2V to 0.5V lower than the set start program.

It is determined whether the upper bit program of the selected page is completed, and if it is not completed, the higher bit program operation is repeatedly performed while gradually raising the program voltage (step A13). If it is determined in step A14 that the higher bit program operation of the selected page is completed, it is determined whether the programs of all the pages in the selected memory block are completed (step A15).

As a result of the determination, if the program of all pages is not completed, the next page is selected until the program operation of all pages is completed (step A16) to perform the above-described low bit program operation and high bit program operation. During the program operation of all pages, the start program voltage of each page is set to set the start program voltage for each page. That is, since the programming speed of the memory cells included in each page is different, setting a start program voltage for each page and performing a program operation using the set start program voltage can shorten the time required for the overall program operation.

In addition, one page may be divided into an even page and an odd page, and their program operations may be performed. Specifically, it is as follows.

5 and 6 are flowcharts illustrating the program method of FIG. 4 in detail.

Referring to FIG. 5, the operation of a lower bit program of an even page is as follows. When the program operation starts, the low-bit program data of the even page is input to the page buffer (step B01). It is determined whether the number of bits for performing the program operation is smaller than the set number of bits according to the program data input to the page buffer (step B02). In this case, the set number of bits is set to be 1/2 or more of the total number of bits of the selected page, and is preferably set to 50% to 60%. This is because the number of bits for determining the program start voltage must be representative. For example, if the total number of bits of the selected page is 100, but there are only two bits to be programmed, the representativeness is lowered when applied to 100 with only the results for the two bits.

In step B02, if the number of bits to be programmed is equal to or greater than the set number of bits, the voltage of each bit line is set according to the program data input to the page buffer (step B05). In detail, if the program data is '0', the corresponding bit line is discharged. If the program data is '1', the corresponding bit line is precharged to the program inhibit voltage.

In step B02, if the number of bits to be programmed is less than the set number of bits, the program data of the selected page is inverted (step B03). Specifically, the program data input to the page buffer is inverted. In other words, when '0' is input to the first latch of the page buffer, it is inverted to be '1'. As such, when the number of bits to be programmed is smaller than the set number of bits, inverting the number of bits to be programmed and the number of bits to be prohibited to program are interchanged with each other, so that the number of bits to be programmed is representative.

In particular, when the program data is inverted, the information about the program data is stored in the flag cell of the corresponding page, and the selected page can be read according to the data stored in the flag cell during the read operation. The voltage of the bit lines is set according to the inverted program data (step B04).

The program operation is performed by applying a program voltage to the word line connected to the selected page (step B06). Since the program operation is performed in an Imcremental Step Pulse Program (ISPP) method of gradually increasing the program voltage applied to the selected word line, the start program voltage is applied to the selected word line when the step B06 is first performed. At this time, the start program voltage is applied to the start program voltage preset in the control circuit.

The number of memory cells whose threshold voltage reaches the target level is counted, and it is determined whether the number of counted memory cells is less than the set number (step B07). In this case, the number of memory cells to be set may be set differently according to the memory device. For example, the set number of memory cells is set to be within 5% of the number of memory cells of an even page. If the threshold voltage is less than the set number of memory cells to reach the target level, the program voltage is increased (step B08), and the program operation (step B06) is repeatedly performed by applying the increased program voltage to the selected word line. The threshold voltage of the memory cells to be programmed in the page is increased.

If the number of memory cells whose threshold voltage reaches the target level is equal to or larger than the set number, data corresponding to the corresponding program voltage is stored in the flag cell (step B09). That is, data about a program voltage having a raised level is stored in a flag cell included in the selected page. For example, the flag cells are also programmed at various levels, and data corresponding to the respective levels and the rising program voltages can be converted into data. The stored data is used to set the start program voltage in subsequent program operations. This will be described later.

In order to perform the lower bit program operation of the remaining memory cells included in the even page (step B10), the program voltage is increased to the selected word line to perform the remaining lower bit program operation of the even page. (Step B11). It is determined whether the low bit program of the even page is completed (step B12). If not, the threshold voltages of the memory cells included in the even page may reach the target level while gradually increasing the program voltage (step B10). The low bit program operation of the remaining memory cells is repeatedly performed in the even page until the operation (steps B10 to B12).

As described above, in the first program operation of the selected page (for example, the lower bit program operation of the even page), the process of finding the optimum starting program voltage is performed, and thus, the program operation time is not shortened. However, the program operation time can be shortened by finding the optimal starting program voltage in the first program operation and using it for the next program operation in the corresponding page.

Referring to FIG. 6, as described with reference to FIG. 5, if data for a start program is stored in a first program operation of a selected page, the set start is performed in a remaining higher bit program of an even page, a lower bit of an odd page, and an upper bit program operation. Perform a program operation using the program voltage.

Referring to FIG. 6, the upper bit program operation of an even page is described as follows.

When the program operation is started, the upper bit program voltage is set according to the data stored in the flag cell during the low bit program operation of the even page (step C01). The set start program voltage is applied to a word line connected to an even page (selected page) (step C02). In this case, since the set start program voltage is set higher than the start program voltage of the lower bit program operation of the even page, the threshold voltage of memory cells to be programmed may be quickly increased during the upper bit program operation of the even page. It is determined whether all threshold voltages of the selected memory cells have reached the target level (step C03). As a result of the determination, if there is a memory cell whose threshold voltage does not reach the target level, the program voltage is increased (step C04), and when the threshold voltage of all the memory cells reaches the target level by applying the increased program voltage to the selected word line. The steps 'C02', 'Step C03' and 'Step C04' are repeated until now.

Referring to FIG. 6, the low-bit program operation of an odd page is described as follows.

When the program operation is started, the upper bit program voltage is set according to the data stored in the flag cell during the low bit program operation of the even page (step C01). The set start program voltage is applied to a word line connected to an odd page (selected page) (step C02). At this time, since the even and odd pages are connected to the same word line, the selected word line is the same as the program operation of the even page. Since the set start program voltage is set higher than the start program voltage of the low bit program operation of the even page, the threshold voltage of the memory cells to be programmed may be quickly increased during the low bit program operation of the odd page. It is determined whether all threshold voltages of the selected memory cells have reached the target level (step C03). As a result of the determination, if there is a memory cell whose threshold voltage does not reach the target level, the program voltage is increased (step C04), and when the threshold voltage of all the memory cells reaches the target level by applying the increased program voltage to the selected word line. The steps 'C02', 'Step C03' and 'Step C04' are repeated until now.

Referring to FIG. 6, the upper bit program operation of the odd page will be described.

When the program operation is started, the upper bit program voltage is set according to the data stored in the flag cell during the low bit program operation of the even page (step C01). The set start program voltage is applied to a word line connected to an odd page (selected page) (step C02). At this time, since the set start program voltage is set higher than the start program voltage of the lower bit program operation of the even page, the threshold voltage of the memory cells to be programmed may be quickly increased during the upper bit program operation of the odd page. It is determined whether all threshold voltages of the selected memory cells have reached the target level (step C03). As a result of the determination, if there is a memory cell whose threshold voltage does not reach the target level, the program voltage is increased (step C04), and when the threshold voltage of all the memory cells reaches the target level by applying the increased program voltage to the selected word line. The steps 'C02', 'Step C03' and 'Step C04' are repeated until now.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention.

110: memory cell array 120: control circuit
130: voltage generation circuit 140: low decoder
150: page buffer group 160: column selection circuit
170: input / output circuit 180: pass / fail determination circuit

Claims (18)

Performing a low bit program operation on selected memory cells while raising a program voltage;
If the threshold voltages of some of the selected memory cells reach a target level, storing data corresponding to a corresponding program voltage in a first flag cell;
Performing a low bit program operation on the memory cells whose threshold voltages do not reach the target level until the threshold voltages of the selected memory cells reach the target level; And
When the lower bit program operation is completed, performing a higher bit program operation of the selected memory cells using a program voltage set according to data stored in the first flag cell as a start program voltage. . The method of claim 1,
Performing the low bit program operation of the selected memory cells,
Applying a program voltage to a word line connected to the selected memory cells; And
And performing a program operation while gradually increasing the program voltage until memory cells having a threshold voltage reaching the target level occur. The method of claim 1,
The storing of the data corresponding to the corresponding program voltage in the first flag cell may include storing data corresponding to the program voltage when the threshold voltage reaches the set number of memory cells that reach the target level. A method of operating a semiconductor memory device. The method of claim 3,
And setting the set number within one or less than 5% of the selected memory cells. The method of claim 4, wherein
And the first flag cell is programmed by performing a low bit program and a high bit program operation. The method of claim 1,
The higher bit program operation may use the start program voltage set according to the data stored in the first flag cell as it is, or reset the start program voltage by 0.2V to 0.5V lower than the set start program voltage. Method of operation. The method of claim 1,
Before performing the low bit program operation of the memory cells to be included in the selected page,
Inputting program data of the memory cells to be programmed into page buffers corresponding to the respective memory cells, and determining whether the number of bits to be programmed is less than the set number of bits according to the page buffers;
If the number of bits to be programmed is equal to or greater than the set number of bits, setting voltages of bit lines corresponding to the memory cells according to the program data; And
If the number of bits to be programmed is less than the set number of bits, inverting the program data stored in the page buffer and setting a voltage of the bit lines according to the inverted program data. Method of operation. The method of claim 7, wherein
And inverting the program data stored in the page buffer, and storing information about the program data in a second flag cell included in the selected page. The method of claim 8,
And setting a voltage level to be used in a subsequent program operation according to the information stored in the second flag cell. The method of claim 8,
And a read operation according to the information stored in the second flag cell. The method of claim 1,
And after the upper bit program operation of the page including the selected memory cells is completed, determining whether the program operation of all the pages to be programmed is completed. The method of claim 11,
If a program operation of all the pages to be programmed is not completed, selecting a next page and performing a lower bit program operation of the selected next page to set a start program voltage of an upper bit program operation; Method of operation. Performing a low bit program operation of an even page included in a first page, and storing first data corresponding to a program voltage when a threshold voltage of some of the memory cells to be programmed reaches a target level in a flag cell;
Performing a remaining program operation of the first page using a start program voltage set according to the first data when the threshold voltages of the memory cells included in the even page reach the target level;
Selecting a second page when all program operations of the first page are completed;
Performing a lower bit program operation of an even page in the second page, and storing second data corresponding to a program voltage when a threshold voltage of some of the memory cells to be programmed reaches a target level in a flag cell; And
When the threshold voltages of the memory cells included in the even page of the second page reach the target level, performing the remaining program operation of the second page using the start program voltage set according to the second data. Method of operating a semiconductor memory device comprising a. The method of claim 13,
Performing the remaining program operation of the first page,
Performing an upper bit program operation of the even page included in the first page by using a start program voltage set according to the first data;
Performing a lower bit program operation of an odd page included in the first page by using the set start program voltage when the upper bit program operation of the even page is completed; And
And performing a higher bit program operation of the odd page using the set start program voltage when the lower bit program operation of the odd page is completed. The method of claim 13,
Before performing the low bit program operation of the even page included in the first page,
Inputting program data of memory cells to be programmed in the even page included in the first page into page buffers corresponding to the respective memory cells, and determining whether the number of bits to be programmed according to the page buffers is less than a set number of bits; ;
If the number of bits to be programmed is equal to or greater than the set number of bits, setting voltages of bit lines corresponding to the memory cells according to the program data; And
If the number of bits to be programmed is less than the set number of bits, inverting the program data stored in the page buffer and setting a voltage of the bit lines according to the inverted program data. Method of operation. A memory cell array in which data is stored;
Page buffers connected to the memory cell array through bit lines and to which program data is input;
A fail bit counter that counts the program data; And
By comparing the counting result with a set number, if the number of data to be programmed is less than the set number, the program data stored in the page buffers are inverted and then a program operation is performed according to the inverted data, or And a control circuit for maintaining the program data stored in the page buffers and controlling the page buffers according to the retained data if the number of data is equal to or larger than the set number. The method of claim 16,
And the set number is set to a number greater than 1/2 or 1/2 of the total number of bits of the selected page. The method of claim 16,
The set number is set to 50% to 60% of the total number of bits of the selected page during the program operation.

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