KR20110117511A - Seaoji type array board - Google Patents

Abstract

The present invention provides a display device comprising: a substrate in which a display area having a plurality of pixel areas and a non-display area having a gate driving circuit portion around the pixel area are defined; A gate wiring and a data wiring crossing the display region on the substrate to define the pixel region; A switching thin film transistor connected to the gate and the data line in each pixel area; A plurality of driving thin film transistors having the same structure as the switching thin film transistor in the gate driving circuit part; A pixel electrode formed in each pixel region in contact with the drain electrode of the switching thin film transistor; A first passivation layer formed over the pixel electrode on the entire surface of the substrate and having a first thickness; A common electrode having a plurality of bar-shaped first openings disposed on the entire surface of the display area over the first passivation layer and spaced apart from each other by a predetermined interval; And a plurality of driving storage capacitors connected to the plurality of driving thin film transistors in the switching region, wherein each of the plurality of driving storage capacitors is formed of the same material on the same layer where the pixel electrode is formed and the first electrode. Provided is an array substrate comprising a second electrode made of the same material on the same layer where the protective layer and the common electrode are formed.

Description

Chip on glass type array substrate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate for a liquid crystal display device, and more particularly, to reduce the area of a plurality of capacitors formed to facilitate driving of a display area in a driving circuit part provided in a non-display area for implementing a gate driver. The present invention relates to an array substrate for a fringe field switching mode liquid crystal display device in which the capacitor capacity is unchanged or increased as compared with the related art even though the area is reduced.

Recently, as the information society has developed rapidly, the necessity of a display device having excellent characteristics such as thinning, light weight, and low power consumption has emerged. Accordingly, development of flat panel displays has been actively conducted. In particular, liquid crystal displays are excellent in resolution, color display, image quality, and the like, and are being actively applied to monitors of notebook computers and desktop computers.

In general, a liquid crystal display device arranges two substrates on which electrodes are formed so that the surfaces on which the two electrodes are formed face each other, injects a liquid crystal material between the two substrates, and applies a voltage to the two electrodes to generate an electric field. By moving the liquid crystal molecules, the image is expressed by the transmittance of light that varies accordingly.

In more detail, the structure thereof will be described with reference to FIG. 1, which is an exploded perspective view of a general liquid crystal display. As shown, the liquid crystal display includes an array substrate 10 and a color filter with a liquid crystal layer 30 therebetween. The substrate 20 has a configuration in which the substrates are face-to-face bonded to each other. The array substrate 10 of the lower part of the plurality of gate wirings 14 is vertically and horizontally arranged on the upper surface of the transparent substrate 12 to define a plurality of pixel regions P. And a data line 16, and a thin film transistor T is provided at an intersection point of the two lines 14 and 16 so as to be connected one-to-one with the pixel electrode 18 provided in each pixel region P. FIG.

In addition, the upper color filter substrate 20 facing the array substrate 10 is a rear surface of the transparent substrate 22, and the non-display of the gate wiring 14, the data wiring 16, the thin film transistor T, and the like. A grid-like black matrix 25 is formed around the pixel region P so as to cover the region, and red (R) and green are sequentially arranged in order to correspond to the pixel region (P) in the grid. A color filter layer 26 including (G) and blue (B) color filter patterns 26a, 26b, and 26c is formed, and is transparent over the entire surface of the black matrix 25 and the color filter layer 26. The common electrode 28 is provided.

Although not shown in the drawings, each of the two substrates 10 and 20 is sealed with a sealant or the like along the edge to prevent leakage of the liquid crystal layer 30 interposed therebetween. 10 and 20 are interposed between upper and lower alignment layers that provide reliability in the molecular alignment direction of the liquid crystal at a boundary portion of the liquid crystal layer 30, and at least one outer surface of each substrate 10 and 20 is provided with a polarizing plate. have.

In addition, a back-light is provided on the outer surface of the array substrate 10 to supply light, and the on / off signal of the thin film transistor T is transmitted to the gate wiring 14. When the image signal of the data wiring 16 is transferred to the pixel electrode 18 of the selected pixel region P by being sequentially scanned and applied, the liquid crystal molecules are driven by the vertical electric field therebetween, and thus the transmittance of light We can display various images by change

In the liquid crystal display device having such a structure, the array substrate, the color filter substrate, and the liquid crystal layer interposed between the two substrates are defined as a liquid crystal panel, and a driving unit for driving the liquid crystal panel is formed on the outer side of the liquid crystal panel.

The driving unit is a printed circuit board (PCB) on which components generating various control signals, data signals, etc. are mounted, and a driving integrated device connected to the liquid crystal panel and the printed circuit board and applying a signal to the wiring of the liquid crystal panel. And a drive IC, comprising a chip on glass (COG) method, a tape carrier package (TCP) method, and the like, according to a method of packaging a driving integrated circuit on the liquid crystal panel. It is divided into a chip on film (COF) method.

The dual COG method has been widely applied to liquid crystal display devices in recent years because the structure is simpler than the TCP method and the COF method, and the ratio of the display area of the liquid crystal panel to the liquid crystal display device can be increased.

FIG. 2 is a plan view showing a portion of a gate driving circuit provided in a non-display area of a conventional array substrate for a liquid crystal display device, and FIG. 3 is a cross-sectional view of a portion cut along the cutting line III-III of FIG. 2.

The gate driving integrated circuit unit reliably applies a smooth scan signal to a plurality of clock signal wires, drive wires for applying Vss, Vdd, and Vst, a plurality of driving thin film transistors selectively connected to the drive wires, and gate wires in the display area. First, second, and third drive storage capacitors are provided for the purpose.

In this case, each of the first, second, and third driving storage capacitors may include a first storage storage capacitor first electrode formed of the same metal material having the gate electrode and the wiring formed on the gate electrode and the gate wiring formed in the display area, and the dielectric layer. The interlayer insulating film and the same metal material constituting the data line provided in the display area are respectively formed of the driving storage capacitor second electrode.

In this case, the interlayer insulating layer is generally formed to have a thickness of 5000 kΩ or more as an inorganic insulating material due to the problem of load increase and power consumption increase due to the influence of parasitic capacitance. Since an insulating film is used as the dielectric layer, the insulating film is formed over a specific area to secure a capacitor capacity for smooth and stable scan signal supply.

On the other hand, in developing a high resolution model, it is inevitable to reduce the area of the gate driving circuit unit GDA formed in the non-display area of the array substrate. Accordingly, the margin of the separation distance of each wiring inside the gate driving circuit unit (GDA) is minimized, and the channel forming unit is also designed to the minimum level to secure device reliability, but stably outputs the scan signal. To this end, the first, second, and third driving storage capacitors must be formed to have an area of a predetermined level or more, and thus, there is a limit in reducing the driving circuit unit GDA.

An object of the present invention is to provide an array substrate for a liquid crystal display device of the COG type that can reduce the area without reducing the capacity of the first, second, third drive storage capacitor provided in the gate driving circuit portion.

An array substrate according to the present invention includes a substrate in which a display area having a plurality of pixel areas and a non-display area having a gate driving circuit part around the substrate are defined; A gate wiring and a data wiring crossing the display region on the substrate to define the pixel region; A switching thin film transistor connected to the gate and the data line in each pixel area; A plurality of driving thin film transistors having the same structure as the switching thin film transistor in the gate driving circuit part; A pixel electrode formed in each pixel region in contact with the drain electrode of the switching thin film transistor; A first passivation layer formed over the pixel electrode on the entire surface of the substrate and having a first thickness; A common electrode having a plurality of bar-shaped first openings disposed on the entire surface of the display area over the first passivation layer and spaced apart from each other by a predetermined interval; And a plurality of driving storage capacitors connected to the plurality of driving thin film transistors in the switching region, wherein each of the plurality of driving storage capacitors is formed of the same material on the same layer where the pixel electrode is formed and the first electrode. A second electrode made of the same material is formed on the same layer where the protective layer and the common electrode are formed.

At this time, the first thickness is characterized in that 1000 ~ 2000Å.

A second passivation layer covering the switching and driving thin film transistors and having a drain contact hole exposing the drain electrode of the switching thin film transistor on the front surface of the substrate is formed, and the first of each of the pixel electrode and the plurality of driving storage capacitors. An electrode is formed on the second passivation layer, and the pixel electrode contacts the drain electrode of the switching thin film transistor through the drain contact hole.

The first protective layer is made of silicon oxide (SiO 2) or silicon nitride (SiN x), which is an inorganic insulating material.

The switching and driving thin film transistors may include a semiconductor layer having a semiconductor layer, a gate insulating layer, a gate electrode and a semiconductor layer contact hole exposing the semiconductor layer, and the semiconductor layer through the semiconductor layer contact hole, respectively. And source and drain electrodes in contact and spaced apart from each other. In this case, the semiconductor layer includes a first region of pure polysilicon and a second region of polysilicon doped with impurities on both sides of the first region, and the gate electrode is formed corresponding to the first region. The semiconductor layer contact hole may expose the second region.

In addition, each of the plurality of driving thin film transistors may be connected to a gate electrode, a source electrode, and a drain electrode, which selectively constitute a driving thin film transistor, respectively, or may be connected through a plurality of auxiliary wirings, or may be connected to the plurality of driving storage capacitors. In this case, any one of the plurality of driving thin film transistors is connected to the gate line.

In addition, the non-display area includes a plurality of driving signal wirings connected to one electrode of the plurality of driving thin film transistors.

The plurality of auxiliary wires may be formed on the interlayer insulating film or the gate insulating film, and the plurality of contact holes may be provided on the interlayer insulating film and the gate insulating film to expose one electrode of the plurality of driving thin film transistors. The plurality of auxiliary wires are electrically connected to each electrode of the plurality of driving thin film transistors through contact holes of the plurality of auxiliary thin films.

The common electrode may have a second opening corresponding to the switching thin film transistor.

In the array substrate for a COG type liquid crystal display device according to the present invention, an insulating layer having a thickness of about 1000 GPa to 2000 GPa disposed between the pixel electrode and the common electrode is used as the dielectric layer, and the first, second, third, and fourth gate driver circuit portions. By forming the driving storage capacitor, the area of the gate driving circuit is reduced by reducing the area without reducing the capacity.

By reducing the area of the gate driving circuit part provided in the non-display area, and instead of increasing the area of the display area, it is possible to improve the substrate utilization rate, thereby reducing the product manufacturing cost and improving the price competitiveness.

As the bezel width of the non-display area is reduced, a lightweight compact display device can be realized without changing the size of the display area.

1 is a perspective view of a general liquid crystal display device.
FIG. 2 is a plan view illustrating a portion of a gate driving circuit provided in a non-display area of a conventional liquid crystal display array substrate. FIG.
3 is a cross-sectional view of a portion cut along the cutting line III-III of FIG.
4 is a schematic plan view of a portion of a gate driving circuit portion in an array substrate for a COG type liquid crystal display device according to an embodiment of the present invention;
FIG. 5 is a cross-sectional view of a portion cut along the cutting line VV in FIG. 4. FIG.
6 is a cross-sectional view of one pixel area including a thin film transistor in an array substrate for a COG type liquid crystal display according to an exemplary embodiment of the present invention.
7 is a simplified circuit diagram of a part of a gate driving circuit portion (GDA) in an array substrate for a COG type liquid crystal display device according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 4 is a schematic plan view of a portion of a gate driving circuit in an array substrate for a COG type liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view of a portion cut along the cutting line VV of FIG. 4. FIG. 6 is a cross-sectional view of one pixel area including a thin film transistor in an array substrate for a COG type liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 7 is a diagram for a COG type liquid crystal display according to an exemplary embodiment of the present invention. A simplified circuit diagram of a portion of the gate drive circuitry (GDA) for an array substrate.

First, referring to the driving circuit unit GDA, the first to fourth clock signal wires CLK1, CLK2, CLK3, and CLK4 for transmitting the first to fourth clock signals are provided as shown in FIG. A plurality of driving wirings Vst, Vss, and Vdd are provided for applying various voltages, and are connected to the driving wirings Vst, Vss, and Vdd, and the first to seventh driving thin film transistors TFT1 to TFT7) is provided.

In addition, first to fourth driving storage capacitors C1, C2, C3, and C4 are connected to some of the first to seventh driving thin film transistors TFT1 to TFT7.

In this case, the connection relationship between the first to seventh driving thin film transistors TFT1 to TFT7 and the first to fourth driving storage capacitors C1, C2, C3, and C4 will be described in more detail. The gate electrode and the drain electrode of the driving thin film transistor TFT1 are connected to the Vst wiring, and the drain electrode of the first driving thin film transistor TFT1 is connected to the gate electrode of the fifth driving thin film transistor TFT5.

The second driving thin film transistor TFT2 is connected to and formed with the fourth clock signal line CLK4 and its gate electrode, and the source electrode and the second driving thin film transistor of the first driving thin film transistor TFT1 are formed. The drain electrode of (TFT2) is connected. The drain electrode of the second driving thin film transistor TFT2 is connected to the first electrode of the fourth driving storage capacitor C4, and the source electrode of the second driving thin film transistor TFT2 is connected to the source electrode of the third thin film transistor C2 and the second driving storage capacitor C2. And a gate electrode of the first electrode and the third driving storage capacitor C3 and the sixth driving thin film transistor TFT6.

In this case, the second electrode of the fourth driving storage capacitor C4 is grounded and grounded.

The drain electrode of the third driving thin film transistor TFT3 may have a source electrode of each of the fifth and seventh thin film transistors TFT5 and TFT7 and a first electrode and a second driving storage of the first driving storage capacitor C1, respectively. The gate electrode of the third driving thin film transistor TFT3 is connected to the second electrode of the capacitor C2 and the drain electrode of the fifth driving thin film transistor TFT5 and the gate electrode of the seventh driving thin film transistor TFT7. And a second electrode of the first driving storage capacitor C1 at the same time.

In addition, a gate electrode of the fourth driving thin film transistor TFT4 is connected to the third clock signal line CLK3, and a source electrode of the fourth driving thin film transistor TFT4 is connected to the drain electrode of the fifth driving thin film transistor TFT5. The drain electrode is connected to the first clock signal line CLK1.

In addition, a drain electrode of the sixth driving thin film transistor TFT6 is connected to the first clock signal line CLK1, and a source electrode of the sixth driving thin film transistor TFT6 is connected to the drain electrode of the seventh driving thin film transistor TFT7 and the third driving storage capacitor. It is connected with the 2nd electrode of C3).

In addition to the gate driving circuit unit GDA having the above-described configuration, one pixel region P provided in the display area is provided with a switching thin film transistor Tr as a switching element, and the drain electrode of the switching thin film transistor Tr. A plurality of first openings connected to the second electrode 146 and having a pixel electrode 160 and overlapping the pixel electrode 160 and having a bar shape through an insulating layer (the second protective layer 165). The common electrode 170 having (oa1) is formed.

In more detail, the stacked structure of each pixel area P and the gate driving circuit unit GDA will be described.

Each pixel region P in the display area of the substrate 101 is made of pure polysilicon, and a central portion thereof has a first region 105a forming a channel, and a high concentration of impurities on both sides of the first region 105a. A semiconductor layer 105 composed of this doped second region 105b is formed. In this case, a buffer layer (not shown) made of an inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx) may be further provided between the semiconductor layer 105 and the substrate 101. The buffer layer (not shown) is to prevent deterioration of the characteristics of the semiconductor layer 105 due to the release of alkali ions from the inside of the insulating substrate 101 when the semiconductor layer 105 is crystallized.

In addition, a gate insulating layer 110 is formed on the entire surface of the substrate 101 to cover the semiconductor layer 105. A gate electrode 113 is formed on the gate insulating layer 110 to correspond to the first region 105a of the semiconductor layer 105.

In addition, the gate insulating layer 110 is connected to the gate electrode 113 formed in the pixel region P, extends in one direction, and a plurality of gate wires (not shown) are formed. In this case, the gate electrode 120 and the gate wiring (not shown) is a first metal material having low resistance, for example, aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, molybdenum ( Mo) may be made of any one of the molybdenum (MoTi) may have a single layer structure, or may have a double layer or triple layer structure as two or more metal materials.

In the display area, an interlayer insulating layer 130 having a thickness of about 5000 kV to about 10,000 kPa is formed on the entire surface of the substrate 101 over the gate electrode 120 and the gate wiring (not shown). In this case, each of the second regions 105b disposed on both sides of the first region 105a of the semiconductor layer is exposed to the interlayer insulating layer 130 and the gate insulating layer 110 below the pixel region P. A semiconductor layer contact hole 135 is provided.

Next, an upper portion of the interlayer insulating layer 130 including the semiconductor layer contact hole 135 intersects the gate wiring (not shown) in the display area, and a second metal material such as aluminum (Al) or aluminum alloy ( A data line 140 formed of any one or two or more materials of AlNd), copper (Cu), copper alloy, molybdenum (Mo), molybdenum (MoTi), chromium (Cr), and titanium (Ti) is formed.

In addition, the pixel region P may be spaced apart from each other on the interlayer insulating layer 130, and may contact the second region 105b exposed through the semiconductor layer contact hole 135, respectively. Source and drain electrodes 143 and 146 made of the same material are formed. In this case, the semiconductor layer 105 including the source and drain electrodes 143 and 146 formed in the driving region DA, and the second region 105b in contact with the two electrodes 143 and 146, respectively. The gate insulating layer 110 and the gate electrode 113 formed on the semiconductor layer 105 form a switching thin film transistor Tr.

In the drawing, the data line 140 and the source and drain electrodes 143 and 146 all have a single layer structure, but these components may have a double layer or triple layer structure.

On the other hand, the gate driving circuit part GDA includes a plurality of first auxiliary wirings (not shown) on the gate insulating layer 110, and has the same stacked structure as the switching thin film transistor Tr, and has a first structure as a driving element. To seventh driving thin film transistors TFT1 to TFT7. Further, the interlayer insulating layer 130 and the gate insulating layer 110 are formed at the ends of the plurality of first auxiliary wirings (not shown) or the first to seventh driving. A plurality of first auxiliary wirings (not shown) or first contact holes (not shown) for selectively exposing each of the electrodes are provided to correspond to the gate electrodes, the source electrodes, and the drain electrodes of the thin film transistors TFT1 to TFT7. Selectively and electrically connecting each electrode of the first to seventh driving TFTs TFT1 to TFT7 through the plurality of first contact holes (not shown) on the interlayer insulating layer 130. A plurality of second auxiliary wirings (not shown) are provided. At this time, since the connection relationship between the electrodes of the first to seventh driving TFTs TFT1 to TFT7 has been described above through a circuit diagram, a detailed description thereof will be omitted.

Next, a first passivation layer 155 is formed on the entire surface of the substrate 101 on the switching thin film transistor Tr and the first to seventh driving thin film transistors TFT1 to TFT7. In this case, the first passivation layer 155 is provided with a drain contact hole 157 exposing the drain electrode 146 of each of the switching thin film transistors Tr in the display area.

Although not shown in the drawings, the gate driving circuit unit GDA also corresponds to electrodes selectively connected to each other in correspondence with the gate, source, and drain electrodes of the first to seventh driving TFTs TFT1 to TFT7. A plurality of second contact holes (not shown) may be formed to expose the electrodes.

Next, each pixel area P is disposed on the first passivation layer 155 through the second contact hole as a transparent conductive material, for example, indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel electrode 160 is formed in contact with the drain electrode 146 of the switching thin film transistor Tr.

Although not shown in the drawings, the gate driving circuit unit GDA may include a plurality of gate, source and drain electrodes of the first to seventh driving TFTs TFT1 to TFT7 through the plurality of second contact holes (not shown). A plurality of third auxiliary wirings (not shown) are formed that contact a plurality of optional two electrodes and electrically connect these two electrodes.

In addition, in the gate driving circuit unit GDA, the first to fourth driving storage capacitors C1, C2, C3, and C4 are spaced apart from each other on the first passivation layer 155 in the most characteristic configuration of the present invention. The first electrode 162 is formed. In this case, although not shown in the drawing, the first electrode 162 of the first driving storage capacitor C1 and the drain electrode of the third driving thin film transistor TFT3 are electrically connected to each other. The first electrode of each of the storage capacitors C2 and C3 is electrically connected to the source electrode of the second driving thin film transistor TFT2, and the first electrode of the four driving storage capacitor C4 is the first driving thin film transistor. It is electrically connected with the source electrode of (TFT1).

In this case, an electrical connection between each of the first electrodes of the first to fourth driving storage capacitors C1, C2, C3, and C4 and the gate, source, and drain electrodes of the first to seventh driving thin film transistors TFT1 to TFT7 is performed. Is formed by direct contact through a plurality of second contact holes (not shown) provided in the first passivation layer 155, or a plurality of third auxiliary wirings provided in the first passivation layer 155. It is characterized by what is being done through (not shown).

Next, an inorganic insulating material, eg, silicon oxide, is formed on the pixel electrode 160, the plurality of third auxiliary wirings (not shown), and the first electrode of the first to fourth driving storage capacitors C1, C2, C3, and C4. (SiO ₂ ) or silicon nitride (SiNx) having a thickness of about 1000 GPa to 2000 GPa and a second protective layer 165 is formed on the entire surface of the substrate 101. In this case, the second protective layer 165 may include a plurality of third auxiliary wirings (not shown) or one of the first to seventh driving thin film transistors TFT1 to TFT7 formed on the first protective layer 155. A plurality of third contact holes (not shown) for exposing the electrodes may be further provided.

Next, a transparent conductive material, for example, indium tin oxide (ITO) or indium zinc oxide (IZO), is disposed on the display area over the second passivation layer 165 at predetermined intervals corresponding to each pixel area P. FIG. A common electrode 170 having a plurality of first openings oal1 having a bar shape spaced apart from each other is formed. In this case, the pixel electrode 160 and the common electrode 170 overlapping each other in each pixel area P form a storage capacitor.

The common electrode 170 exposes the switching thin film transistor Tr provided in each pixel region P in addition to the plurality of first openings oa1 provided in the pixel region P. The second opening oa2 may be further provided. In the figure, the second opening oa2 is formed.

In the driving gate circuit unit, first electrodes of the first to fourth driving storage capacitors C1, C2, C3, and C4 are made of the same material forming the common electrode 170 on the second passivation layer 165. In response to this, the second electrode 172 is formed. Therefore, the first electrode 162 and the second protective layer 165 and the first to fourth driving storage capacitors of the first to fourth driving storage capacitors C1, C2, C3, and C4 overlap each other. The second electrodes 172 of C1, C2, C3, and C4 form the first to fourth driving storage capacitors C1, C2, C3, and C4, respectively.

In this case, the second electrode 172 of the first driving storage capacitor C1 is electrically connected to the gate electrode of the seventh driving thin film transistor TFT7, and the second electrode of the second driving storage capacitor C2 is The drain electrode of the third driving thin film transistor TFT3 is electrically connected, and the second electrode of the third driving storage capacitor C3 is electrically connected to the source electrode of the sixth driving thin film transistor TFT6.

In this case, gate, source, and drain electrodes of each of the second electrodes 162 of the first to fourth driving storage capacitors C1, C2, C3, and C4 and the first to seventh driving thin film transistors TFT1 to TFT7. The electrical connection is formed by direct contact through a plurality of third contact holes (not shown) provided in the second protective layer 165 or a plurality of agents provided in the second protective layer 165. 3 It is characterized by being made through auxiliary wiring (not shown).

In the COG type liquid crystal display autonomous array substrate 101 according to the embodiment of the present invention having the above configuration, the first to fourth driving storage capacitors C1, C2, C3, and C4 included in the driving circuit unit GDA may be formed. A dielectric layer interposed between the first and second electrodes 162 and 172 and having a thickness of about 1000 to 2000 micrometers and the second protective layer 165 interposed between the pixel electrode 160 and the common electrode 170 of the display area. ), The capacitor capacity of 2.5 to 5 times can be improved compared to the driving storage capacitor (C1 of FIG. 3) using the interlayer insulating film (60 of FIG. 3) having a thickness of about 5000 kW to 1000 kW as a dielectric layer. .

Therefore, when designed to have the same capacity as the conventional driving storage capacitor can be formed to have an area of about 1/5 to 2/5 of the area of the conventional driving storage capacitor, it is possible to reduce the area of the driving storage capacitor. Therefore, since the area of the non-display area can be finally reduced by reducing the area of the gate driving circuit unit GDA, the bezel width is reduced, thereby making it possible to realize a compact COG type liquid crystal display device.

On the other hand, although not shown in the drawings as a modification according to an embodiment of the present invention, the first protective layer 155 may be omitted. In this case, the pixel electrode 160 and the plurality of second auxiliary wirings are formed on the interlayer insulating layer 130, wherein each pixel electrode 160 is a drain electrode 146 of the switching thin film transistor Tr. It is characterized in that it is formed in direct contact with one end of the) without the drain contact hole.

 In this case, the first protection layer 155 is also omitted in the gate driving circuit unit GDA, so that the first electrodes 162 of the first to fourth driving storage capacitors C1, C2, C3, and C4 are respectively A second passivation layer formed on the interlayer insulating layer 130 and having a thickness of about 1000 GPa to 2000 GPa is formed on the entire surface of the substrate 101, and the first to fourth driving storage capacitors C1, C2, and C3 thereon. The second electrode 172 of the first to fourth driving storage capacitors C1, C2, C3, and C4 is formed to correspond to the first electrode 162 of C4, and thus, in this case, the first electrode Since the capacity of the first to fourth driving storage capacitors C1, C2, C3, and C4 is increased 2.5 to 5 times compared with the conventional, the area can be reduced to 2/5 to 1/5 compared with the conventional.

In addition, this invention is not limited to the above-mentioned embodiment and its modified example, It can implement in various changes within the range which does not deviate from the meaning of this invention.

101: substrate
110: gate insulating film
130: interlayer insulating film
155: first protective layer
162: First electrode of the first driving storage capacitor
165: second protective layer
172: second electrode of the first driving storage capacitor

Claims (11)

A substrate in which a display area having a plurality of pixel areas and a non-display area having a gate driving circuit part around the pixel are defined;
A gate wiring and a data wiring crossing the display region on the substrate to define the pixel region;
A switching thin film transistor connected to the gate and the data line in each pixel area;
A plurality of driving thin film transistors having the same structure as the switching thin film transistor in the gate driving circuit part;
A pixel electrode formed in each pixel region in contact with the drain electrode of the switching thin film transistor;
A first passivation layer formed over the pixel electrode on the entire surface of the substrate and having a first thickness;
A common electrode having a plurality of bar-shaped first openings disposed on the entire surface of the display area over the first passivation layer and spaced apart from each other by a predetermined interval;
A plurality of driving storage capacitors connected to the plurality of driving thin film transistors in the switching region
Each of the plurality of driving storage capacitors may include a first electrode made of the same material on the same layer on which the pixel electrode is formed, and a second electrode made of the same material on the same layer on which the first protective layer and the common electrode are formed. An array substrate, characterized in that configured.
The method of claim 1,
And said first thickness is in the range of 1000 mW to 2000 mW.
The method of claim 1,
A second protective layer covering the switching and driving thin film transistor and having a drain contact hole exposing the drain electrode of the switching thin film transistor on an entire surface of the substrate;
The first electrode of each of the pixel electrode and the plurality of driving storage capacitors is formed on the second protective layer,
And the pixel electrode contacts the drain electrode of the switching thin film transistor through the drain contact hole.
The method of claim 1,
The first protective layer is an array substrate, characterized in that made of silicon oxide (SiO2) or silicon nitride (SiNx) as an inorganic insulating material.
The method of claim 1,
The switching and driving thin film transistors are in contact with the semiconductor layer through the semiconductor layer and the semiconductor layer contact hole, each having a semiconductor layer, a gate insulating layer, a gate electrode, and a semiconductor layer contact hole exposing the semiconductor layer. An array substrate comprising a source and a drain electrode spaced apart from each other.
The method of claim 5, wherein
The semiconductor layer includes a first region of pure polysilicon and a second region of polysilicon doped with impurities at both sides of the first region, and the gate electrode is formed corresponding to the first region. And a contact hole exposing the second region.
The method of claim 5, wherein
Each of the plurality of driving thin film transistors may be selectively contacted with a gate electrode, a source electrode, and a drain electrode constituting each of the driving thin film transistors, or may be connected through a plurality of auxiliary wirings, or electrically connected through the plurality of driving storage capacitors. Array substrate characterized in that connected to.
The method of claim 7, wherein
One of the plurality of driving thin film transistors is connected to the gate line
Array substrate characterized in that.
The method of claim 7, wherein
And a plurality of driving signal wirings connected to one electrode of the plurality of driving thin film transistors in the non-display area.
The method of claim 7, wherein
The plurality of auxiliary wirings are formed on the interlayer insulating film or the gate insulating film, and the plurality of contact holes are formed in the interlayer insulating film and the gate insulating film to expose one electrode of the plurality of driving thin film transistors. And the plurality of auxiliary wires are electrically connected to each electrode of the plurality of driving thin film transistors through holes.
The method of claim 1,
And the common electrode has a second opening corresponding to the switching thin film transistor.

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