KR20110109124A - Input buffer - Google Patents

Abstract

The input buffer includes a bias voltage generation unit generating a bias voltage whose level is adjusted according to whether the switch is turned on, a first load unit generating a gate voltage in response to a resistance value adjusted in response to the bias voltage, and the gate. And a second load unit configured to determine a resistance value between the output nodes to which the output signal is output in response to the voltage.

Description

Input buffer {INPUT BUFFER}

The present invention relates to a semiconductor integrated circuit, and more particularly to an input buffer.

In general, a semiconductor integrated circuit refers to an apparatus packaged to perform logic and memory operations using various transistors and other passive elements implemented by processing a silicon wafer. Various devices and circuits, such as microprocessors and controllers, or DRAM and SRAM, belong to semiconductor integrated circuits.

The semiconductor integrated circuit includes various internal circuits for performing logic and memory operations, and the internal circuit receives an input signal input from the outside through an input buffer. The following is a more detailed look at the function of a general input buffer.

First, when the driving power supply Vdd is 3.3V, the internal circuits of the semiconductor integrated circuit move within the range of 'logic high' to 3.3V and 'logic low' to 0V, and the two potentials (3.3V and 0V) There is a transition point at which logic transitions at about 1.65V, which is the median value. In this case, the logic state follows the driving power with high accuracy and is called rail-to-rail operation.

Of course, the internal power supply of the semiconductor device is not always fixed at 3.3V and can be changed within a limited range by the system's power control and internal and external circumstances, but the CMOS logic clearly performs rail-to-rail operation. . At this time, the input buffer is a device that connects the LVTTL environment of the external bus with the CMOS environment inside the device.

1 and 2 are circuit diagrams of an input buffer according to the prior art.

First, the input buffer shown in FIG. 1 uses a passive load using resistance elements R10 and R11. The input buffer of such a configuration is very vulnerable at high speeds such as DDR3 and low voltage, noise of passive components such as resistors is directly connected to the output signal, and current consumption is not possible because the DC level of the output signal cannot be adjusted. It is difficult to regulate.

Next, the input buffer shown in FIG. 2 uses an active load composed of resistor elements R12 and R13 and NMOS transistors N12 and N13. The input buffer shown in FIG. 2 exhibits superior operating characteristics than the input buffer shown in FIG. 1 when operating at high speed and at low voltage. However, since it is difficult to adjust the resistance value of the load by the resistance values of the resistor elements R12 and R13, and the DC level of the output signal cannot be adjusted, the input buffer shown in FIG. 2 is also shown in FIG. It is difficult to control the current consumption like the input buffer.

The present invention discloses an input buffer that can easily adjust the resistance and current consumption of the load.

To this end, the present invention provides a bias voltage generation unit for generating a bias voltage whose level is adjusted according to whether the switch is turned on, a first load unit for generating a gate voltage in response to a resistance value adjusted in response to the bias voltage; An input buffer includes a second load unit configured to determine a resistance value between output nodes to which an output signal is output in response to the gate voltage.

1 and 2 are circuit diagrams of an input buffer according to the prior art.
3 is a circuit diagram of an input buffer according to an embodiment of the present invention.
FIG. 4A is a diagram for describing a change in the bias voltage level depending on whether a switch is turned on in the bias voltage generator included in the input buffer shown in FIG. 3.
FIG. 4B is a view for explaining a level change of an output signal depending on whether a switch is turned on in the input buffer shown in FIG.
FIG. 4C is a diagram for describing a change in current consumption according to whether a switch is turned on in the input buffer shown in FIG. 3.

Hereinafter, the present invention will be described in more detail with reference to Examples. These embodiments are only for illustrating the present invention, and the scope of rights of the present invention is not limited by these embodiments.

3 is a circuit diagram of an input buffer according to an embodiment of the present invention.

As shown in Fig. 3, the input buffer of this embodiment is composed of a load control unit 2, a DC level control unit 3 and a signal input unit 4. The load control unit 2 includes a bias voltage control unit 20, a first load unit 21, and a second load unit 22.

The bias voltage controller 20 is connected to the resistor elements R21 to R25 connected in series between the first power supply voltage VDD1 and the ground voltage, and the node nd25 to which the ground voltage and the bias voltage BIAS are output. The first switch SW1, the second switch SW2 connected between the node nd21 and the node nd25, the third switch SW3 connected between the node nd22 and the node nd25, and the node nd23. ) And a fourth switch SW4 connected between the node nd25 and a fifth switch SW5 connected between the node nd24 and the node nd25. The level of the bias voltage BIAS output from the bias voltage controller 20 is determined according to whether the first to fifth switches SW1 to SW5 are turned on. As shown in FIG. 4A, only the first switch SW1 is turned on. 0 (V) when turned on, VB2 (V) when only the second switch SW2 is turned on, and VB5 (V) when only the fifth switch SW5 is turned on. That is, the level of the bias voltage BIAS is generated at the smallest level when only the first switch SW1 is turned on and at the largest level when only the fifth switch SW5 is turned on.

The first load unit 21 includes a plurality of PMOS transistors P20-P25 connected in series between the first power supply voltage VDD1 and the node nd26 from which the gate voltage VG is output. The PMOS transistors P20-P25 operate as a switch device turned on in response to the bias voltage BIAS. The turn-on resistance values of the turned on PMOS transistors P20-P25 are determined according to the level of the bias voltage BIAS. do. That is, as the level of the bias voltage BIAS is smaller, the turn-on resistance of the PMOS transistors P20-P25 decreases, and the level of the gate voltage VG increases.

The second load unit 22 includes an NMOS transistor N20 operating as a switch element connected between the second power supply voltage VDD2 and the node nd30 to which the inverted signal OUTB of the output signal is output and turned on, 2 is composed of an NMOS transistor N21 which is connected between the power supply voltage VDD2 and the node nd31 to which the output signal OUT is output and operates as a switch element turned on. Both the NMOS transistor N20 and the NMOS transistor N21 are turned on by receiving the gate voltage VG to determine a resistance value of a load. The resistance value of the load is determined according to the level of the gate voltage VG. As the level of the gate voltage VG increases, the amount of current supplied to the node nd30 and the node nd31 increases. Therefore, as shown in FIG. 4B, when only the first switch SW1 is turned on, the level of the gate voltage VG is formed to be the largest, and therefore the level of the output signal OUT is also formed to be the largest.

The DC level controller 3 is connected between the second power supply voltage VDD2 and the node nd32 to adjust the level of the node nd32 in response to the bias voltage BIAS, and the node ( The current mirror unit 30 includes NMOS transistors N30 and N31 for adjusting the DC level of the node nd30 and the node nd31 according to the level of the nd32. Here, the level of the node nd32 is determined by the level of the bias voltage BIAS, and the current mirror unit 30 forms a constant current source so that the node nd30 and the node (regardless of the level of the input signal IN) nd31) is set. Therefore, the amount of current of the constant current source formed by the current mirror unit 30 is determined according to the level of the bias voltage BIAS. Since the current amount of the constant current source formed by the current mirror unit 30 determines the amount of current consumption of the input buffer, as shown in FIG. 4C, the current consumption of the input buffer is only the first switch SW1. When turned on, it is largest as I1 (A), and when only the fifth switch SW5 is turned on, it is smallest as I5 (A).

The signal input unit 4 is connected between the node nd40 and the node nd42 to receive the input signal IN, and is connected between the node nd41 and the node nd42 to receive the input signal IN. The NMOS transistor N41 receives the inversion signal INB and a constant current source Iss connected to the node nd42.

The input buffer having the above-described configuration determines the level of the bias voltage BIAS according to whether the first to fifth switches SW1 to SW5 are turned on, and loads the input buffer according to the level of the bias voltage BIAS. Adjust the resistance value. More specifically, the input buffer according to the present embodiment includes a first load unit 21 implemented as an active load, and the gate voltage VG is controlled by a turn-on resistance value adjusted according to the level of the bias voltage BIAS. ) And adjusts the turn-on resistance of the second load unit 22 implemented as an active load according to the level of the gate voltage VG. In addition, the input buffer of the present embodiment sets the DC levels of the nodes nd30 and nd31 according to the level of the bias voltage BIAS to adjust the current consumption IDD of the input buffer.

2: load control unit 20: bias voltage control unit
21: first load portion 22: second load portion
3: DC level control unit 30: current mirror unit
4: signal input

Claims (8)

A bias voltage generator configured to generate a bias voltage whose level is adjusted according to whether the switch is turned on;
A first load unit generating a gate voltage in response to a resistance value adjusted in response to the bias voltage;
And a second load unit configured to determine a resistance value between output nodes to which an output signal is output in response to the gate voltage.
The method of claim 1, wherein the bias voltage generation unit
A first resistor connected between the first power supply voltage and the first node;
A first switch connected between the first node and a second node at which the bias voltage is output;
A second resistance element connected between the first node and a third node; And
And a second switch coupled between the second node and the third node.
3. The display device of claim 2, wherein the first load unit comprises at least one first switch device connected between the first power supply voltage and a fourth node to which the gate voltage is output, wherein the first switch device is connected to the bias voltage. An input buffer whose turn-on resistance is adjusted in response.
4. The input buffer of claim 3, wherein the first switch element is a PMOS transistor.
The method of claim 3, wherein the second load unit includes a second switch device connected between a second power supply voltage and the output node, wherein the second switch device is turned on in response to the gate voltage to adjust a turn-on resistance value. Input buffer.
6. The input buffer of claim 5, wherein the second switch element is an NMOS transistor.
The method of claim 1,
A DC level adjusting unit adjusting a DC level of the output node in response to the bias voltage; And
An input buffer including a signal input unit for receiving an input signal to adjust the amount of emission current of the output node.
The method of claim 7, wherein the DC level control unit
A level setting element for setting the level of the first node in response to the bias voltage; And
And a current mirror configured to receive a signal from the first node and adjust a DC level of the output node.

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