KR20110092867A - Wafer level package and manufacturing method thereof - Google Patents

Abstract

Forming a first passivation pattern exposing a bonding pad disposed on the wafer; Forming a seed metal layer along exposed surfaces of the first passivation pattern, the bonding pads and the wafer; Forming a redistribution metal pattern on the seed metal layer to contact the bonding pads; Removing the seed metal layer except for the portion where the redistribution metal pattern is formed; Forming an adhesive layer surrounding the front and side portions of the redistribution metal pattern; Selectively exposing an edge portion of the redistribution metal pattern; And forming a second passivation layer pattern covering the remaining portions except the edge portions of the exposed redistribution metal pattern.

Description

Wafer level package and the method for manufacturing the same

The present invention relates to a semiconductor package, and more particularly, to a wafer level package and a method of manufacturing the same.

As the degree of integration of semiconductor devices increases, the need for high performance increases the importance of packaging of semiconductor devices. Packaging technology electrically connects the input / output and power terminals of semiconductor chips containing integrated circuits to the outside, protects them from sources of external defects such as moisture or dust, and is built to withstand mechanical shocks. It is a technique to let. Packaging technology is rapidly and accurately performing the assembly process of mounting the completed semiconductor chip on the substrate, and research is being conducted toward reducing the overall size of the package to mount a larger number of packages on a limited substrate.

Among such packaging technologies, a wafer level package is proposed and applied, which is directly processed into a package without undergoing a sawing process in a wafer state. A wafer level package can package a number of semiconductor chips in a wafer at the same time, thereby lowering manufacturing costs, and the size of the semiconductor chip becomes the package area, thereby making the package smaller.

The wafer level package includes a semiconductor chip and a redistribution layer (RDL). Bonding pads are disposed at the front center of the semiconductor chip, and are electrically connected to an integrated circuit of a substrate having an integrated circuit. The redistribution layer connects the bonding pads disposed in the center of the semiconductor chip with the electrode pads disposed in the edge portion of the substrate. The redistribution layer is composed of an insulating layer and a metal wiring with a portion of the surface exposed on the insulating layer.

Meanwhile, when fabricating a wafer level package, a passivation layer is introduced to prevent the metal film disposed on the semiconductor chip from being electrically connected to the new metal wiring for the package. In this case, the metal wirings of the redistribution layer are joined in direct contact with the passivation layer. However, when the metal wiring and the passivation layer of the redistribution layer are directly contacted and bonded, there is a problem in that the passivation layer is not formed accurately at a desired position due to the diffuse reflection property of the metal wiring in the subsequent passivation process. In addition, there is a problem that the reliability is degraded, such as the passivation layer is separated from the redistribution layer in the subsequent process to act as a defect.

The technical problem to be achieved by the present invention is a method of manufacturing a wafer-level package that can improve the reliability of the process by reducing the diffuse reflection phenomenon of the metal wiring by changing the bonding method of the metal wiring and the passivation layer of the redistribution layer during wafer-level package manufacturing To provide.

A method of manufacturing a wafer level package according to an embodiment of the present invention includes forming a first passivation pattern exposing a bonding pad disposed on a semiconductor chip; Forming a seed metal layer along an exposed surface of the first passivation pattern, the bonding pad, and the semiconductor chip; Forming a redistribution metal pattern connected to the bonding pad on the seed metal layer; Removing the seed metal layer except for the portion where the redistribution metal pattern is formed; Forming an adhesive layer surrounding front and side portions of the redistribution metal pattern; Selectively exposing an edge portion of the redistribution metal pattern; And forming a second passivation layer pattern covering the remaining portion except for the edge portion of the exposed redistribution metal pattern.

In the present invention, after removing the seed metal layer, it is preferable to further include forming a connection electrode film surrounding the redistribution metal layer.

The connection electrode film may include nickel (Ni), palladium (Pd), or silver (Au).

Exposing the edge portion of the redistribution metal pattern, after forming the adhesive layer, it is preferable to remove a portion of the surface of the adhesive layer to expose.

The seed metal layer is formed by sputtering a titanium (Ti) film or a copper (Cu) film into each single film or a laminated structure, and the redistribution metal pattern is formed by electroplating including copper (Cu). It is preferable.

The adhesive layer may be formed of a material that maintains the adhesion state between the second passivation layer and the lower layer and prevents diffuse reflection of the lower layer.

The adhesive layer is preferably formed by selecting one or more materials from the group of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) and titanium-tungsten alloy (TiW).

A wafer level package according to the present invention includes a semiconductor chip on which a bonding pad is disposed; A first passivation pattern exposing a bonding pad disposed on the semiconductor chip; A seed metal layer formed along an exposed surface of the first passivation pattern, the bonding pad, and the semiconductor chip; A redistribution metal pattern formed on the seed metal layer to be in contact with the bonding pad; An adhesive layer for selectively exposing an edge portion of the redistribution metal pattern while covering the front and side portions of the redistribution metal pattern; And a second passivation layer pattern covering the remaining portion except for the exposed portion of the redistribution metal pattern.

According to the present invention, it is possible to improve the problem that the passivation pattern cannot be accurately formed in a desired pattern shape by the diffuse reflection characteristic of the metal generated when the passivation pattern is directly formed on the connection electrode film. In addition, the adhesive layer may be disposed between the connection electrode film and the passivation pattern to prevent the passivation pattern from falling off in a subsequent step.

1 to 12 are views illustrating a method of manufacturing a wafer level package according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

1 to 12 illustrate a wafer level package and a method of manufacturing the same according to an embodiment of the present invention.

Referring to FIG. 1, a semiconductor chip 100 is prepared. The semiconductor chip 100 includes a data storage unit (not shown) and a data processing unit (not shown) formed by performing a semiconductor device manufacturing process. The bonding pads 105 are disposed in the front center portion of the semiconductor chip 100. The bonding pad 105 is electrically connected to a data storage unit or a data processor embedded in the semiconductor chip 100. In addition, the semiconductor chip 100 further includes a fuse box 110 including a fuse for repairing the data storage unit. An insulating layer pattern 120 having a first opening 117 exposing the bonding pad 105 and a second opening 119 exposing the fuse box 110 is disposed on the semiconductor chip 100. The insulating layer pattern 120 includes a polyimid isoindro quindzoline (PIQ) film.

Referring to FIG. 2, a first passivation pattern 125 is formed on the semiconductor chip 100. The first passivation pattern 125 has a first opening 117 that exposes the bonding pad 105 disposed on the front center portion of the semiconductor chip 100, and blocks the fuse box 110. The first passivation pattern 125 may block the fuse box 110 to prevent an electrical short between the metal film of the redistribution layer to be subsequently formed and the fuse box 110.

Referring to FIG. 3, a seed metal layer 130 is formed on the semiconductor chip 100. The seed metal layer 130 may form a titanium (Ti) film or a copper (Cu) film, respectively, or in a stacked structure, and may be formed by a sputtering method. The seed metal layer 130 serves to easily bond the metal layer of the redistribution layer to be subsequently formed on the first passivation pattern 125. The seed metal layer 130 is formed along the exposed surface of the first passivation pattern 125 and the bonding pad 105, and is also formed on the insulating layer pattern 120 exposed to the edge portion of the semiconductor chip 100.

Referring to FIG. 4, a resist film pattern 135 having a third opening 137 defining a region where a redistribution metal layer is to be formed is formed. To this end, a resist is coated on the semiconductor chip 100 and a lithography process including an exposure and development process is performed to selectively expose the seed metal layer 130 in the region where the redistribution metal layer is to be formed. A resist film pattern 135 having 137 is formed. The resist layer pattern 135 blocks other regions except for the third openings 137.

Referring to FIG. 5, a redistribution metal layer (RDL) 140 is formed on the seed metal layer 130 exposed in the resist film pattern 135. The redistribution metal layer 140 may include copper (Cu) by electroplating. The redistribution metal layer 140 is connected to the bonding pad 105 to electrically extend the bonding pad 105 along the redistribution metal layer 140. Next, the resist film pattern 135 is removed by a strip process. Then, as shown in FIG. 6, the lower seed metal layer 130 covered with the resist film pattern 135 is partially exposed.

Referring to FIG. 7, the seed metal layer 130 (see FIG. 6) of the exposed portion may be etched. The redistribution metal layer 140 is partially formed on the seed metal layer 130 by the electroplating method, but the seed metal layer 130 does not remove a portion outside the redistribution metal layer 140, thereby causing an electrical short circuit. Accordingly, an etching process of removing the seed metal layer 130 exposed outside the redistribution metal layer 130 and the first passivation pattern 125 is performed.

Referring to FIG. 8, a connection electrode film 145 is formed on the redistribution metal layer 130. The connection electrode film 145 may be formed by electroless plating, and may include nickel (Ni), palladium (Pd), or silver (Au). The redistribution metal layer 130 including copper (Cu) is difficult to directly connect the metal wires in a metal wiring bonding process for connecting to the electrode pad of the printed circuit board. Accordingly, the connection electrode film 145 made of a material which is easily connected to the metal wire is formed on the redistribution metal layer 130. Here, the connection electrode film 145 is formed to surround the redistribution metal layer 130. Accordingly, the outside of the first passivation pattern 125 and the outside of the insulating layer pattern 120 are exposed.

Referring to FIG. 9, an adhesion layer 150 is formed by extending along the exposed surface of the connection electrode film 145. The adhesive layer 150 is formed of a material having excellent adhesive properties and low reflectance, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and titanium-tungsten alloy. It can be formed by selecting one or more materials from the group of (TiW). The adhesive layer 150 may be formed by a method of depositing a thin film, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). As the adhesive layer 150 is formed on the entire surface of the semiconductor chip 100, the adhesive layer 150 is covered with the adhesive layer 150 to the outside of the exposed first passivation pattern 125 and to the outside of the insulating layer pattern 120.

Referring to FIG. 10, a resist film pattern 155 having a fourth opening 160 defining a region in which a bonding pad is to be formed is formed at an edge of the semiconductor chip 100. To this end, a resist is coated on the adhesive layer 150, and a resist having a fourth opening 160 for selectively exposing the adhesive layer 150 in a region where a bonding pad is to be formed by performing a lithography process including an exposure and development process. The film pattern 155 is formed. The resist layer pattern 155 selectively exposes the first passivation pattern 125 and the insulating layer pattern 120 of the outer portion of the semiconductor chip 100 while blocking the remaining regions except for the fourth opening 160.

Referring to FIG. 11, a portion of the surface of the connection electrode film 145 is exposed by removing the adhesive layer 150 of the portion exposed by the resist film pattern 155. The resist film pattern 155 is removed by a strip process. Here, the adhesive layer 150 is also removed from the outer portion of the semiconductor chip 100 to partially expose the first passivation pattern 125 and the insulating layer pattern 120.

Referring to FIG. 12, a second passivation pattern 165 exposing the surface of the connection electrode film 145 is formed. The second passivation pattern 165 blocks the first passivation pattern 125 and the insulating layer pattern 120 at the outer portion of the adhesive layer 150 and the semiconductor chip 100, and blocks the fourth openings 160 (see FIG. 10). Exposed connection electrode film 145 is exposed. To this end, a second passivation film is formed on the semiconductor chip 100. Next, a resist is applied on the second passivation film, a resist pattern is formed by a lithography process including an exposure and development process, and then the second passivation film is etched with the resist pattern to form a second passivation pattern 165. do. In this case, when the second passivation pattern 165 is directly formed on the connection electrode film 145, there is a problem in that the second passivation pattern 165 cannot be accurately formed due to the diffuse reflection property of the metal.

In contrast, in the present invention, the diffuse reflection of light generated when the second passivation pattern 165 is formed may be reduced by the lower adhesive layer 150, thereby improving reliability. The adhesive layer 150 may be disposed between the connection electrode layer 145 and the second passivation pattern 165, which are redistributed metal layers, to prevent the second passivation pattern 165 from falling off in a subsequent process. This method can be applied to any type of package. For example, in the exemplary embodiment of the present invention, a method of applying in a wafer level package has been described, but it can be applied to all package types such as RDL, TSV, Flip chip, or CSP.

100: semiconductor chip 125: first passivation pattern
130: seed metal layer 140: redistribution metal layer
145: connection electrode film 150: adhesive layer
165: second passivation pattern

Claims (12)

Forming a first passivation pattern exposing a bonding pad disposed on the semiconductor chip;
Forming a seed metal layer along an exposed surface of the first passivation pattern, the bonding pad, and the semiconductor chip;
Forming a redistribution metal pattern connected to the bonding pad on the seed metal layer;
Removing the seed metal layer except for the portion where the redistribution metal pattern is formed;
Forming an adhesive layer surrounding front and side portions of the redistribution metal pattern;
Selectively exposing an edge portion of the redistribution metal pattern; And
Forming a second passivation layer pattern covering a portion of the exposed redistribution metal pattern except for an edge portion thereof. The method of claim 1,
After removing the seed metal layer, forming a connection electrode layer surrounding the redistribution metal layer. The method of claim 2,
The connecting electrode film is nickel (Ni), palladium (Pd) or silver (Au) containing a manufacturing method of a wafer level package. The method of claim 1,
Exposing the edge portion of the redistribution metal pattern, after the forming of the adhesive layer, a portion of the surface of the adhesive layer is removed to expose the wafer level package manufacturing method. The method of claim 1,
The seed metal layer is a method of manufacturing a wafer level package to form a titanium (Ti) film or a copper (Cu) film by sputtering (sputtering) to each single film or laminated structure. The method of claim 1,
The redistribution metal pattern is a method of manufacturing a wafer level package including copper (Cu) is formed by the electroplating method. The method of claim 1,
The adhesive layer is a method of manufacturing a wafer level package made of a material to maintain the adhesion state of the second passivation layer and the lower layer, and to prevent diffuse reflection of the lower layer. The method of claim 7, wherein
The adhesive layer is a wafer-level package for forming at least one material selected from the group of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) and titanium-tungsten alloy (TiW) Way. A semiconductor chip on which bonding pads are disposed;
A first passivation pattern exposing a bonding pad disposed on the semiconductor chip;
A seed metal layer formed along an exposed surface of the first passivation pattern, the bonding pad, and the semiconductor chip;
A redistribution metal pattern formed on the seed metal layer to be in contact with the bonding pad;
An adhesive layer for selectively exposing an edge portion of the redistribution metal pattern while covering the front and side portions of the redistribution metal pattern; And
And a second passivation layer pattern covering the remaining portion of the redistribution metal pattern except for the exposed portion. 10. The method of claim 9,
The adhesive electrode layer may include nickel (Ni), palladium (Pd), or silver (Au). 10. The method of claim 9,
The seed metal layer may include a titanium (Ti) film or a copper (Cu) film, each having a single layer or a stacked structure. 10. The method of claim 9,
The adhesive layer is a wafer level package formed by selecting one or more materials from the group of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) and titanium-tungsten alloy (TiW).

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