KR20110086453A - Manufacturing Method of Phase Change Memory Device - Google Patents

Abstract

The present invention discloses a method of manufacturing a phase change memory device. The method includes depositing a first conductive film on the interlayer insulating film and the lower electrode contact hole; Depositing a second conductive layer on the first conductive layer to gap fill the lower electrode contact hole; Anisotropically etching the first and second conductive layers to form a first lower electrode contact having a predetermined thickness under the lower electrode contact hole; Forming a spacer covering an upper surface of the first conductive layer etched on sidewalls of the lower electrode contact hole; Sequentially depositing a third conductive film and a gap fill insulating film on the interlayer insulating film, the spacer and the first lower electrode contact, and then performing a planarization process until the upper surface of the interlayer insulating film is exposed; Selectively etching the interlayer insulating layer, the third conductive layer, and the gapfill insulating layer to form a lower electrode contact to which the first lower electrode contact and the third conductive layer are connected; Characterized in that it comprises a. Therefore, according to the present invention, as the set resistance is reduced, the sensing margin of the data increases, thereby increasing the reliability of the data, the yield of the chip, and efficiently increasing the joule heat, thereby reducing the reset current consumed and power consumption. In addition, the resistance distribution of the lower electrode contact may be improved to improve performance and integration of the phase change memory device.

Description

Method of manufacturing phase change memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a phase change memory device, and more particularly, to a method of manufacturing a phase change memory device capable of reducing power reset and enabling high integration and reducing set resistance to improve data reliability. will be.

In general, phase-change materials are materials having different states of a crystalline state and an amorphous state depending on temperature. The crystalline state exhibits lower resistance than the amorphous state and has a regular ordered atomic arrangement.

The crystalline state and the amorphous state can be mutually reversible. That is, it can be changed from the crystalline state to the amorphous state, and can be changed from the amorphous state to the crystalline state again. PRAM (Phase-Change Memory Device) is applied to a memory device having a mutually changeable state and having a characteristic that can be clearly distinguished.

FIG. 1 is a view for explaining a method of operating a conventional phase change memory device, and includes a lower electrode 10a, a lower electrode contact 10b, a phase change material layer 10c, and an upper electrode 10d. The phase change region A1 is formed in the change material layer 10c.

Referring to FIG. 1, when the phase of the phase change material layer 10c is in the crystalline state, it is assumed to be a set state and the bit data “1” is recorded. The first phase transition current I1 is applied from the upper electrode 10d to the lower electrode 10a via the phase change material layer 10c while the bit data “1” is written in the phase change material layer 10c.

The first phase transition current I1 is a current that changes the phase of the portion in contact with the lower electrode contact 10b of the phase change material layer 10c to an amorphous state, and is called a reset current. The first phase transition current I1 is concentrated in the lower electrode contact 10b, which is much narrower than the phase change material layer 10c.

In addition, when the phase change region A1 of the phase change material layer 10c is in an amorphous state, it is referred to as a reset state, and bit data “0” is regarded as recorded. When the phase change region A1 of the phase change material layer 10c is in an amorphous state, the second phase transition current I2 in the same direction as the first phase transition current I1 in the storage node units 10a, 10b, 10c, and 10d. ) Is applied. The second phase transition current I2 is called a set current because the phase of the phase change region A1 of the phase change material layer 10c changes from an amorphous state to an original crystal state.

As described above, the resistance state of the phase change material layer 10c in the PRAM according to the prior art is determined by the first phase transition current I1 and the second phase transition current I2. However, the increase in the first phase transition current I1, that is, the reset current, is an obstacle to improving the characteristics of the PRAM.

In detail, it is not technically difficult to reduce the size of the PRAM by reducing the size of the storage node units 10a, 10b, 10c, and 10d and the diode according to the development of semiconductor manufacturing technology. However, as the size of the diode decreases, the current that the diode can accept, that is, the current that the diode can tolerate, becomes smaller, making it difficult to virtually integrate the PRAM without reducing the reset current.

Therefore, the research and development of the PRAM currently aims at low power driving by reducing the reset current and lowering the set resistance to increase the sensing margin of the data, thereby achieving a high reliability device.

The most basic method for reducing the reset current is to increase the Joule thermal effect by increasing the interface resistance between the phase change material layer and the lower electrode contact, and the basic method for reducing the set resistance is the phase which occupies the highest specific gravity of the set resistance. It is to reduce the contact string resistance between the change material layer and the bottom electrode contact. The two are trade-offs, and bottlenecks exist in the development of PRAM technology.

That is, although the cross sectional area of the lower electrode contact can be reduced, the cross sectional area distribution of the lower electrode contact is essentially determined by the area spread of the lower electrode contact hole.

Thus, if the reduction of the cross-sectional area of the lower electrode contact does not involve a decrease in the cross-sectional area distribution, which is at least in the same proportion, the reduction of the cross-sectional area of the lower electrode contact rather reduces the uniformity of the memory cells.

This uniformity problem is a technical issue that significantly affects the yield of the PRAM in that the integration of the semiconductor device increases as the degree of integration increases. Therefore, a technique for reducing not only the cross-sectional area of the lower electrode contact but also its dispersion is required.

An object of the present invention is to form a wide contact area with a lower structure in a lower region of a lower electrode contact of a phase change memory device, and to prevent a lower electrode contact component having a low resistance from contacting a phase change material layer in an upper region. It is to provide a method of manufacturing a phase change memory device to improve the.

A method of manufacturing a phase change memory device of the present invention for achieving the above object comprises the steps of depositing a first conductive film on the interlayer insulating film and the lower electrode contact hole; Depositing a second conductive layer on the first conductive layer to gap fill the lower electrode contact hole; Anisotropically etching the first and second conductive layers to form a first lower electrode contact having a predetermined thickness under the lower electrode contact hole; Forming a spacer covering an upper surface of the first conductive layer etched on sidewalls of the lower electrode contact hole; Sequentially depositing a third conductive film and a gap fill insulating film on the interlayer insulating film, the spacer and the first lower electrode contact, and then performing a planarization process until the upper surface of the interlayer insulating film is exposed; Selectively etching the interlayer insulating layer, the third conductive layer, and the gapfill insulating layer to form a lower electrode contact to which the first lower electrode contact and the third conductive layer are connected; Characterized in that it comprises a.

The forming of the lower electrode contact hole in the method of manufacturing a phase change memory device of the present invention for achieving the above object includes depositing the interlayer insulating film on a substrate on which a lower structure is formed; Etching the interlayer insulating layer to expose the lower structure to form the lower electrode contact hole; Characterized in that it comprises a.

The lower structure of the method of manufacturing a phase change memory device of the present invention for achieving the above object is characterized in that it comprises a stack of an active region, a diode, a metal silicide layer formed on the substrate.

The lower electrode contact hole of the method of manufacturing a phase change memory device of the present invention for achieving the above object is characterized in that formed in a cylindrical shape using an anisotropic etching process.

The first conductive film of the method of manufacturing a phase change memory device of the present invention for achieving the above object is any one of tungsten (W), titanium (Ti), tantalum (Ta), aluminum (Al), and copper (Cu). Using to form a lower portion of the first lower electrode contact.

The second conductive layer of the method of manufacturing a phase change memory device of the present invention for achieving the above object is a tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), aluminum nitride (AlN) and titanium aluminum nitride ( TiAlN) to form an upper portion of the first lower electrode contact.

The first and second conductive films of the method of manufacturing a phase change memory device of the present invention for achieving the above object is formed using any one of a sputtering process, a chemical vapor deposition process, and an atomic layer deposition process. .

The first lower electrode contact of the method of manufacturing a phase change memory device of the present invention for achieving the above object is a cylindrical shape in which the first and second conductive layers are electrically connected to contact the upper surface of the lower structure. do.

The first and second conductive films of the method of manufacturing a phase change memory device of the present invention for achieving the above object is characterized by having an etch selectivity with respect to the interlayer insulating film.

The predetermined thickness of the method of manufacturing a phase change memory device of the present invention for achieving the above object is characterized in that 15 to 25% of the depth of the lower electrode contact hole.

Forming the spacer of the method of manufacturing a phase change memory device of the present invention for achieving the above object comprises depositing a spacer film on the interlayer insulating film and the first lower electrode contact; And anisotropically etching the spacer film so that the top surface of the interlayer insulating layer and the top surface of the first lower electrode contact are exposed.

The spacer film of the method of manufacturing a phase change memory device of the present invention for achieving the above object is characterized by having an etching selectivity with respect to the second conductive film.

In order to achieve the above object, the third conductive layer of the method of manufacturing a phase change memory device of the present invention may be formed of a material substantially the same as that of the second conductive layer, and may be formed to have a uniform resistance value to form the second conductive layer. It is characterized in that it is electrically connected.

In the forming of the lower electrode contact of the method of manufacturing a phase change memory device of the present invention for achieving the above object, the interlayer insulating film, the spacer, and the gapfill insulating film are etched using a gaseous plasma of a first type. The third conductive layer may remain to form the lower electrode contact in the form of a double plug.

The first kind of gas of the method of manufacturing a phase change memory device of the present invention for achieving the above object is characterized in that any one of the gas selected from the group consisting of hydrogen, nitrogen and oxygen and fluorine.

In the forming of the lower electrode contact of the method of manufacturing a phase change memory device of the present invention for achieving the above object, the third conductive layer is etched by using a gaseous plasma of a second type, and the interlayer insulating layer and the The spacer layer and the gap fill insulating layer remain to form the lower electrode contact hole having a ring-shaped recess and form the lower electrode contact in a partially confined form.

The second kind of gas of the method of manufacturing a phase change memory device of the present invention for achieving the above object is characterized in that any one gas selected from a compound of hydrogen, nitrogen and oxygen and chlorine.

Depositing a phase change material film on the etched interlayer insulating film, the gap fill insulating film and the lower electrode contact after forming the lower electrode contact of the method of manufacturing a phase change memory device of the present invention for achieving the above object. ; And depositing a fourth conductive film on the phase change material film.

The fourth conductive film of the method of manufacturing a phase change memory device of the present invention for achieving the above object comprises any one of polysilicon, metal and conductive metal nitride doped with impurities as a material for the upper electrode, sputtering process, chemical It is formed using any one of a vapor deposition process and an atomic layer deposition process.

In the lower region of the lower electrode contact of the manufacturing method of the phase change memory device of the present invention, the contact area with the lower structure is formed to be wide, and as the set resistance is reduced, the sensing margin of the data increases, thereby increasing the reliability of the data and the yield of the chip. do.

In addition, in the upper region of the lower electrode contact, the lower electrode contact component having a lower resistance may increase in thickness without being in contact with the phase change material layer, so that the Joule heat may be efficiently increased along with the set resistance reduction. Current is reduced and power consumption is reduced.

Accordingly, the resistance distribution is improved in the upper and lower regions of the lower electrode contact, thereby improving the performance and integration of the phase change memory device.

1 is a view for explaining a method of operating a conventional phase change memory device.
2 to 11 are cross-sectional views of processes for describing a method of manufacturing a phase change memory device according to an embodiment of the present invention.
12 and 13 are cross-sectional views of processes for describing a method of manufacturing a phase change memory device, according to another embodiment of the present invention.

Hereinafter, the manufacturing method of the phase change memory device of the present invention will be described.

2 to 11 are cross-sectional views of processes for describing a method of manufacturing a phase change memory device according to an embodiment of the present invention.

First, as shown in FIG. 2, the interlayer insulating layer 140 is formed on the substrate 100 on which the lower structure 135 is formed. The substrate 100 includes a silicon wafer, and the lower structure 135 includes a stack of an active region 110, a diode 120, and a metal silicide layer 130.

The interlayer insulating layer 140 includes at least one oxide film or nitride film.

For example, the oxide film is formed using tetraethly orthosilicate (TEOS), undoped silicate glass (USG), spin on glass (SOG), and oxide, and the nitride film is formed using silicon nitride (SixNy).

The interlayer insulating layer 140 is formed using a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, and an atomic layer deposition (ALD) process, and completely covers an underlying structure disposed on the substrate 100. It is formed to be wide enough.

As shown in FIG. 3, by partially etching the interlayer insulating layer 140 using an exposure and etching process, a lower electrode contact hole 150H is formed to partially expose the lower structure in the interlayer insulating layer 140. The electrode contact hole 150H is formed in a cylindrical shape using an anisotropic etching process.

Here, the exposure and etching process refers to a process of selectively removing a layer formed on the substrate as a result of an oxidation process or a thin film deposition process, and the anisotropic etching process means that the etching reaction proceeds in one direction only, for example, in a vertical direction. Refers to the etching process.

As illustrated in FIG. 4, the first conductive layer 152 is deposited on the interlayer insulating layer 140 and the partially exposed lower structure 135, and the second conductive layer 152 is formed on the first conductive layer 152. 154 is deposited to gap fill the lower electrode contact hole 150H.

The first conductive layer 152 is a material that forms a lower portion of the first lower electrode contact, and has a good deposition property and step coverage, for example, tungsten (W), titanium (Ti), and tantalum (Ta). ), Aluminum (Al), copper (Cu) and the like are preferably set to a thickness of about 10 to 50 angstroms.

 In addition, the second conductive layer 154 is a material that is electrically connected to the first conductive layer 152 to form an upper portion of the first lower electrode contact, and is a conductive metal nitride having good evaporation and step coverage. For example, it is formed using tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), aluminum nitride (AlN) or titanium aluminum nitride (TiAlN).

The first and second conductive layers 152 and 154 are formed using a sputtering process, a chemical vapor deposition process, and an atomic layer deposition process.

As shown in FIG. 5, the anisotropic etching is performed by adjusting the etching amount and the etching time of the first and second conductive layers 152 and 154 gap-filled in the lower electrode contact hole 150H by using an exposure and etching process. In this case, since the first and second conductive layers 152 and 154 have an etching selectivity with respect to the interlayer insulating layer 140, the first lower portion having a cylindrical shape having a predetermined height and a wide contact area under the lower electrode contact hole 150H. Electrode contact 156 is formed.

The predetermined height is preferably about 20% of the depth of the lower electrode contact hole 150H. For example, assuming that the depth of the lower electrode contact hole 150H is 1000 angstroms, the first lower electrode contact 156 may be formed. It is desirable to form the height of about 400 angstroms.

Therefore, as the contact area between the first lower electrode contact 156 and the lower structure 135 is wider and the set resistance is reduced, the sensing margin of the data increases, thereby increasing the reliability of the data and the yield of the chip. .

Here, the etching selectivity means that only one of the two materials is selectively etched when the two materials are etched using a specific etching gas or an etching solution.

As shown in FIG. 6, after the spacer film is deposited on the interlayer insulating layer 140 and the etched first lower electrode contact 156, the spacer film is anisotropically etched using an anisotropic etching method to form the spacer 160.

The spacer film is chemically formed using a material having an etch selectivity with respect to the second conductive film 154, for example, a nitride such as silicon nitride or an oxynitride such as silicon oxynitride (SiON) or titanium oxynitride (SiON). It is formed using a vapor deposition process, a plasma enhanced chemical vapor deposition process, an atomic layer deposition process.

As shown in FIGS. 7 and 8, the third conductive layer 170 is deposited on the upper portion of the first lower electrode contact 156 and the spacer 160 exposed through etching and the interlayer insulating layer 140. .

In this case, since the third conductive layer 170 is electrically connected to the first lower electrode contact 156, the same material and process as those of the second conductive layer 154 may be used for uniformity of the resistance value. desirable.

In addition, a gap fill insulating layer 180 is deposited on the deposited third conductive layer 170 to gap fill the lower electrode contact hole 150H.

Here, the kind and formation process of the gap fill insulating film need not necessarily use the same materials and processes as those in the spacer film.

As shown in FIG. 9A, an etching back process or a chemical mechanical polishing (CMP) process is performed until the upper surface of the interlayer insulating layer 140 is exposed. The second lower electrode contact 175 is formed by planarizing the third conductive layer 170 and the gap-fill insulating layer 185 stacked above the electrode contact hole 150H to exceed the height of the surface of the interlayer insulating layer 140.

FIG. 9 (b) is a view showing a plan view after completion of the planarization process according to FIG. 9 (a) with a cross-sectional view of FIG. 9 (a). And a lower electrode contact 175 and a circular gap fill insulating film 185.

Therefore, as compared with the conventional lower electrode contact having a single cylindrical shape, the contact area with the phase change material film is reduced by the thin film of the ring-shaped second lower electrode contact 176, and as a result, the amount of heat increases. It is possible to easily phase change even a small reset current, thereby reducing the power consumption by reducing the reset current consumed.

As shown in FIG. 10, the interlayer insulating layer 140, the spacer 160, and the gap fill insulating layer 185 are etched by anisotropic etching on the planarized surface of FIG. 9A using a dry etching method.

The dry etching method is etching using a plasma of a certain kind of gas selected from the group consisting of hydrogen, nitrogen, oxygen, fluorine compounds and chlorine compounds as an etching gas. In the present embodiment, among the compounds of hydrogen, nitrogen, oxygen and fluorine The etching rate of the interlayer insulating layer 140, the spacer 160, and the gap fill insulating layer 185 is significantly higher than that of the second lower electrode contact 176 due to the linearity of the first type of gas plasma ions. The 140, the spacer 160, and the gap fill insulating layer 185 may be etched, but the second lower electrode contact 176 remains to form the lower electrode contact 177 having a double plug type.

As shown in FIG. 11, the phase change material layer 190 is deposited to cover all of the end surfaces of the etched interlayer insulating layer 140, the spacer 160, and the gap fill insulating layer 185 and the lower electrode contact 177. The phase change material film 190 includes a chalcogenide compound, for example, germanium-antimony-tellurium (Ge-Sb-Te), arsenic-antimony-tellurium (As-Sb-Te), tin-antimony-tellurium (Sn-Sb-Te), tin-indium-antimony-tellurium (Sn-In-Sb-Te), arsenic-germanium-antimony-tellurium (As-Ge-Sb-Te), etc. are mentioned.

In addition, a fourth conductive layer 200 is formed on the phase change material layer 190.

Here, the fourth conductive film 200 is a material for the upper electrode, and thus the resistance values of the first to third conductive films 152, 154, and 170 are not necessarily uniform. It is not necessary to use the same materials and processes as 154, 170).

Accordingly, the type of the fourth conductive film 200 may include polysilicon, a metal, or a conductive metal nitride doped with impurities, and the process of forming the fourth conductive film 200 may include a sputtering process, a chemical vapor deposition process, and an atom. A layer lamination process.

In FIG. 11, since the lower electrode contact 177 protrudes from the etched surface in the form of a double plug to contact the phase change material film 190, the lower electrode contact 177 contacts the phase change material film 190 in a state where the lower electrode contact 177 does not protrude from the conventional etched surface. Compared to the case, the contact area increases, so that the set resistance can be reduced.

In addition, the first conductive layer 152 has a lower resistance than the second conductive layer 154 in order to prevent the first conductive layer 152 from contacting the phase change material layer 190 through the spacer 160 to lower the set resistance. When the thickness of the film 152 is increased, the joule heat is reduced due to the contact of the first conductive film 152 with the area in contact with the phase change material film 190.

12 and 13 are cross-sectional views of processes for describing a method of manufacturing a phase change memory device, according to another embodiment of the present invention.

2 to 9B are the same as the embodiment of the present invention, so further detailed description will be omitted, and hereinafter, only different processes will be described according to another embodiment of the present invention.

As shown in FIG. 12, the third conductive layer 175 is etched by anisotropic etching on the planarized surface of FIG. 9A using a dry etching method.

In the present embodiment, the interlayer insulating layer 140, the spacer 160, and the gap fill compared to the etching rate generated in the third conductive layer 175 due to the linearity of the plasma plasma ions selected from hydrogen, nitrogen, oxygen, and chlorine compounds. The etching rate of the insulating layer 185 is remarkably low so that the third conductive layer 175 is etched, but the interlayer insulating layer 140, the spacer 160, and the gap-fill insulating layer 185 remain to form a ring-shaped recess 177H. Excitation lower electrode contact holes 150H are formed.

As shown in FIG. 13, the phase change material layer 190 is deposited to cover both the etched interlayer insulating layer 140, the spacer 160, and the gap fill insulating layer 185 and the ring-shaped recess 177H. As a result, the third lower electrode contact 179 having a partial confined shape is formed.

That is, when the phase change material layer 190 is deposited on the remaining recess 177H of the lower electrode contact hole 150H partially filled with the third conductive layer 175, the lower electrode contact hole 150H may be formed on the bottom of the lower electrode contact hole 150H. The lower electrode contact 179 is formed, and the phase change material layer 190 is filled in the recess 177H on the lower electrode contact hole 150H so that the lower electrode contact hole 150H is formed in a partially confined shape.

Accordingly, the phase change material layer 190 is buried in the partially confined lower electrode contact hole 150H to suppress the expansion of the phase change volume to concentrate the heating of the phase change region, thereby partially depositing on the conventional etched surface. Compared to the case where the phase change material layer 190 is in contact with the phase change material layer 190 in a non-conformed state, the Joule heat increases, thereby reducing the reset current.

The phase change material film 190 includes a chalcogenide compound, for example, germanium-antimony-tellurium (Ge-Sb-Te), arsenic-antimony-tellurium (As-Sb-Te), tin-antimony-tellurium (Sn-Sb-Te), tin-indium-antimony-tellurium (Sn-In-Sb-Te), arsenic-germanium-antimony-tellurium (As-Ge-Sb-Te), etc. are mentioned.

In addition, a fourth conductive layer 200 is formed on the phase change material layer 190.

Here, the fourth conductive film 200 is a material for the upper electrode, and thus the resistance values of the first to third conductive films 152, 154, and 170 are not necessarily uniform. It is not necessary to use the same materials and formation processes as 154, 170).

Accordingly, the type of the fourth conductive film 200 may include polysilicon, a metal, or a conductive metal nitride doped with impurities, and the process of forming the fourth conductive film 200 may include a sputtering process, a chemical vapor deposition process, and an atom. A layer lamination process.

As described above, in the method of manufacturing the phase change memory device of the present invention, the sensing area of the data increases as the set resistance is reduced by forming a wide contact area with the lower structure 135 in the lower region of the lower electrode contact. And the yield of the chip is increased.

In addition, in the upper region of the lower electrode contact, the lower electrode contact component having a lower resistance may increase in thickness without being in contact with the phase change material layer, so that the Joule heat may be efficiently increased along with the set resistance reduction. Current is reduced and power consumption is reduced.

Accordingly, the resistance distribution is improved in the upper and lower regions of the lower electrode contact, thereby improving the performance and integration of the phase change memory device.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art can be variously modified and modified within the scope of the present invention without departing from the spirit and scope of the present invention described in the claims below. It will be appreciated that it can be changed.

100 substrate 110 active region
120: diode 130: metal silicide layer
140: interlayer insulating film 152: first conductive film
156: first lower electrode contact 160: spacer
175: second lower electrode contact 185: gap fill insulating film
190: phase change material film 200: fourth conductive film

Claims (19)

Depositing a first conductive film on the interlayer insulating film and the lower electrode contact hole;
Depositing a second conductive layer on the first conductive layer to gap fill the lower electrode contact hole;
Anisotropically etching the first and second conductive layers to form a first lower electrode contact having a predetermined thickness under the lower electrode contact hole;
Forming a spacer covering an upper surface of the first conductive layer etched on sidewalls of the lower electrode contact hole;
Sequentially depositing a third conductive film and a gap fill insulating film on the interlayer insulating film, the spacer and the first lower electrode contact, and then performing a planarization process until the upper surface of the interlayer insulating film is exposed;
Selectively etching the interlayer insulating layer, the third conductive layer, and the gapfill insulating layer to form a lower electrode contact to which the first lower electrode contact and the third conductive layer are connected;
Method of manufacturing a phase change memory device comprising a.
The method of claim 1,
Forming the lower electrode contact hole
Depositing the interlayer insulating film on a substrate on which a lower structure is formed;
Etching the interlayer insulating layer to expose the lower structure to form the lower electrode contact hole;
Method of manufacturing a phase change memory device comprising a.
The method of claim 2,
The substructure is
And a stack of an active region, a diode, and a metal silicide layer formed on the substrate.
The method of claim 1,
The lower electrode contact hole
A method of manufacturing a phase change memory device, characterized in that it is formed in a cylindrical shape using an anisotropic etching process.
The method of claim 1,
The first conductive film is
Phase change memory device characterized in that the lower portion of the first lower electrode contact is formed using any one of tungsten (W), titanium (Ti), tantalum (Ta), aluminum (Al), and copper (Cu). Method of preparation.
The method of claim 1,
The second conductive film is
Forming an upper portion of the first lower electrode contact using any one of tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), aluminum nitride (AlN) and titanium aluminum nitride (TiAlN). A method of manufacturing a phase change memory device.
The method of claim 1,
The first and second conductive film
And a sputtering process, a chemical vapor deposition process, and an atomic layer deposition process.
The method of claim 2,
The first lower electrode contact is
The method of claim 1, wherein the first and second conductive layers are electrically connected to each other to be in contact with the upper surface of the lower structure.
The method of claim 1,
The first and second conductive film
And a etch selectivity with respect to the interlayer insulating film.
The method of claim 1,
The constant thickness
And 15 to 25% of the depth of the lower electrode contact hole.
The method of claim 1,
Forming the spacer
Depositing a spacer film on the interlayer insulating film and the first lower electrode contact;
And anisotropically etching the spacer film to expose an upper surface of the interlayer insulating layer and an upper surface of the first lower electrode contact.
The method of claim 11,
The spacer membrane
And etching selectivity with respect to the second conductive layer.
The method of claim 1,
The third conductive film is
The method of manufacturing the phase change memory device as claimed in claim 2, wherein the resistance is made uniform by using a material substantially the same as that of the second conductive layer, and the second conductive layer is electrically connected to the second conductive layer.
The method of claim 1,
Forming the lower electrode contact
The phase change of the interlayer insulating film, the spacer, and the gap fill insulating film are etched using the first kind of gas plasma as an etching gas, and the third conductive film is left to form the lower electrode contact in the form of a double plug. Method of manufacturing a memory device.
The method of claim 14,
The first kind of gas
A method of manufacturing a phase change memory device, characterized in that any one selected from hydrogen, nitrogen, and a compound of oxygen and fluorine.
The method of claim 1,
Forming the lower electrode contact
The third conductive layer is etched using the second kind of gas plasma as an etching gas, and the interlayer insulating layer, the spacer layer, and the gap fill insulating layer remain to form the lower electrode contact hole having a ring-shaped recess, and partially. And forming a lower electrode contact in a confined form.
17. The method of claim 16,
The second kind of gas
A method of manufacturing a phase change memory device, characterized in that any one selected from hydrogen, nitrogen, oxygen and chlorine compounds.
The method of claim 1,
After forming the lower electrode contact
Depositing a phase change material film on the etched interlayer insulating film, the gap fill insulating film, and the lower electrode contact;
And depositing a fourth conductive layer on the phase change material layer.
The method of claim 18,
The fourth conductive film is
A material for the upper electrode, including any one of polysilicon, a metal, and a conductive metal nitride doped with impurities;
And a sputtering process, a chemical vapor deposition process, and an atomic layer deposition process.

Images