KR20110064114A - LCD Display - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device having a pattern for compensating for a difference in luminance between left and right pixels based on data lines in a liquid crystal display device for driving dot inversion. The liquid crystal display according to the present invention comprises: data lines and gate lines crossing each other; Pixel electrodes arranged in two columns between the adjacent data lines to form a matrix; And a liquid crystal display panel including thin film transistors connected to the pixel electrodes, each of two pixel electrodes disposed to the right of the m (m is a positive integer) th data line in each of the odd horizontal display lines of the liquid crystal display panel. And the data voltages sequentially supplied from the m th data line, and the two pixel electrodes disposed to the left of the m th data line in each of the even horizontal display lines of the liquid crystal display panel are sequentially from the m th data line. Charging the data voltage supplied to the. According to the present invention, the change in the aperture ratio hardly occurs, and the deterioration in image quality such as uneven brightness difference due to asymmetric capacitance can be prevented.

Description

Liquid Crystal Display {LIQUID CRYSTAL DISPLAY}

The present invention relates to a liquid crystal display device for driving a liquid crystal display panel in a dot inversion by using a source drive integrated circuit (IC) for outputting a data voltage whose polarity is inverted in the column inversion. In particular, the present invention relates to a liquid crystal display device having a pattern for compensating for a difference in luminance between left and right pixels based on data lines in a liquid crystal display device for driving dot inversion.

The liquid crystal display of the active matrix driving method displays a moving image using a thin film transistor (hereinafter referred to as TFT) as a switching element. Liquid crystal displays can be miniaturized compared to cathode ray tubes (CRTs), which are applied to displays in portable information devices, office equipment, computers, etc., as well as televisions, and are rapidly replacing cathode ray tubes.

The liquid crystal display device includes a liquid crystal display panel, a backlight unit for irradiating light to the liquid crystal display panel, a source drive integrated circuit (IC) for supplying data voltage to data lines of the liquid crystal display panel, and a gate of the liquid crystal display panel. And a gate drive IC for supplying a gate pulse (or scan pulse) to the lines (or scan lines), a control circuit for controlling the ICs, a light source driving circuit for driving a light source of the backlight unit, and the like.

Thanks to the rapid development of the process technology and the driving technology of the liquid crystal display device, the manufacturing cost of the liquid crystal display device is lowered and the image quality is greatly improved. It is necessary to further improve the power consumption, image quality, and manufacturing cost of the liquid crystal display device in order to meet low power consumption and low cost of the information terminal.

As a technical requirement, a double rate drive (DRD) for transferring information to two pixels connected to different gate lines through one data line has been proposed. In addition, a liquid crystal display device for driving a liquid crystal display panel in a dot inversion using a source drive integrated circuit which outputs a data voltage whose polarity is inverted in column inversion has been proposed. However, in such a DRD dot inversion driving method, a luminance difference occurs between the left and right pixels with respect to the data line. This luminance difference is a necessary problem to overcome because it causes a screen failure.

An object of the present invention is to provide a liquid crystal display device that can improve the power consumption and image quality. Another object of the present invention is a capacitance for compensating for a luminance difference occurring in left and right pixels based on a data line in a structure in which information is transmitted to two pixels connected to different gate lines through one data line to improve power consumption. There is provided a liquid crystal display device having a pattern.

In order to achieve the above object, the liquid crystal display according to the present invention comprises: data lines and gate lines crossing each other; Pixel electrodes arranged in two columns between the adjacent data lines to form a matrix; And a liquid crystal display panel including thin film transistors connected to the pixel electrodes, each of two pixel electrodes disposed to the right of the m (m is a positive integer) th data line in each of the odd horizontal display lines of the liquid crystal display panel. And the data voltages sequentially supplied from the m th data line, and the two pixel electrodes disposed to the left of the m th data line in each of the even horizontal display lines of the liquid crystal display panel are sequentially from the m th data line. Charging the data voltage supplied to the.

a first dummy pattern branching from an m + 1 th data line and facing a portion of adjacent pixel electrodes among the two pixel electrodes disposed on the right side of the m th data line; The semiconductor device may further include a second dummy pattern branched from an m−1 th data line to face a portion of adjacent pixel electrodes among the two pixel electrodes disposed on the left side of the m th data line.

The first dummy pattern branches from the m + 1 th data line and branches from the data electrode for supplying data voltage to a pixel electrode which is in contact with one of the two pixel electrodes disposed on the left side of the m + 1 th data line. It is characterized by.

The second dummy pattern is branched from the m-1 th data line and branched from the data electrode for supplying a data voltage to a pixel electrode which is in contact with one of the two pixel electrodes disposed on the right side of the m-1 th data line. It is characterized by.

The polarities of the data voltages charged in the two pixel electrodes disposed on the right side of the m-th data line and the two pixel electrodes disposed on the left side are the same.

According to the present invention, the polarity of the data voltages charged in the liquid crystal cells connected to one data line can be controlled to be equal to the amount of data charging in the liquid crystal sections and the power consumption of the source drive IC can be reduced. Accordingly, the present invention can prevent image quality degradation such as luminance unevenness and color distortion caused by non-uniformity of data charge caused by the conventional inversion method, and reduce the number of polarity reversal of data voltage to consume the source drive IC. Power can be reduced. In addition, the present invention can reduce the number of data lines and the channel number of source drive ICs by using TFT connection relationships in which liquid crystal cells adjacent to the left and right share one data line. In the present invention, the change in the aperture ratio hardly occurs, and ΔVrms is drastically reduced to prevent deterioration in image quality such as uneven brightness difference due to asymmetric capacitance.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 1 to 4. 1 is a schematic view showing the structure of a liquid crystal display device according to the present invention.

Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal display panel on which a pixel array 10 is formed, a source drive IC 12, and a timing controller 11. A backlight unit for uniformly irradiating light onto the liquid crystal display panel may be disposed below the liquid crystal display panel.

The liquid crystal display panel includes an upper glass substrate and a lower glass substrate facing each other with a liquid crystal layer interposed therebetween. The pixel array 10 is formed in the liquid crystal display panel. The pixel array 10 displays video data including liquid crystal cells arranged in a matrix by a cross structure of data lines and gate lines. The lower glass substrate of the pixel array 10 includes data lines, gate lines, thin film transistors (TFTs), a pixel electrode of a liquid crystal cell connected to the TFT, and a storage capacitor connected to the pixel electrode of the liquid crystal cell. , Cst) and the like. Each of the liquid crystal cells of the pixel array 10 is driven by the voltage difference between the pixel electrode charging the data voltage through the TFT and the common electrode to which the common voltage is applied to display an image of the video data by adjusting the transmission amount of light. . A detailed structure of the pixel array 10 will be described in detail with reference to FIG. 2.

A black matrix, a color filter, and a common electrode are formed on the upper glass substrate of the liquid crystal display panel. The common electrode is formed on the upper glass substrate in the case of the vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and in-plane switching (IPS) mode and fringe field switching (FFS) mode. In the case of the same horizontal electric field driving method, the pixel electrode is formed on the lower glass substrate together with the pixel electrode.

A polarizing plate is attached to each of the upper glass substrate and the lower glass substrate of the liquid crystal display panel, and an alignment layer for setting the pre-tilt angle of the liquid crystal is formed.

The liquid crystal display device of the present invention can be implemented in any liquid crystal mode as well as the TN mode, VA mode, IPS mode, FFS mode. The liquid crystal display of the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display. In the transmissive liquid crystal display device and the transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The source drive ICs 12 are mounted on a tape carrier package (TCP) 15 and bonded to a lower glass substrate of a liquid crystal display panel by a tape automated bonding (TAB) process, and a source printed circuit board (PCB) 14. Is connected to. The source drive ICs 12 may be adhered to the lower glass substrate of the liquid crystal display panel by a chip on glass (COG) process. The data output channels of each of the source drive ICs 12 are connected 1: 1 to the data lines of the pixel array 10.

Each of the source drive ICs 12 receives digital video data from the timing controller 11. The source drive ICs 12 convert the digital video data into a positive / negative analog data voltage in response to a source timing control signal from the timing controller 11 to output data lines of the pixel array 10 through output channels. Supply to The source drive ICs 12 supply data voltages having opposite polarities to neighboring data lines under the control of the timing controller 11, and make the polarities of the data voltages supplied to the respective data lines equal to each other for one frame period. Keep it.

The gate driving circuit 13 sequentially supplies gate pulses to gate lines of the pixel array in response to the gate timing control signal from the timing controller 11. The gate driving circuit 13 is mounted on TCP and bonded to the lower glass substrate of the liquid crystal display panel by a TAB process, or directly formed on the lower glass substrate simultaneously with the pixel array 10 by a GIP (Gate In Panel) process. Can be. The gate driving circuit 13 may be disposed on both sides of the pixel array 10 or one side of the pixel array 10 as shown in FIG. 2.

The timing controller 11 supplies digital video data input from an external system board to the source drive ICs 12. The timing controller 11 generates a source timing control signal for controlling the operation timing of the source drive ICs 12 and a gate timing control signal for controlling the operation timing of the gate driving circuit 13. The timing controller 11 is mounted on the control PCB 16. The control PCB 16 and the source PCB 14 are connected through a flexible circuit board 17 such as a flexible flat cable (FFC) or a flexible printed circuit (FPC).

2 is a circuit diagram illustrating in detail a pixel array 10 according to an exemplary embodiment of the present invention. Referring to FIG. 2, the pixel array 10 may include data lines D1, D2, D3, D4,..., And gate lines G1, G2, G3, G4,. TFTs T11, T12, and T13 for supplying the pixel electrodes P11, P12, P13, P14, ... Pij to the data lines D1, D2, D3, D4, ... in response to the pulse. , T14, ... Tij).

During the Nth (N is positive integer) frame period, only the positive analog data voltages are supplied from the source drive ICs 12 to the odd data lines D1, D3 ... D2m-1, D2m + 1. Only the negative analog data voltages are supplied from the source drive ICs 12 to the even data lines D2, D4 ... D2m. During the N + 1th frame period, only the negative analog data voltages are supplied from the source drive ICs 12 to the odd data lines D1, D3 ... D2m-1, D2m + 1, and the even data lines Only positive analog data voltages are supplied from the source drive ICs 12 to D2, D4 ... D2m.

The data voltage whose polarity is reversed by the column inversion method, the same polarity is continuously supplied to each of the data lines for one frame period due to the connection of the TFTs and the data lines, and the data voltages charged in the liquid crystal cells of the pixel array are Its polarity is reversed to horizontal two dots and vertical one dot inversion.

In each of the data lines D1, D2, D3, D4, ... in the odd horizontal display lines LINE1, LINE3, ..., LINE2p-1 of the pixel array 10, two pixels are disposed on the right side. The electrodes are connected to sequentially charge data voltages of the same polarity supplied from the same data line. In the even horizontal display lines LINE2, LINE4,..., And LINE2p of the pixel array 10, two pixel electrodes disposed on the left side of each of the data lines D1, D2, D3, D4,... Connected to sequentially charge data voltages of the same polarity supplied from the same data line.

Based on the general matrix arrangement, the TFTs T11, T12, T13, T14, ..., Tij and data lines respectively allocated to the pixel electrodes P11, P12, P13, P14, ..., Pij Looking at the connection between the (D1, D2, D3, D4, ...) in more detail as follows. Here, m (data line number related), n (gate line number related), p (display line number related), i (row number related), j (column number related), etc. mean a positive integer. Referring to FIG. 2, a plurality of data lines are arranged and two pixel electrodes are arranged between neighboring data lines. Here, since the gate line does not significantly contribute to the arrangement structure, description thereof is omitted. Since the description is based on the image information displayed in the case of one frame, only the data line is considered from which data line each pixel receives information when all the gate lines are sequentially selected.

In each of the odd horizontal display lines LINE1, LINE3,..., And LINE2p-1, TFTs and pixel electrodes existing between the m th data line and the m + 1 th data line are sequentially disposed from the m th data line. Charge the supplied data voltage. In addition, the pixel electrodes existing between the m th data line (m is a positive integer) and the m th data line in each of the even horizontal display lines LINE2, LINE4,. Charges the data voltage sequentially supplied from the data line. That is, the pixel electrodes connected to the m th data line are P (2p-1,2m-1) and P (2p-1,2m) and P (2p, 2 (m-) in a matrix arrangement as shown in FIG. Pixel electrodes corresponding to 1) -1) and P (2p, 2 (m-1)). Then, TFTs for switching the current path between these pixel electrodes and the mth data line are connected. That is, T (2p-1,2m-1) and T (2p-1,2m) and T (2p, 2 (m-1) -1) and T (2p, 2 (m-1)) TFTs. For example, from the third data line, P15 through T15, P16 through T16, P35 through T35, P36 through T36, P23 through T23, P24 through T24, P43 through T43 Through this T44, P44, etc. are supplied with data voltages. Here, when calculating the matrix position, if the value is '0' or less, it means that there is no connection.

In the liquid crystal display according to the first embodiment, since the polarities of the data voltages charged in the liquid crystal cells connected to one data line are the same, the power consumption of the source drive IC may be reduced, and the amount of data charging of each of the liquid crystal cells may be reduced. It can be made uniform. Therefore, the present invention can prevent deterioration in image quality such as luminance unevenness and color distortion caused by unevenness of the amount of data filling caused by the existing inversion method. In addition, the present invention can reduce the number of data lines and the number of channels of source drive ICs by using a TFT connection relationship in which liquid crystal cells adjacent to the left and right share one data line, and further reduce the manufacturing cost of the liquid crystal display device. Can be.

In the first embodiment described above, when one of the data lines is used as a reference, the data voltage is supplied to the pixel electrode adjacent to the data line and the pixel electrode in direct contact with the data line. That is, based on one pixel electrode, a data line passes through one side and no data line passes through the opposite side. As a result, the capacitance Cdp between the pixel electrode and the data line has a left-right asymmetric structure. As the column inversion is driven in this state, the pixel electrode changes in the Vrms value due to the capacitance formed between one neighboring data line.

In addition, in the first embodiment, from the physical arrangement state side, pixels having data voltages supplied by the corresponding data lines are adjacent to one side, and pixels having data voltages supplied by the other data lines are opposite to one another. It has an adjacent state. In other words, when viewed based on the data line, the capacitance between the left pixel electrode and the right pixel electrode also have different values. In addition, since the pixel arrangement is the same for each odd display line and the same for each even display line, the Vrms values of pixel voltages due to capacitance are different in units of four pixel electrodes.

In FIG. 2, the pixel electrodes P24, P25, P34, and P35 will be described in detail with reference to the data line D3.

Pixel voltages are applied to the pixel electrodes P24 and P35 through the data line D3. Therefore, when the data line D3 has a positive value, the pixel electrodes P24 and P35 are charged with (+). On the other hand, the pixel voltage is applied to the pixel electrode P25 through the data line D4 and the pixel electrode P34 to the data line D2. Therefore, the data lines D2 and D4 have a negative value, so that the pixel electrodes P25 and P34 are charged with negative (-).

The pixel voltages P24, P25, P34, and P35 are all adjacent to the data line D3, but Cdp1, Cdp2, Cdp3, and Cdp4 are formed therebetween. Therefore, the capacitances Cdp1 and Cdp4 between the data lines D3 having the positive charge signal and the pixel electrodes P24 and P35 charged with the positive charge are charged to the data lines D3 and (-) having the positive charge signal. It is relatively smaller than the capacitances Cdp2 and Cdp3 between the pixel electrodes P25 and P34. Therefore, the pixel electrodes P24 and P35 have a large Vrms of the pixel voltage due to the weak capacitance, and the pixel electrodes P25 and P34 have a small Vrms of the pixel voltage due to the strong capacitance.

In the example of the actual product of the liquid crystal display according to Example 1 described above, ΔVrms, which is the difference between the strong Vrms and the weak Vrms, was measured at about 28.2 mV. Such an imbalance of Vrms causes a difference in luminance between the pixel electrodes. Therefore, a result may not be solved rather than the luminance non-uniformity problem to be obtained in the first embodiment. Thus, in Embodiment 2 of the present invention, a structure of a liquid crystal display device which solves a problem of luminance unevenness due to asymmetry of capacitance generated in Embodiment 1 will be described. 3 is a circuit diagram illustrating in detail a pixel array according to a second exemplary embodiment of the present invention. FIG. 4 is a diagram illustrating an actual pattern of a data line, a gate line, a TFT, and a pixel electrode of FIG. 3.

3 and 4, the arrangement and connection structure of the data line DL, the gate line GL, the thin film transistor TFT, and the pixel electrode PXL are basically the same as those of the first embodiment. If there is a difference, in the second embodiment, a dummy pattern for further forming a compensation capacitance ACdp symmetrical to the asymmetric capacitance Cdp generated between the pixel electrode PXL and the adjacent data line DL is formed. DUM). In particular, the compensation capacitance ACdp is the difference between the dummy pattern DUM and the pixel electrode PXL branched from the data line DL, which is opposite to the polarity of the data line DL on which the asymmetric capacitance Cdp is formed. It is formed between.

In more detail, in the case of the matrix structure illustrated in FIG. 3, pixel electrodes proximate to the right side of the m th data line are assisted by the first dummy pattern DUM1 branching from the m + 1 th data line. To form capacitance. The pixel electrodes adjacent to the left side of the m-th data line form an auxiliary capacitance by the second dummy pattern DUM2 branching from the m-th data line.

Various methods can be considered to form the first and second dummy patterns DUM1 and DUM2. However, in the present embodiment, the most preferred method is presented as follows. The first dummy pattern DUM1 branches from the m + 1 th data line and supplies a data voltage to a pixel electrode which is adjacent to one of the two pixel electrodes arranged on the left side of the m + 1 th data line in the odd display line. It is preferable to have a wiring shape that branches vertically from the data electrode. In particular, a first dummy pattern DUM1 is formed in each of the pixels connected to the TFTs having the data electrodes for supplying the data voltages and the pixels disposed thereunder.

On the other hand, the second dummy pattern DUM2 branches from the m-1 th data line and applies a data voltage to a pixel electrode which is adjacent to one of the two pixel electrodes arranged on the right side of the m-1 th data line in the even-numbered display line. It is preferable to have a wiring shape that branches vertically from the data electrode to be supplied. In particular, a second dummy pattern DUM2 is formed in each of the pixels connected to the TFTs having the data electrodes for supplying the data voltages and the pixels disposed thereunder.

Another method for reducing the asymmetric capacitance mentioned in Embodiment 1 is to set the distance between the data line and the pixel electrode. However, this method inevitably reduces the size of the pixel electrode, and in order to reduce the capacitance, the pixel electrode becomes smaller, which causes another problem such as lowering of the aperture ratio. FIG. 5 is a graph illustrating a result of measuring a relationship between ΔVrms and an aperture ratio change according to a separation distance between a data line and a pixel electrode. As shown in FIG. 5, although the distance between the data line and the pixel electrode can be designed to reduce the ΔVrms value from 28.2 mV to 10.0 mV, the adverse effect of greatly reducing the aperture ratio from 53.5% to 48.2% is obtained. Occurs.

However, in the liquid crystal display device according to the second embodiment of the present invention,? Vrms can be significantly reduced while the change of the aperture ratio hardly occurs. In practice, the separation distance between the pixel electrode and the data line is 5.2 to 7.0 μm, the separation distance between the pixel electrode PXL and the dummy pattern DUM is about 4 to 5 μm, and the length of the dummy pattern DUM is about 10 to 15 μm. When designed to such a degree, the aperture ratio did not change, and ΔVrms was reduced to 7.3 mV.

In Example 2, the dummy pattern DUM has been described as being formed in the shape of a wiring branched from the data line, but the pattern may be variously set as necessary. That is, any form that can form an auxiliary capacitance with the pixel electrode is possible. In addition, even in the form of wiring, various sizes can be set without being limited to the size described above.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a schematic view showing the structure of a liquid crystal display device according to the present invention.

2 is a circuit diagram showing in detail a pixel array according to a first embodiment of the present invention.

3 is a circuit diagram showing a pixel array according to Embodiment 2 of the present invention;

4 is a view showing an actual pattern of a data line, a gate line, a TFT, and a pixel electrode according to FIG. 3;

FIG. 5 is a graph illustrating a result of measuring a relationship between ΔVrms and an aperture ratio change according to a separation distance between a data line and a pixel electrode. FIG.

<Explanation of symbols for main parts of the drawings>

10: pixel array 11: timing controller

12: source drive IC 13: gate driving circuit

14: Source PCB 15: Source Drive IC

16: Control PCB 17: Flexible Circuit Board

D1, D2, D3, D4, DL: Data lines G1, G2, G3, G4, GL: Gate lines

T11, T12, T13, T14, TFT: Thin Film Transistor

P11, P12, P13, P14, PXL: pixel electrode DUM: dummy pattern

DUM1: first dummy pattern DUM2: second dummy pattern

Cdp: Asymmetric Capacitive ACdp: Auxiliary Capacitance

Claims (6)

Data lines and gate lines crossing each other; Pixel electrodes arranged in two columns between the adjacent data lines to form a matrix; And A liquid crystal display panel including thin film transistors connected to the pixel electrodes; In each of the odd horizontal display lines of the liquid crystal display panel, two pixel electrodes disposed to the right of the m (m is a positive integer) data line charge data voltages sequentially supplied from the m data line. And two pixel electrodes disposed to the left of the m-th data line in each of the even horizontal display lines of the liquid crystal display panel to charge data voltages sequentially supplied from the m-th data line. The method of claim 1, a first dummy pattern branching from an m + 1 th data line and facing a portion of adjacent pixel electrodes among the two pixel electrodes disposed on the right side of the m th data line; and a second dummy pattern branching from an m-1 th data line and facing a portion of adjacent pixel electrodes among the two pixel electrodes disposed on the left side of the m th data line. Device. The method of claim 2, The first dummy pattern is branched from the m + 1th data line and branched from a data electrode for supplying a data voltage to a pixel electrode which is in contact with one of the two pixel electrodes disposed on the left side of the m + 1th data line. Liquid crystal display device characterized in that. The method of claim 2, The second dummy pattern is branched from the m-1 th data line and branched from the data electrode for supplying a data voltage to a pixel electrode which is in contact with one of the two pixel electrodes disposed on the right side of the m-1 th data line. Liquid crystal display device characterized in that. The method of claim 1, Source drive ICs for supplying the data voltages whose polarities are inverted in column inversion to the data lines; And And a gate driving circuit for sequentially supplying gate pulses to the gate lines. The method of claim 1, And the polarities of the data voltages charged in the two pixel electrodes disposed on the right side of the m-th data line and the two pixel electrodes disposed on the left side are the same.

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