KR20110024783A - How to Design Integrated Circuits and Tyssels in Integrated Circuits - Google Patents

Abstract

PURPOSE: An integrated circuit and a method of designing tie cells in the integrated circuit are provided to locally distribute a plurality of protection cells in an integrated circuit, thereby increasing performance of an integrated circuit by reducing fan out of the protection cells. CONSTITUTION: The first power(VDD) is provided to the first pads(112,114). The second power(VSS) is provided to the second pads(122,124,126). A plurality of protection cells(132,134,142,144,146) is connected to the first pads or the second pads. The protection cells are locally distributed in the integrated circuit. Standard cells are connected to the protection cells respectively.

Description

Integrated Circuit and Method of designing the tie cells within the Integrated Circuit

TECHNICAL FIELD The present invention relates to semiconductor devices, and more particularly, to integrated circuits and methods of designing tissels within integrated circuits.

In general, electrostatic discharge (ESD) is generated when a user is electrostatically charged by friction or induction. Integrated circuits, particularly ICs formed from MOS transistors, are vulnerable to such ESD. The ESD may be delivered to input / output pads, power pins, or other IC pads inside the IC, where such ESD may cause catastrophic damage to semiconductor junctions, dielectrics, interconnects, or internal components of the IC. Can give

Generally, in the semiconductor manufacturing process of 90 nm or 65 nm, since the gate oxide film is thin, a circuit for protecting the gate of the transistor from static electricity is required. A large scale integrated circuit is designed using a large number of transistors, and a first power supply VDD or a second voltage VSS is applied to a pin of a gate of a designed transistor or a standard cell.

The gate of the transistor connected to the first power supply VDD is called a tie up, and the gate of the transistor connected to the second power source VSS is called a tie down. Thus, there is a need for a procedure and function to protect the gate of the transistor from static electricity when a tie up or tie down occurs.

An object of the present invention is to provide an integrated circuit and a method of designing ti cells within the integrated circuit, which can reduce the fanout of the Tyssel.

According to an embodiment of the present disclosure, an integrated circuit according to an embodiment of the present invention may include first pads to which first power is supplied, second pads to which second power is supplied, the first pads, or the second pad. And a plurality of protection cells that are connected to each other and disposed in the integrated circuit, and a plurality of standard cells that are correspondingly connected to each of the plurality of protection cells.

The plurality of protection cells may include a plurality of first protection cells, each of which is connected to a corresponding one of the plurality of first pads, and each of the plurality of pads corresponding to one of the plurality of second pads. It may include a plurality of second protection cells connected with.

According to another aspect of the present invention, there is provided a method of designing protection cells in an integrated circuit, by disposing standard cells in an integrated circuit, by locally distributing a plurality of protection cells in the integrated circuit. And arranging, and connecting the plurality of protection cells that are geographically dispersed and the deployed standard cells.

The step of connecting the arranged standard cells may be divided into a plurality of groups by locally classifying the standard cells disposed in the integrated circuit, and belonging to the plurality of groups and a plurality of locally distributed protection cells It may include the step of connecting with the standard cell.

The method of designing protection cells in the integrated circuit may further include adjusting the number of locally distributed ti cells connected to the standard cells, and connecting the ti cells with the standard cells according to the adjusted number of ti cells. Can be.

According to an embodiment of the present disclosure, a method of designing a tissel in an integrated circuit and an integrated circuit may improve the performance of an integrated circuit by reducing a fanout of the tissel by distributing a plurality of ticells locally. It has an effect.

Hereinafter, the technical objects and features of the present invention will be apparent from the description of the accompanying drawings and the embodiments. Looking at the present invention in detail.

1 is a conceptual diagram of an integrated circuit design for electrostatic discharge (ESD) protection according to an embodiment of the present invention. Referring to FIG. 1, a plurality of input pins 110, 112, 114, 122, 124, 126, a plurality of tie cells (TIE CELLS, 132, 134, 142, 144, 146), and a plurality of standard cells 152, 154, 162, 164, 172, 174, 182, 184, 192, and 194 are included.

The plurality of input pins include first power input pins 112 and 114, and second power input pins 122, 124 and 126. A first power supply voltage (eg, VDD) may be input to each of the first power input pins 112 and 114, and a second power supply voltage (eg, VSS) may be input to the second power input pins 122, 124 and 126.

The plurality of ticells 132, 134, 142, 144, and 146 function as protection cells that protect the gates of the plurality of standard cells from static electricity.

The plurality of tie cells 132, 134, 142, 144 and 146 include TIEHI CELL 132, 134 and TIELOW CELL 142, 144, 146.

The Taihai cell supplies the first power supply voltage VDD to the gate of the transistor included in the standard cell, and the tie low cell supplies the second power supply voltage VSS to the gate of the transistor included in the standard cell.

Each of the plurality of tie-hai cells 132 and 134 is connected to a corresponding one of the first power input pins 112 and 114. For example, the first tie high cell 132 is connected to the first power first input pin 112.

In addition, each of the plurality of tie cells 142, 144, and 146 is connected to a corresponding one of the second power input pins 122, 124, and 126. For example, the first tie cell 142 is connected to the second power first input pin 124.

FIG. 2A shows a circuit diagram of the Taihai cell shown in FIG. 1. The other sub cells 132 and 134 illustrated in FIG. 1 may have the same structure as shown in FIG. 2A.

Referring to FIG. 2A, the tie-high cell 132 includes a first NMOS transistor 210 and a first PMOS transistor. The source 216 of the first NMOS transistor 210 is connected to the second power supply VSS, and the gate 212 and the drain 214 are connected to the gate 222 of the first PMOS transistor 220.

The source 224 of the first PMOS transistor 220 is connected to a first power supply VDD, and the drain 226 of the first PMOS transistor 220 is connected to a gate of a standard cell. do.

FIG. 2B shows a circuit diagram of the tie cell shown in FIG. 1. The tire cells 142, 144, and 146 shown in FIG. 1 may all have the same structure as shown in FIG. 2A.

Referring to FIG. 2B, the tie cell 142 includes a second PMOS transistor 230 and a second NMOS transistor 240. The source 234 of the second PMOS transistor 230 is connected to the first power source VDD, and the gate 232 and the drain 236 of the second PMOS transistor 230 are the gates of the second NMOS transistor 240. 242 is connected.

The source 246 of the second NMOS transistor 240 is connected to a second power supply VSS, and the drain 244 of the NMOS transistor 240 is connected to a gate of a standard cell. . The tie-high cell and the tie-low cell are used to prevent the first power source VDD or the second power source VSS from being directly connected to the gate of the standard cell.

A plurality of standard cells may be distributed inside an integrated circuit, and may be divided into several groups of adjacent standard cells as a group. For example, a number of standard cells designed inside an integrated circuit are divided into a first group 152, 154, a second group 162, 164, a third group 172, 174, a fourth group 182, 184, and a fifth group 192, 194. Can be.

One of the plurality of tie-high cells supplies a first power supply VDD to a gate of a transistor included in standard cells belonging to any one of the plurality of groups. For example, the first tie-high cell 132 may supply the first power VDD to the gate of the transistor included in the standard cells 182 and 184 belonging to the fourth group.

One of the plurality of tie-cells supplies a second power supply VSS to a gate of a transistor included in standard cells belonging to any one of the plurality of groups. For example, the first tie cell 142 may supply a second power source VSS to a gate of a transistor included in the standard cells 152 and 154 belonging to the first group.

As shown in FIG. 1, in order to compensate for the problem of increased fanout, a plurality of tissels are formed to be distributed by region in the integrated circuit. For example, the plurality of ti cells may be formed to be uniformly distributed in the integrated circuit for each region. Each of the plurality of ti cells is connected to supply a first power source or a second power source to adjacent standard cells.

FIG. 3 illustrates a conceptual diagram of designing the tissels illustrated in FIG. 1 in an integrated circuit. Referring to FIG. Referring to FIG. 3, a plurality of first power rails VDD1 to VDD5 and a plurality of second power rails VSS1 to VSS4 are formed in an integrated circuit.

The tie high cell TIEHI CELL is formed between the first power source first rail VDD1 and the second power source first rail VSS1. The first standard cell 302 is formed between the second power supply first rail VSS1 and the first power supply second rail VDD2, and the second standard cell 304 is the first power supply second rail VDD2. And a second power source are formed between the second rails. The first standard cell 302 and the second standard cell 304 are connected to adjacent Tie HI cells.

The tie cell (TIELOW CELL) is formed between the second power source third rail VSS3 and the first power source fourth rail VDD4. The third standard cell 312 is formed between the first power source third rail VDD3 and the second power source third rail VSS3, and the fourth standard cell 314 is the first power source fourth rail and the second power source. It is formed between the power source fourth rail VSS4. The third standard cell 312 and the fourth standard cell 314 are connected to a tie low cell.

As described above, the plurality of ti cells in the integrated circuit according to the embodiment of the present invention are distributed by regions to supply the first power source VDD or the second power source VSS to the standard cells.

4 is a flowchart illustrating a method of designing tissels inside an integrated circuit for ESD protection according to an exemplary embodiment of the present invention. Referring to FIG. 4, a netlist netlist is first created (S410). Here, the netlist refers to text for a place and route tool (PNR) tool for arranging or designing standard cells based on time delay information for the standard cells. The PNR tool is a kind of software for designing the inside of the integrated circuit.

Next, the standard cells are placed according to the netlist using the PNR tool (S420). At this time, the standard cells are connected to each other according to the netlist, and the first power source VDD and the second power source VSS are connected to the standard cells.

Next, the place of the standard cells is adjusted according to CTS (Clock Tree Synthesis) (S430). It is to adjust the layout of the standard cells in consideration of the influence of the clock. For example, the arrangement of the standard cells is adjusted to avoid the malfunction of the standard cells with respect to the operation clock.

Next, tie cells distributed locally to satisfy design rules and process conditions are connected to the standard cells (S440). At this time, in order to reduce the fanout of the tissels, the tissels are locally distributed inside the integrated circuit.

For example, according to the CTS (Clock Tree Synthesis) forms a group of geographically divided standard cells in the integrated integrated circuit place. The Ticells are then connected to regionally separated standard cells. Therefore, since a single cell supplies the first power source VDD or the second power source VSS only to the regionally divided standard cells, the fan out can be reduced, thereby improving the performance (eg, operating speed) of the integrated circuit. .

Next, the number of locally distributed ti cells connected to the standard cells is adjusted in consideration of the integrated circuit area, and the ti cells and the standard cells are connected according to the adjusted number of ti cells (S450). In other words, the number of connected Ti-cells can be adjusted in consideration of the integrated circuit area and the fan-out side. For example, simply increasing the number of ticells to reduce the fanout exceeds the integrated circuit area, so that the number of ticells that can minimize the fanout can be determined in consideration of the integrated circuit area.

In operation S460, the integrated circuit designed according to the adjusted number of ticells is satisfied. If no verification results in an error, the integrated circuit design is completed. On the other hand, if an error occurs as a result of verification, steps S440 and S450 are repeated.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a conceptual diagram of an integrated circuit design for ESD protection according to an embodiment of the present invention.

FIG. 2A shows a circuit diagram of the Taihai cell shown in FIG. 1.

FIG. 2B shows a circuit diagram of the tie cell shown in FIG. 1.

FIG. 3 illustrates a conceptual diagram of designing the tissels shown in FIG. 1 into an integrated circuit. Referring to FIG.

4 is a flowchart illustrating a method of designing tissels inside an integrated circuit for ESD protection according to an exemplary embodiment of the present invention.

Claims (5)

In an integrated circuit, First pads to which first power is supplied; Second pads to which second power is supplied; A plurality of protection cells connected to the first pads or the second pads and distributed in the integrated circuit; And And a plurality of standard cells connected corresponding to each of the plurality of protection cells. The method of claim 1, wherein the plurality of protection cells, A plurality of first protection cells each of which is connected to a corresponding one of the plurality of first pads; and And a plurality of second protection cells each connected to a corresponding one of the plurality of second pads. Disposing standard cells in an integrated circuit; Distributing the plurality of protection cells locally in the integrated circuit; And Connecting the plurality of guard cells distributed locally with the deployed standard cells. The method of claim 3, wherein the method of designing protection cells in the integrated circuit comprises: Adjusting the number of locally distributed ti cells connected to the standard cells, and connecting the ti cells to the standard cells according to the adjusted number of ti cells. How to. The method of claim 3, wherein the connecting of the arranged standard cells comprises: Dividing the standard cells arranged in the integrated circuit into a plurality of groups by locally classifying the standard cells; And Connecting to each of a plurality of locally distributed guard cells and the standard cells belonging to a corresponding one of the plurality of groups.

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