KR20110021444A - 3D semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

A three-dimensional semiconductor memory device and a method of manufacturing the same are provided. The 3D semiconductor memory device includes a substrate including a first contact region and a second contact region spaced apart from each other, and a plurality of conductive patterns stacked in turn, each of the conductive patterns comprising: a wiring portion parallel to an upper surface of the substrate; A contact extension extending from one end of the wiring portion along a direction penetrating through the upper surface of the substrate, wherein at least one of the conductive patterns is disposed in the first contact region, and at least one of the conductive lines The contact extension is disposed in the second contact region.

Description

Three dimensional semiconductor memory device and method for fabricating the same

The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly, to a semiconductor memory device having a three-dimensional structure and a manufacturing method thereof.

There is a demand for increasing the integration of semiconductor devices in order to meet the high performance and low price demanded by consumers. In the case of semiconductor memory devices, since the degree of integration is an important factor in determining the price of a product, an increased degree of integration is particularly required. In the case of the conventional two-dimensional or planar semiconductor memory device, since the degree of integration is mainly determined by the area occupied by the unit memory cell, it is greatly influenced by the level of the fine pattern formation technique. However, since expensive equipment is required for pattern miniaturization, the degree of integration of a two-dimensional semiconductor memory device is increasing but is still limited.

In order to overcome this limitation, three-dimensional semiconductor memory devices having three-dimensionally arranged memory cells have been proposed. However, for mass production of 3D semiconductor memory devices, a process technology capable of realizing reliable product characteristics while reducing manufacturing cost per bit than that of 2D semiconductor memory devices is required.

An object of the present invention is to provide a three-dimensional semiconductor memory device that can be easily integrated.

Another object of the present invention is to provide a method of manufacturing a three-dimensional semiconductor memory device that can be easily integrated.

The problem to be solved by the present invention is not limited to the above-mentioned problem, and other tasks not mentioned will be clearly understood by those skilled in the art from the following description.

In order to achieve the above object, a three-dimensional semiconductor memory device according to an embodiment of the present invention includes a substrate including a first contact region and a second contact region spaced apart from each other and a plurality of conductive patterns stacked in sequence Each of the conductive patterns may include a wiring portion parallel to an upper surface of the substrate and a contact extension portion extending from one end of the wiring portion along a direction penetrating through the upper surface of the substrate, wherein the at least one contact extension portion of the conductive patterns may be formed. The contact extension is disposed in the first contact region, and the contact extension of at least another one of the conductive lines is disposed in the second contact region.

According to another aspect of the present invention, there is provided a method of manufacturing a 3D semiconductor memory device, which includes preparing a substrate including a cell array region between first and second contact regions, An opening having a bottom surface parallel to each other and sidewalls formed in each of the first and second contact regions, and including a plurality of conductive layers sequentially stacked, each of the conductive layers having a wiring portion parallel to the upper surface of the substrate; And contact extension parts extending from the both ends of the wiring part to the sidewalls of the opening, and each of the conductive layers recesses the contact extension part of the contact extensions to form a dummy extension part, wherein the dummy extension parts are different from each other. It is formed between the contact extension of the conductive films disposed in the layer.

According to the three-dimensional semiconductor memory device of the present invention, in a structure in which conductive patterns are stacked over a plurality of layers, contact extensions of odd layer conductive patterns and contact extensions of even layer conductive patterns are disposed in different contact regions. As a result, a margin for forming contact plugs or wires directly connected to the contact extensions may be secured. Accordingly, the degree of integration of the three-dimensional semiconductor memory device can be improved.

Advantages and features of the present invention, and methods for achieving them will be apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention belongs. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, the terms 'comprises' and / or 'comprising' mean that the stated element, step, operation and / or element does not imply the presence of one or more other elements, steps, operations and / Or additions. Also, in the present specification, when it is mentioned that a film is on another film or substrate, it means that it may be formed directly on another film or substrate or a third film may be interposed therebetween.

In addition, the embodiments described herein will be described with reference to cross-sectional and / or plan views, which are ideal exemplary views of the present invention. In the drawings, the thicknesses of films and regions are exaggerated for effective explanation of technical content. Accordingly, shapes of the exemplary views may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include variations in forms generated by the manufacturing process. For example, the etched regions shown at right angles may be rounded or have a predetermined curvature. Accordingly, the regions illustrated in the figures have schematic attributes, and the shape of the regions illustrated in the figures is intended to illustrate a particular form of region of the device and not to limit the scope of the invention.

The 3D semiconductor memory device according to example embodiments includes a cell array region and a contact region. Three-dimensional memory cells are formed in the memory cell array region, and contact plugs connecting the memory cells and peripheral circuits are formed in the contact region.

1 is a cross-sectional view of a 3D semiconductor memory device according to example embodiments.

Referring to FIG. 1, the substrate 10 includes a cell array region CAR and contact regions CR1 and CR2 disposed around the cell array region CAR. The contact region may include a first contact region CR1 positioned at one side of the cell array region CAR and a second contact region CR2 positioned at the other side of the cell array region CAR.

The protruding insulating pattern 11 is disposed on the contact area of the substrate 10. The protruding insulating pattern 11 may define an opening that exposes a part of the surface of the substrate 10. The protruding insulating pattern 11 may have a sidewall perpendicular to the substrate 10 or have an inclined sidewall. Sidewalls of the protruding insulating pattern 11 may be disposed on the first contact region CR1 and the second contact region CR2, respectively.

On the substrate 10 exposed by the protruding insulation pattern 11, a plurality of conductive patterns GL1 to GL6 are stacked to be spaced apart from each other. The gate structure is disposed. An interlayer insulating layer is formed between the conductive patterns GL1 to GL6.

Each of the conductive patterns GL1 to GL6 is disposed in the cell array region CAR and is disposed in the wiring portion IC parallel to the substrate 10, and is disposed in the contact regions CR1 and CR2 and with respect to the substrate 10. It may include an inclined contact extension (CT). Each of the conductive patterns GL1 to GL6 includes a contact extension CT extending from the first end of the wiring part IC and a dummy extension part CTCT extending from the second end of the wiring part IC. It may include.

The contact extension CT and the dummy extension DCT have different lengths. According to an embodiment, the length of the dummy extension DCT may be shorter than the length of the contact extension CT. The upper surface of the contact extension CT may be higher than the upper surface of the dummy extension DCT. The upper surface of the contact extension CT may be disposed at the same height as the upper surface of the protruding insulation pattern 11, and the contact extension CTs of the conductive patterns GL1 to GL6 may be formed by the contact plugs CP and the respective contact plugs CP. Connected. The dummy extension part DCT is electrically separated from the contact plug CP by the insulating film 64 and the interlayer insulating film 71.

As the wiring portions IC of the conductive patterns GL1 to GL6 become farther from the upper surface of the substrate 10, the lengths of the wiring portions IC may be shortened. The spacing of the wiring portions IC of the conductive patterns GL1 to GL6 is determined by the thickness of the interlayer insulating film. In addition, as the wiring parts IC of the conductive patterns GL1 to GL6 become farther from the upper surface of the substrate 10, the contact extension parts CT may be spaced apart from the protruding insulation pattern 11. In addition, the contact extensions CT may be shorter from the sidewalls of the protruding insulation pattern 11.

The top surfaces of the contact extension portions CT of the conductive patterns GL1 to GL6 are positioned at substantially the same height as the top surface of the protruding insulation pattern 11, and the dummy extensions DCT of the conductive patterns GL1 to GL6. The upper surfaces of the teeth are located at a height lower than the upper surface of the protruding insulation pattern 11. That is, the distances between the upper surface of the substrate 10 and the upper surfaces of the contact extensions CT may be substantially the same. In addition, the distances between the top surface of the substrate 10 and the top surfaces of the dummy extensions DCTs may be substantially the same.

According to another exemplary embodiment, the top surfaces of the dummy extensions DCTs of the conductive patterns GL1 to GL6 may be positioned at the same height as the top surface or the bottom surface of the top gate electrode GL6. In other words, the dummy extension DCT may not be connected to one end of the wiring IC. In this case, the uppermost gate electrode may be formed of the wiring part IC and the contact extension part CT.

The plurality of conductive patterns GL1 to GL6 are stacked such that the contact extension CT and the dummy extension DCT are alternately disposed in each of the first and second contact regions CR1 and CR2. In detail, the contact extension portions CT of the conductive patterns GL1, GL3, and GL5 disposed in the odd layer are disposed in the first contact region CR1, and the conductive patterns GL2, GL4, Dummy extensions DCT of GL6 may be disposed in the first contact region CR1. Similarly, the dummy extensions DCTs of the conductive patterns GL1, GL3, and GL5 disposed in the odd layer are disposed in the second contact region CR2, and the conductive patterns GL2, GL4, GL6 disposed in the even layer. The contact extensions CT of) may be disposed in the second contact region CR2. In other words, the dummy extension of the even-numbered conductive patterns GL2, GL4, and GL6 is formed between the contact extension portions CT of the odd-numbered conductive patterns GL1, GL3, and GL5 in the first contact region CR1. Divisions (DCTs) are deployed.

The conductive patterns GL1, GL3, and GL5 disposed in the odd layer are connected to the contact plug CP by the contact extensions CT on the first contact region CR1, and the conductive patterns disposed in the even layer. GL2, GL4, and GL6 may be connected to the contact plug CP by the contact extensions CT on the second contact region CR2.

Contact plugs CP connected to the odd-numbered conductive patterns GL1, GL3, and GL5 and contact plugs CP connected to the even-numbered conductive patterns GL2, GL4, and GL6 have different contacts. Disposed on the area.

The contact plugs CP formed on each of the contact extensions CT may electrically connect the wiring lines ICL and the conductive patterns GL1 to GL6. The wiring lines ICL may be disposed across the wiring portions IC of the conductive patterns GL1 to GL6. According to another embodiment, the wiring line ICL may be directly formed on the contact extensions CT.

The dummy extensions DCTs not connected to the contact plugs CP are covered by the insulating layer 64. Therefore, when the thickness of the insulating film 64 is a and the thickness of the gate electrodes GL1 to GL6 is b, the distance between the wiring portions IC of the conductive patterns GL1 to GL6 is a, but the contact plug CP is used. ) May be 2a + b between the contact extension portions CT of the conductive patterns GL1 to GL6. Therefore, the misalign margin of the contact plugs CP may be increased.

In the 3D semiconductor memory device according to example embodiments, various types of semiconductor memory devices may be formed in the cell array region CAR. This will be described in detail later.

FIG. 2 illustrates a modified embodiment of the 3D semiconductor memory device shown in FIG. 1.

Referring to FIG. 2, the protruding insulation patterns 13 formed on the first and second contact regions CR1 and CR2 of the substrate 10 may have an inclination with respect to the substrate 10. That is, the protruding insulation pattern 13 may have an inclined sidewall. The sidewalls of the protruding insulation patterns 13 may have an angle of about 90 degrees to about 130 degrees with respect to the substrate 10.

The contact extensions CT and the dummy extensions CT and DCT of the conductive patterns GL1 to GL6 formed on the substrate 10 by the protruding insulation pattern 13 are formed to be inclined with respect to the wiring part IC. do. That is, the gate electrodes GL1 to GL6 may have an angle θ of about 90 degrees to about 130 degrees between the wiring portion IC and the contact extension portion CT or the dummy extension portion CT. Since the contact extensions CT and the dummy extensions DCT are formed to be inclined, the area of the upper surface of the contact extension CT connected to the contact plug CP may be a contact extension formed perpendicular to the substrate 10. It may be larger than the area of the upper surface of the portion CT.

3 to 8 illustrate a method of manufacturing a semiconductor memory device according to embodiments of the present invention.

Referring to FIG. 3, a substrate 10 including a cell array region CAR and contact regions CR1 and CR2 is prepared, and an opening 25 defining a region where a conductive pattern is to be formed is formed. The contact region may include a first contact region CR1 on one side of the cell array region CAR and a second contact region CR2 on the other side of the cell array region CAR.

According to an embodiment, the opening 25 may be formed by depositing an insulating film having a predetermined thickness on the substrate 10 and patterning the insulating film to form a protruding insulating pattern 11 defining the bottom and side surfaces of the opening 25. It may comprise the step of forming. According to another embodiment, the opening 25 may be formed through a patterning step of recessing the substrate 10 to a predetermined depth. The sidewalls of the opening 25 may have a slope of about 90 degrees to 130 degrees with respect to the bottom surface.

Referring to FIG. 4, the thin film structures are formed by alternately stacking the first thin films 31 to 36 and the second thin films 41 to 46 on the substrate 10. The first thin films may be formed of a material having an etch selectivity with respect to the second thin films. In this case, the first thin films 30 and the second thin films 40 may be substantially conformally formed along the top surface of the substrate 10 and the surfaces of the protruding insulating patterns 11. In other words, the insulating film 30 and the conductive film 40 may be deposited to have a substantially uniform thickness along the upper surface of the substrate 10 and the surface of the protruding insulating pattern 11. Accordingly, the first thin films 30 and the second thin films 40 having the same profile as the profile of the substrate 10 and the protruding insulating pattern 11 may be formed.

The thin film structure including the first thin films 30 and the second thin films 40 alternately stacked may be formed such that the thickness of the thin film structure is smaller than the height of the protruding insulation pattern 11 in the cell array region CAR. .

The thickness of each of the first thin films 30 and the second thin films 40 may vary depending on the memory cells formed in the cell array region CAR. In addition, to reduce the thickness of the thin film structure, the insulating film 40 may be deposited thinner than the second thin film 40. The first thin films 30 may be formed of an insulating material. For example, the first thin films 30 may be formed of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. The second thin films 40 may be formed of a conductive material. For example, the second thin films 40 may be formed of at least one of a doped polycrystalline silicon film, a silicide film, and a metal film. According to another embodiment, the second thin films 40 may be formed of an insulating material having an etch selectivity with respect to the first thin films 30.

Referring to FIG. 5, the upper portion of the thin film structure is planarized to expose the top surface of the protruding insulating pattern 11. As the thin film structure is planarized, the first thin films 30 and the second thin films 40 stacked on the protruding insulation pattern 11 may be removed, and the first thin films 30 and the second thin films may be removed. 40 may be defined in the opening 25.

The second thin films 40 defined in the opening 25 may include the wiring part IC parallel to the substrate 10 and the contact extension parts CT formed on the sidewalls of the protruding insulating pattern 11. It may be made of. In other words, in each conductive pattern, contact extensions CT extending from both ends of the wiring part IC and having the same length may be formed. In addition, upper surfaces of the contact extensions CT of the second thin films 40 may be exposed at substantially the same height by the planarization step. In addition, since the second thin films 40 are repeatedly stacked, as the wiring IC of the second thin film 40 moves away from the upper surface of the substrate 10, the wiring IC parallel to the substrate 10 is formed. ) Area can be reduced.

The planarization of the upper portion of the thin film structure may include forming a buried film 52 filling a step of the thin film structure on the thin film structure, and planarizing the thin film structure until the upper surface of the protruding insulation pattern 11 is exposed. It includes. In the forming of the buried film 52, the buried film 52 may be formed of an insulating material having excellent gap fill characteristics. For example, the buried film 52 may include borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), tetraethically ortho silicate (TEOS), undoped silicate glass (USG), or high density plasma (HDP) or Spin On Glass (SOG) may be used. The planarization of the thin film structure may use a chemical mechanical polishing (CMP) or etch back process.

Meanwhile, according to another exemplary embodiment, before or after planarizing the upper portion of the thin film structure, the thin film structure may be patterned to form a trench in the form of a line exposing the substrate 10. In this case, a thin film structure having a line shape may be formed in the opening 25.

  Referring to FIG. 6, a mask pattern 54 may be formed to selectively expose upper surfaces of the contact extension parts CT of the second thin films 40. In detail, the mask pattern 54 exposes top surfaces of the contact extension portions CT of the second thin films 40 formed on the even layer in the first contact region CR1, and may be odd in the second contact region CR2. Top surfaces of the contact extensions CT of the second thin films 40 formed on the layer are exposed.

The forming of the mask pattern 54 may include forming a mask film on the thin film structure exposing the surfaces of the contact extensions CT and patterning the mask film. In the forming of the mask film, the mask film may be formed of a photoresist film or a silicon nitride film. In the patterning of the mask layer, the mask pattern 54 may expose a part of the interlayer insulating layer 30 on both sides of the contact extension CT.

Referring to FIG. 7, by selectively etching the contact extensions CT of the second thin film 40 using the mask pattern 54 as an etch mask, the recess regions (not shown) may be formed in some of the contact extensions CT. 62).

In detail, the contact extension portions CT of the second thin films 40 disposed on the even layer may be recessed in the first contact region CR1, and may be recessed in the odd layer in the second contact region CR2. Contact extensions CT of the second thin films 40 may be recessed.

In the etching of the contact extensions CT of the second thin films 40, an etching recipe having an etch selectivity with respect to the insulating layer may be used. Recessing the upper surfaces of the contact extensions CT may be performed until the upper surface of the uppermost interconnection part IC is exposed. According to another embodiment, when the contact extensions CT of the second thin film 40 are recessed, some of the first thin films on both sides of the contact extension CT may be etched according to the etching recipe. In another embodiment, when the contact extensions CT of the second thin film 40 are recessed, adjacent first thin films may also be recessed together to expose sidewalls of both contact extensions CT. After forming the recessed region 62, the etch mask is removed.

As such, as the recess region 62 is formed, the contact extension CT of the second thin films 40a and 40b in the first or second contact regions CR1 and CR2 is illustrated in FIG. 7. ) Can be alternately recessed. That is, the second thin film pattern structure in which a plurality of second thin film patterns 40a and 40b including the wiring part IC and the contact extension part CT and the dummy extension part DCT having different lengths are stacked is provided. Can be formed. That is, each of the second thin film patterns 40a and 40b may be formed of unrecessed contact extensions CT and recessed dummy extensions DCT. In addition, a dummy extension part CTT of the second thin films 40b disposed in the even layer is formed in the first contact region CR1, and a dummy extension part of the second thin films 40a disposed in the odd layer ( CT is formed in the second contact region CR2.

Referring to FIG. 8, the insulating film 64 is embedded on the recessed dummy extensions DCT, and the insulating film 64 is planarized until the top surfaces of the contact extensions CT are exposed. As the insulating layer 64 is buried in the recess region, the top surface of the dummy extensions DCTs may be covered with the insulating layer 64. In addition, sidewalls of the contact extension portions CT exposed when the recess region 62 is formed may also be covered with the insulating layer 64.

Thereafter, contact plugs CP are formed on the first and second contact regions CR1 and CR2 to be connected to the conductive patterns, respectively.

Forming the contact plugs CP may include forming an interlayer insulating film on the gate structures 40a and 40b, forming contact holes, and filling a conductive material in the contact hole. Forming the interlayer insulating layer 71 may include depositing an insulating material such as a silicon oxide film. The forming of the contact holes may include forming an mask pattern exposing the interlayer insulating layer 71 and then anisotropically etching the interlayer insulating layer 71 using the mask pattern as an etching mask. The contact holes expose the top surface of the contact extensions CT of the conductive patterns. Therefore, contact holes of the first contact region CR1 expose contact extension portions CT of the odd layer conductive patterns, and contact holes of the second contact region CR2 contact contact portions CT of the even layer gate electrode. Can expose them. Filling the conductive material in the contact hole may include depositing the contact material on the interlayer insulating layer 71 on which the contact holes are formed, and then planarizing the contact material.

Like the contact extension portions CT of the conductive patterns, the contact plugs CP are formed by dividing the first and second contact regions CR1 and CR2. Therefore, the number of contact plugs CP formed in the first or second contact regions CR1 and CR2 can be reduced by half.

Meanwhile, in the exemplary embodiment, contact plugs CP having the same length are described. However, contact plugs CP having different lengths may be formed according to the arrangement of the wirings connected to the conductive pattern.

After forming the contact plugs CP, wiring lines ICL are formed on the respective contact plugs CP, as shown in FIG. 1. Other contact plugs and wiring lines may be formed between the contact plug CP and the wiring line ICL. The wiring lines ICL may be formed to cross the wiring portions IC of the conductive patterns.

According to another embodiment, the step of forming the contact plugs CP on the contact extensions CT may be omitted, in which case the wiring line ICL may be formed directly on the contact extensions CT. have.

Hereinafter, embodiments of the present invention will be described with an example in which a NAND flash memory having a three-dimensional structure is formed in a cell array region CAR. However, the present invention is not limited thereto, and various types of memory devices such as PRAM, RRAM, or MRAM having a three-dimensional structure may be formed.

9 is a perspective view illustrating a semiconductor device according to an embodiment of the present invention.

9, an intermediate wiring structure 200 is disposed on a substrate 10. The intermediate wiring structure 200 may include insulating layer patterns 131, 132, 133, 134, and 135 and intermediate wirings 141, 142, 143, and 144 sequentially and repeatedly stacked. At least one semiconductor pattern 65 may be disposed on the sidewall of the intermediate wiring structure 200, and the information storage pattern 55 may be disposed between the semiconductor pattern 65 and the intermediate wiring structure 200. The lower wiring 20 connecting the lower regions of the semiconductor pattern 65 is disposed between the semiconductor pattern 65 and the substrate 10, and an upper portion of the intermediate wiring structure 200 connected to the semiconductor pattern 65. The wiring 75 may be disposed.

The substrate 10 may include at least one of a semiconductor, a conductive material, and an insulating material. According to an embodiment, the substrate 10 may be a silicon film having a single crystal structure, and the lower wiring 20 may be an impurity diffusion region formed in the substrate 10. In this case, the impurity diffusion regions used as the substrate 10 and the lower wiring 20 may have different conductivity types.

The semiconductor pattern 65 may be a single crystal semiconductor or a polycrystalline semiconductor. In this case, when the lower wiring 20 is an impurity diffusion region, the semiconductor pattern 65 may have a different conductivity type from the lower wiring 20 so as to form a diode with the lower wiring 20. According to an embodiment, the semiconductor pattern 65 may be an intrinsic semiconductor.

Meanwhile, the lower wiring 20 may be formed of a conductive material. In this case, the semiconductor pattern 65 may include at least two parts having different conductivity types in order to implement a rectifying device such as a diode. For example, some regions (hereinafter, the body portion) B of the semiconductor pattern 65 disposed around the intermediate wirings 141 to 146 may be different from those of the semiconductor pattern 65 contacting the lower wiring 20. The region (source region) and the conductivity type may be different. In addition, a portion (hereinafter, a drain region) D of the upper region of the semiconductor pattern 65 may be formed to have a different conductivity type from the body portion B. FIG.

The semiconductor pattern 65 may extend from one side of the intermediate wiring structure 200 and be connected to another semiconductor pattern 65 disposed on the other side of the intermediate wiring structure 200. In this case, the semiconductor pattern 65 is also disposed on the upper surface of the intermediate wiring structure 200, and the upper wiring 75 is formed on the upper surface of the intermediate wiring structure 200 through a predetermined plug 70. Can be connected to the semiconductor pattern 65.

The intermediate lines 141 to 146 may be at least one of conductive materials. For example, the intermediate lines 141 to 146 may include at least one of doped semiconductors, metals, metal nitrides, and metal silicides. In this case, the intermediate wirings 141 to 146 may be formed in a direction crossing the upper wiring 75.

According to an aspect of the present invention, the intermediate interconnections 141 to 146 may control the electrical connection between the upper interconnection 75 and the lower interconnection 20 by controlling the potential of the semiconductor pattern 65. More specifically, the semiconductor pattern 65 may form a MOS capacitor by capacitively coupling the intermediate lines 141 to 146. In this case, the voltage applied to the intermediate wirings 141 to 146 can variably control the potential of the semiconductor pattern 65 adjacent thereto, and the energy band of the semiconductor pattern 65 is applied to the intermediate wirings 141 to 146. It may be inverted depending on the voltage applied. Therefore, the electrical connection between the upper wiring 75 and the lower wiring 20 may be controlled by the voltage applied to the intermediate wirings 141 to 146 constituting the intermediate wiring structure 200.

On the other hand, such electrical connection is possible when the regions inverted on each side of the intermediate lines 141 to 146 overlap each other. In order to allow the inversion regions to overlap, the insulating layer patterns 132 to 134 between the intermediate lines 141 to 146 may be formed to have a thickness smaller than twice the maximum width of the inverted region. The insulating layer patterns 131 to 135 may be at least one of insulating materials, and may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. However, since the uppermost insulating layer pattern 135 may be used as an etching mask in a subsequent patterning process, the uppermost insulating layer pattern 135 may be formed to have a thicker thickness than the other insulating layer patterns 131 to 134. In addition, according to an embodiment of the present invention for a flash memory device, a high voltage may be applied to the lowermost intermediate wiring 141 which may cause an insulation breakdown phenomenon between the substrate 10 or the lower wiring 20. have. Therefore, the lowermost insulating layer pattern 131 may be formed to have a thickness thicker than the insulating layer patterns 131 to 134 interposed between the intermediate lines 141 to 146.

According to another aspect of the present invention, the intermediate wirings 141 to 146 may be used to change the information stored in the information storage pattern 55, in addition to the semiconductor pattern 65. According to one aspect of the present invention, when the voltage applied to each of the intermediate wirings 141 to 146 is independently adjusted, the semiconductor pattern 65 of the predetermined intermediate wiring side may be formed by the upper wiring 75 or the lower wiring ( 20) may optionally be connected. That is, some regions of the semiconductor pattern 65 facing the predetermined intermediate wirings (eg, 142) may be formed by the upper wirings 75 according to voltages applied to the other intermediate wirings 141, 143, and 144. Or may be placed at an equipotential with the lower wiring 20. Therefore, when a voltage different from that of the upper wiring 75 or the lower wiring 20 is applied to the selected intermediate wiring 142, a potential difference that can be used to change information is generated at both ends of the information storage pattern 55. Can be.

According to an aspect of the present invention, the information storage pattern 55, together with the semiconductor pattern 65 and the intermediate wirings 141 to 146, may be used as a capacitor dielectric film constituting a MOS capacitor. For this purpose, the information storage pattern 55 includes at least one of insulating materials.

According to another aspect of the present invention, the information storage pattern 55 may form a MOS transistor together with the semiconductor pattern 65 and the intermediate wirings 141 to 146. In this case, the semiconductor pattern 65 is used as the channel region, the intermediate wirings 141 to 146 are used as the gate electrode, and the information storage pattern 55 is used as the gate insulating film. In this case, a portion of the semiconductor pattern 65 on the side of the information storage pattern 55 is inverted by the voltage applied to the intermediate wirings 141 to 146, and thus may be used as source / drain electrodes of the MOS transistor. In addition, since the semiconductor pattern 65 is disposed on the sidewalls of the intermediate interconnections 141 to 146, the current direction of the MOS transistor using the semiconductor pattern 65 as the channel region is perpendicular to the upper surface of the substrate 10.

The information storage pattern 55 includes an insulating material and may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a high dielectric film. In this case, the high dielectric film refers to insulating materials having a dielectric constant higher than that of silicon oxide film, and include tantalum oxide film, titanium oxide film, hafnium oxide film, zirconium oxide film, aluminum oxide film, yttrium oxide film, niobium oxide film, cesium oxide film, indium oxide film, iridium oxide film, It may include a BST film and a PZT film.

In the semiconductor memory device described with reference to FIG. 9, the intermediate lines 141 to 146 may be interconnections ICs of the plurality of conductive patterns GL1 to GL6 described with reference to FIGS. 1 and 2. have. Accordingly, the contact extension part CT and the dummy extension part CT of the plurality of conductive patterns GL1 to GL6 described with reference to FIGS. 1 and 2 may be connected to the intermediate lines 141 to 146.

10 is a cross-sectional view illustrating a data storage pattern according to an embodiment of the present invention.

Referring to FIG. 10, the information storage pattern 55 may include a tunnel insulating film 55a adjacent to the semiconductor pattern 65, a blocking insulating film 55c adjacent to the intermediate wiring structure 200, and a tunnel insulating film 55a and a blocking insulating film. It may include a charge storage film 55b interposed between the 55c.

In this case, the blocking insulating layer 55c may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a high dielectric film. According to an embodiment, the blocking insulating film 55c may be a multilayer thin film including a high dielectric film. The tunnel insulating film 55a may be formed of a material having a lower dielectric constant than the blocking insulating film 55c, and the charge storage film 55b may be an insulating thin film (eg, silicon nitride film) rich in charge trap sites, or conductive particles. It may be an insulating thin film including the. In example embodiments, the tunnel insulation layer 55a may be a silicon oxide layer, the charge storage layer 55b may be a silicon nitride layer, and the blocking insulation layer 55c may be an insulation layer including an aluminum oxide layer. In this case, the intermediate wirings 141 to 146 may include tantalum nitride films.

11 is a circuit diagram illustrating a cell array structure of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 11, a semiconductor memory device according to this embodiment may include a plurality of bit lines BL, a common source electrode CSL, a semiconductor device connecting each of the bit lines BL and the common source electrode CSL. The pattern 65 includes a plurality of intermediate lines 140 that face the bit lines BL while facing the semiconductor patterns 65. A rectifying element may be disposed between the semiconductor patterns 65 and the bit line BL or the common source electrode CSL. An information storage body may be disposed between the intermediate line 140 and the semiconductor pattern 65. According to an embodiment, the information storage body may include a thin film for charge storage as described with reference to FIG. 10.

The unit memory cell UC of the semiconductor memory device according to the present exemplary embodiment includes a semiconductor pattern 65, one intermediate wiring 140 facing the semiconductor pattern 65, and an information storage interposed therebetween. In this case, between the bit line BL and the common source electrode CSL, a plurality of intermediate lines 140, which face one semiconductor pattern 65, are sequentially disposed. Accordingly, the unit memory cells UC sharing one semiconductor pattern 65 connect the bit line BL and the common source electrode CSL in series. The cell string STR of the semiconductor memory device according to the present exemplary embodiment includes a bit line BL, a common source electrode CSL, and unit memory cells UC connected in series therebetween.

According to an exemplary embodiment, the intermediate line closest to the bit line BL may be used as the string select line SSL that controls the electrical connection between the cell string STR and the corresponding bit line BL. In addition, an intermediate line closest to the common source electrode CSL may be used as a ground select line GSL that controls an electrical connection between the cell string STR and the common source electrode CSL. The intermediate lines 140 between the string and ground select lines SSL and GSL may be used as word lines WL used to change information of the unit memory cell UC. For simplicity, four word lines are shown in the figure, but the cell string STR may include a greater number of word lines.

The word lines WL may be connected to the global word lines GWL. In this case, each of the word lines WL constituting one cell string STR is connected to different global word lines GWL. According to an embodiment, the global word lines GWL are disposed in a direction parallel to the bit line BL to electrically connect the word lines WL. Meanwhile, when the global word lines GWL and the bit lines BL are parallel in this manner, the string select line SSL and the ground select line GSL may be the bit line BL to select the unit memory cell UC. It may be formed in a direction crossing the.

12 is a perspective view illustrating a portion of a cell array of a semiconductor memory device according to an embodiment of the present invention. The semiconductor memory device according to this embodiment has the technical features of the present invention described in the above embodiments with reference to FIGS. 9 and 10. Thus, for brevity of description, descriptions of overlapping technical features may be omitted.

Referring to FIG. 12, a semiconductor memory device according to this embodiment includes a plurality of intermediate wiring structures 200 disposed on a substrate 10. The intermediate wiring structures 200 may be disposed in parallel with each other, and each of the intermediate wiring structures 200 may include insulating layer patterns 131 to 135 and intermediate wirings 141 to 146 that are sequentially and repeatedly stacked.

A plurality of semiconductor patterns 65 may be disposed on both side surfaces of the intermediate interconnection structures 200 to cross the intermediate interconnection structures 200. According to an embodiment, the semiconductor patterns 65 may be connected to each other at the top surface of the intermediate wiring structures 200 and the bottom surface therebetween. In this case, the semiconductor patterns 65 may be formed in a line shape covering the side surfaces of the intermediate wiring structures 200 while crossing the intermediate wiring structures 200.

An information storage pattern 55 may be disposed between the semiconductor pattern 65 and the intermediate wiring structure 200. According to this embodiment, the information storage pattern 55 may include a charge storage film, as described with reference to FIG. 10, and the information stored in the information storage pattern 55 may be interposed with the semiconductor pattern 65. Can be changed using Fowler-Northernheim tunneling caused by the voltage difference between (141-146).

The lower wiring 20 (or lower impurity region) may be formed in the substrate 10 under the intermediate wiring structures 200. The lower impurity region 20 may be formed not only under the intermediate wiring structures 200 but also in the substrate 10 therebetween, so that the plurality of semiconductor patterns 65 may be electrically connected to each other. A plurality of upper interconnections 75 may be disposed on the intermediate interconnection structure 200 to cross the intermediate interconnections 141 to 146 while being connected to the semiconductor pattern 65. According to this embodiment, the lower impurity region 20 is used as a common source electrode (CSL in FIG. 3), and the upper interconnections 75 are stored with a write voltage or stored voltage for changing information stored in the information storage pattern 55. It may be used as bit lines (BL of FIG. 3) for applying a read voltage for reading information.

Meanwhile, according to an embodiment of the present invention, except for a contact section for connection with an upper wiring, which will be described later, an arrangement structure of intermediate wirings (for example, 141) arranged in a predetermined layer is arranged in another layer. It may be substantially the same as the layout structure of the intermediate lines (for example, 142 to 146).

In the semiconductor memory device described with reference to FIGS. 11 and 12, the intermediate lines 141 ˜ 146 may include the wiring units IC of the plurality of conductive patterns GL1 ˜ GL6 described with reference to FIGS. 1 and 2. May be). Accordingly, the contact extension part CT and the dummy extension part CT of the plurality of conductive patterns GL1 to GL6 described with reference to FIGS. 1 and 2 may be connected to the intermediate lines 141 to 146.

13 to 18 are perspective views illustrating a method of manufacturing a semiconductor memory device in accordance with an embodiment of the present invention.

Referring to FIG. 13, a substrate 10 having a cell array region, a contact region, and a core region is prepared similarly to that described with reference to FIG. 3. The top surface of the cell array region is formed lower than the top surface of the core region. According to one embodiment, such a structure may be formed through a patterning step of recessing the substrate 10 in the cell array region. According to another embodiment, the structure may be formed by forming a predetermined thin film having a thickness corresponding to a step between two regions on the substrate 10 and then etching the thin film in the cell array region. .

Thereafter, the insulating layers 31, 32, 33, 34, 35, 36, 37 and the conductive layers 41, 42, 43, 44, 45, 46 are sequentially and repeatedly deposited on the substrate 10. In this case, the insulating layers 31 to 37 and the conductive layers 41 to 46 may be conformally formed on the substrate 10. The total thicknesses of the insulating layers 31 to 37 and the conductive layers 41 to 46 may be smaller than the step H between the cell array region and the core region.

The insulating layers 31 to 37 may be a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. Meanwhile, the thicknesses of the insulating films 32 to 34 interposed between the conductive films 41 to 46 may be selected in a range that satisfies the technical characteristics for overlap of inversion regions described in FIG. 9. Can be. However, since the uppermost insulating layer 35 may be used as an etching mask in a subsequent patterning process, the upper insulating layer 35 may be formed to a thickness thicker than those of the other insulating layers 31 to 34. In addition, the lowermost insulating layer 31 may have conductive layers 41 ˜ 46 so as to prevent insulation breakdown between the lowermost intermediate wiring 141 of FIG. 11 and the substrate 10 or the lower impurity region 20. It may be formed to a thickness thicker than the insulating layers 32 to 34 interposed therebetween.

The conductive layers 41 to 46 may include at least one of doped semiconductors, metals, metal nitrides, and metal silicides. As shown in FIG. 9, a memory cell transistor according to example embodiments has a vertical channel, and thicknesses of the conductive layers 41 to 46 define a channel length of the memory cell transistor. In this aspect, the thicknesses of the conductive films 41 to 46 may be selected in a range that satisfies the technical requirements (eg, prevention of short channel effects) related to the channel length of the memory cell transistor.

According to an embodiment, the lower impurity region 20 may be formed in the cell array region of the substrate 10 before the insulating layers 31 to 37 and the conductive layers 41 to 46 are formed. The lower impurity region 20 may be formed to have a different conductivity type from that of the substrate 10, and in this case, may be used as the common source electrode CSL described with reference to FIG. 11.

Referring to FIG. 14, the intermediate wiring structures 200 defining trenches T for patterning the insulating layers 31 to 37 and the conductive layers 41 to 46 to expose the upper surface of the substrate 10. ). The intermediate wiring structure 200 includes the insulating film patterns 131, 132, 133, 134, 137, 136, and 137 formed by patterning the insulating films 31 to 37 and the conductive films 41 to 46. The wirings 141, 142, 143, 146, 145, and 146 may be formed. Side surfaces of the intermediate lines 141 to 146 and the insulating layer patterns 131 to 137 are exposed to define the trench T.

The intermediate wiring structures 200 may be formed through a patterning process using the patterned top insulating film 137 as a hard mask after patterning the top insulating film 137 through photolithography and etching processes. According to the modified embodiments, before forming the intermediate interconnect structures 200, a separate mask layer for an etching mask is formed on the entire surface of the substrate to reduce difficulty in patterning due to the step difference between the cell array region and the core region. After forming, the method may further include planarization etching of the resultant.

According to still other modified embodiments, the intermediate wiring structures 200 may be formed through a plurality of patterning steps. For example, the insulating layers 31 to 37 and the conductive layers 41 to 46 may be independently patterned in the core region and the cell array region. Specifically, the patterning step may include first patterning the thin films in the core region, forming a mask layer covering the patterned core region, and then patterning the cell array region.

Referring to FIG. 15, after forming the information storage layer pattern 55 covering the side surfaces of the intermediate interconnection structures 200, the semiconductor layer 60 is formed on the resultant.

The data storage layer pattern 55 may extend from the side surface of the intermediate wiring structure 200 to cover the upper surface of the intermediate wiring structure 200. According to this embodiment, the data storage layer pattern 55 may be formed to expose the top surface of the substrate 10 at the bottom of the trench T. To this end, an etching process for removing the data storage layer pattern 55 from the bottom of the trench T may be further performed.

According to a modified embodiment, in order to prevent the data storage layer pattern 55 from being damaged, an etching process may be performed while the data storage layer pattern 55 is covered with a predetermined protective film. For example, the semiconductor film 60 may be formed through two or more deposition processes, and the first semiconductor film deposited may be used as a protective film.

According to an embodiment, the data storage layer pattern 55 may include a charge storage layer. For example, the information storage film pattern 55 is sequentially shown as shown in FIG. A blocking insulating layer 55c, a charge storage layer 55b, and a tunnel insulating layer 55a may be stacked. The blocking insulating layer 55c may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a high dielectric film, and may include a plurality of films. In this case, the high dielectric film refers to an insulating material having a dielectric constant higher than that of the silicon oxide film, and includes tantalum oxide film, titanium oxide film, hafnium oxide film, zirconium oxide film, aluminum oxide film, yttrium oxide film, niobium oxide film, cesium oxide film, indium oxide film, iridium oxide film, and BST. Film and PZT film. The tunnel insulating film 55a may be formed of a material having a lower dielectric constant than the blocking insulating film 55c, and the charge storage film 55b may be an insulating thin film (eg, silicon nitride film) rich in charge trap sites, or conductive particles. It may be an insulating thin film including the. In example embodiments, the tunnel insulation layer 55a may be a silicon oxide layer, the charge storage layer 55b may be a silicon nitride layer, and the blocking insulation layer 55c may be an insulation layer including an aluminum oxide layer.

The semiconductor film 60 may be a single crystal semiconductor or a polycrystalline semiconductor, and may be formed using a vapor deposition technique or an epitaxial technique. The semiconductor layer 60 may be formed to have a conformal thickness or may substantially fill the remaining space of the trench T in which the data storage layer pattern 55 is formed. According to an embodiment, the semiconductor layer 60 may have a different conductivity type from the lower impurity region 20 to form a diode with the lower impurity region 20.

Referring to FIG. 16, the resultant on which the semiconductor film 60 is formed is planarized and exposed to expose the upper surface of the substrate 10. Meanwhile, as described above, the total thickness t of the insulating layers 31 to 37 and the conductive layers 41 to 46 may be smaller than the step H between the cell array region and the core region. In this embodiment, the intermediate lines 141 to 146 and the insulating layer patterns 131 to 137 are limitedly disposed in the cell array region by planarization etching.

Meanwhile, each of the intermediate lines 141 to 146 defined inside the cell array region may have a wiring section parallel to the upper surface of the substrate 10 and a contact section extending from one or both ends of the wiring section. In this case, the contact sections of the intermediate lines 141 to 146 are disposed near the boundary between the cell array region and the core region, and as a result of planarization etching, their upper surfaces are the same height as the exposed upper surfaces of the substrate 10. Can be formed on.

According to an exemplary embodiment, as described with reference to FIG. 5, a buried insulating layer 88 may be further formed before the planarization etching to cover the resultant formed with the semiconductor layer 60 to fill the trench T. FIG. In this case, upper surfaces of the contact sections of the intermediate lines 141 to 146 are exposed between the substrate 10 and the buried insulating film.

Referring to FIG. 17, the semiconductor film 60 is patterned to form a plurality of semiconductor patterns 65 that cross the intermediate wiring structure 200. The forming of the semiconductor patterns 65 may include patterning the buried insulating film 88 to form the buried insulating film pattern 99 defining openings 99a exposing the semiconductor film 60, and then exposing the exposed semiconductor film. And etching (60). In this case, the openings 99a may be formed in a direction crossing the intermediate wiring structures 200, and thus, the semiconductor patterns 65 are formed in a direction crossing the intermediate wiring structures 200.

Etching the buried insulating film may be performed by an anisotropic etching method having an etch selectivity with respect to the semiconductor film 60, and etching the semiconductor film 60 may be performed by an etching method having an etch selectivity with respect to the buried insulating film. Can be implemented. The etching of the semiconductor film 60 may be performed by an isotropic etching method to separate the semiconductor film 60 from the side surface of the intermediate wiring structure 200. However, the etching of the semiconductor film 60 may be performed through each of the anisotropic etching method and the isotropic etching method, or a combination thereof.

According to an embodiment, after the semiconductor patterns 65 are formed, the data storage layer pattern 55 may be further etched to expose the intermediate wiring structure 200.

In addition, prior to forming the semiconductor patterns 65, as described with reference to FIGS. 6 to 8, selectively recessing the contact sections of the intermediate lines 141 to 146 may be performed. That is, the contact sections of the intermediate lines 141, 143, and 145 disposed in the odd layer and the contact sections of the intermediate lines 142, 144, and 146 disposed in the even layer may be recessed in different areas. have.

Referring to FIG. 18, after forming an insulating layer (not shown) filling the openings 99a on the resultant semiconductor patterns 65, the semiconductor patterns 65 and the intermediate wirings 141 to 146 are formed. Upper wirings 75 connected to the first and second interconnectors 75 are formed. The upper interconnections 75 respectively connected to the semiconductor patterns 65 and the intermediate interconnections 141 to 146 are used as the bit lines BL and the global intermediate interconnections GWL described with reference to FIG. 3. .

In addition, after forming the upper interconnections 75, a string select line SSL and a ground select line GSL may be formed to connect to the uppermost intermediate interconnection 146 and the lowermost intermediate interconnection 141, respectively. The upper and ground select lines SSL and GSL may be formed in a direction crossing the bit line BL.

In the method of manufacturing the semiconductor memory device described with reference to FIGS. 13 to 18, the intermediate lines 141 to 146 may be formed by forming the plurality of conductive patterns GL1 to GL6 described with reference to FIGS. 3 to 8. It can be formed using the method. Accordingly, the contact extension part CT and the dummy extension part CT of the plurality of conductive patterns GL1 to GL6 described with reference to FIGS. 3 to 8 may be connected to the intermediate lines 141 to 146.

19 is a circuit diagram illustrating an electrical connection structure of intermediate wirings according to an exemplary embodiment of the present invention.

In the semiconductor memory device according to this embodiment, as described with reference to FIG. 11, each of the plurality of bit lines BL, the common source electrode CSL, and the bit lines BL, and the common source electrode CSL The semiconductor patterns 65 may be connected to each other, and the plurality of intermediate lines 140 may be disposed to cross the bit lines BL while facing the semiconductor patterns 65.

In this embodiment, global word lines GWL are disposed at both sides with a plurality of bit lines BL interposed therebetween. The word lines WL crossing the global word lines GWL are alternately connected to the global word lines GWL on one side or the other side.

In addition, the string select line SSL and the ground select line GSL are disposed with the plurality of bit lines BL interposed therebetween. In this case, the string select line SSL and the ground select line GSL may be formed in a direction crossing the bit lines BL. According to another exemplary embodiment, the string select line SSL and the ground select line GSL may be disposed in parallel with the global word lines GWL.

In the semiconductor memory device described with reference to FIG. 19, the word lines WL may be interconnections ICs of the plurality of conductive patterns GL1 to GL6 described with reference to FIGS. 1 and 2.

20 and 21 are perspective views illustrating an electrical connection structure of intermediate wirings according to an exemplary embodiment of the present invention.

As described with reference to FIG. 13, the conductive films 41 to 46 may be conformally formed. In this case, the angle between the contact sections of the intermediate wirings 141 to 146 and the upper surface of the substrate 10 is substantially the same as the angle at which the boundary surface of the cell array region and the core region forms the upper surface of the substrate 10. can do. For example, as shown in FIG. 20, when the interface between the cell array region and the core region is perpendicular to the upper surface of the substrate 10, the contact sections of the intermediate lines 141 to 146 may also be formed on the substrate 10. It is formed perpendicular to the upper surface.

In addition, contact sections of intermediate lines disposed in the even or odd layer are recessed from the planarized top surface. That is, the top surface of the contact sections of the intermediate lines disposed in the even or odd layer not recessed are exposed. The contact plugs are connected to the contact sections where the top surface is exposed. In other words, as described with reference to FIG. 1, even-layer intermediate interconnections are connected to the contact plug at one side of the cell array region, and odd-layer intermediate interconnections are connected to the contact plug at the other side of the cell array region.

Meanwhile, according to another embodiment of the present invention, as shown in FIG. 21, an interface between the cell array region and the core region may form an angle θ less than 90 degrees with respect to the upper surface of the substrate 10. In this case, the area of the upper surfaces of the intermediate lines 141 to 146 exposed by the planarization etching described above is increased compared to the previous embodiment. Specifically, if the thickness and width of the intermediate wiring are a and b, respectively, the exposed area of such intermediate wiring is ab for the preceding embodiments and ab / sinθ for this embodiment. Therefore, as the angle decreases, the exposed area of the intermediate lines 141 to 146 increases. According to one embodiment, the angle may be between 30 degrees and 90 degrees.

In the semiconductor memory device described with reference to FIGS. 20 through 21, the intermediate lines 141 ˜ 146 may include wiring lines ICs of the plurality of conductive patterns GL1 ˜ GL6 described with reference to FIGS. 1 and 2. May be). In addition, in the semiconductor memory device described with reference to FIGS. 20 through 21, the contact periods of the intermediate lines 141 through 146 may be formed by the plurality of conductive patterns GL1 through GL6 described with reference to FIGS. 1 and 2. Contact extensions CT and dummy extensions DCT.

22 is a perspective view illustrating a cell array structure of a semiconductor memory device according to another embodiment of the present invention.

Referring to FIG. 22, a 3D semiconductor memory device according to an embodiment may include a common source line CSL, a plurality of bit lines BL0, BL1, BL2, and BL3, a common source line CSL, and bit lines It may include a plurality of cell strings CSTR disposed between BL0-BL3.

The common source line CSL may be a conductive thin film disposed on the semiconductor substrate 100 or an impurity region formed in the substrate 100. The bit lines BL0-BL3 may be conductive patterns (eg, metal lines) spaced apart from the semiconductor substrate 100 and disposed thereon. The bit lines BL0-BL3 are two-dimensionally arranged, and a plurality of cell strings CSTR are connected in parallel to each other. Accordingly, the cell strings CSTR are two-dimensionally arranged on the common source line CSL or the substrate 100.

 Each of the cell strings CSTR includes a ground select transistor GST connected to the common source line CSL, a string select transistor SST connected to the bit lines BL0-BL3, and ground and string select transistors GST, The memory cell transistors MCT may be disposed between the SSTs. The ground select transistor GST, the string select transistor SST, and the memory cell transistors MCT may be connected in series. In addition, the ground select line GSL, the plurality of word lines WL0-WL3, and the plurality of string select lines SSL disposed between the common source line CSL and the bit lines BL0-BL3. The ground select transistor GST, the memory cell transistors MCT, and the string select transistors SST may be used as conductive patterns, respectively.

 All of the ground select transistors GST may be disposed at substantially the same distance from the substrate 100, and their conductive patterns may be commonly connected to the ground select line GSL to be in an equipotential state. To this end, the ground select line GSL may be a plate-shaped or comb-shaped conductive pattern disposed between the common source line CSL and the memory cell transistor MCT adjacent thereto. Similarly, conductive patterns of the plurality of memory cell transistors MCT, which are disposed at substantially the same distance from the common source line CSL, are also commonly connected to one of the word lines WL0-WL3 and are in an equipotential state. There may be. To this end, each of the word lines WL0-WL3 may be a conductive pattern having a flat plate shape or a comb shape parallel to the upper surface of the substrate 100. On the other hand, since one cell string CSTR is composed of a plurality of memory cell transistors MCT having different distances from the common source line CSL, the common source line CSL and the bit lines BL0-. Multiple word lines WL0-WL3 are disposed between BL3s.

 Each of the cell strings CSTR may include a semiconductor pillar PL extending vertically from the common source line CSL and connected to the bit lines BL0-BL3. The semiconductor pillars PL may be formed to penetrate the ground select line GSL and the word lines WL0-WL3. In addition, the semiconductor pillar PL may include a body portion B and impurity regions formed at one end or both ends of the body portion B. For example, the drain region D may be formed at an upper end of the semiconductor pillar PL (that is, between the body portion B and the bit lines BL0-BL3).

An information storage layer may be disposed between the word lines WL0-WL3 and the semiconductor pillar PL. According to an embodiment, the information storage layer may be a charge storage layer. For example, the information storage film may be one of an insulating film including a trap insulating film, a floating gate electrode, or conductive nano dots.

 A dielectric film used as the gate insulating film of the ground select transistor GST or the string select transistor SST between the ground select line GSL and the semiconductor pillar PL or between the string select lines SSL and the semiconductor pillar PL. This can be arranged. The gate insulating film of at least one of the ground and string selection transistors GST and SST may be formed of the same material as the information storage film of the memory cell transistor MCT, but a gate insulating film for a typical MOSFET may be formed. For example, a silicon oxide film).

The ground and string select transistors GST and SST and the memory cell transistors MCT may be Morse field effect transistors (MOSFETs) using the semiconductor pillar PL as a channel region. According to another embodiment, the semiconductor pillar PL may form a MOS capacitor together with the ground select line GSL, the word lines WL0-WL3 and the string select lines SSL. . In this case, the ground select transistor GST, the memory cell transistors MCT, and the string select transistor SST may be separated from the ground select line GSL, the word lines WL0-WL3 and the string select lines SSL. It can be electrically connected by sharing inversion layers formed by parasitic fringe fields.

In the semiconductor memory device described with reference to FIG. 22, the word lines WL0-WL3, the ground and string select lines SSL and GSL may include the plurality of conductive patterns described with reference to FIGS. 1 and 2. The interconnections ICs GL1 to GL6 may be formed.

23 and 24 are perspective views for explaining in detail the active pillar and the gate insulating film according to another embodiment of the present invention.

The gate insulating layer GI is disposed between the active pillars PL and the word line planes WL_PT. According to an embodiment, the gate insulating layer GI may be used as a thin film for storing information. For example, the gate insulating layer GI may include a charge storage layer, and more specifically, as shown in FIGS. 23 and 24, the blocking insulating layer 231, the charge storage layer 232, and the tunnel insulating layer 233 may be formed. It may include. In this case, the three-dimensional semiconductor memory device according to the present invention can be used as a charge trapping nonvolatile memory device. The blocking insulating layer 231, the charge storage layer 232, and the tunnel insulating layer 233 may have technical features disclosed in known documents.

In addition, according to an exemplary embodiment, the gate insulating layers GI may be formed between the lower selection plane LS_PT or the string selection line SSL between the active pillars PL and the word line planes WL_PT. It can extend between the active pillars PL. That is, the gate insulating layer GI may be formed between the active pillars PL and the gate conductive layers (ie, WL_PT, LS_PT, and SSL).

In the semiconductor memory device described with reference to FIGS. 23 to 24, the word line planes WL_PT may include the wiring portion IC of the plurality of conductive patterns GL1 to GL6 described with reference to FIGS. 1 and 2. Can be heard. Accordingly, contact extensions may be connected to one side of the word line planes WL_PT.

25 to 30 are cross-sectional views illustrating a method of manufacturing a semiconductor memory device in accordance with other embodiments of the present invention.

Referring to FIG. 25, similar to that described with reference to FIG. 3, the lower gate insulating layer 110 and the lower gate layer 120 are sequentially formed on the semiconductor substrate 100. The semiconductor substrate 100 may include a cell array region (or cell array region) in which memory cells are formed and a peripheral circuit region in which peripheral circuits for operating the memory cells are formed.

The semiconductor substrate 100 may be a single crystal semiconductor having a first conductivity type (for example, a p-type silicon wafer). The semiconductor substrate 100 may include a region (that is, a well region) electrically separated by impurity regions of another conductivity type. A plurality of well regions may be formed in one semiconductor substrate 100, and the well regions may be formed of a pocket well structure or a triple well structure. In addition, an isolation layer 105 may be formed on the semiconductor substrate 100 to define electrical devices.

The lower gate insulating layer 110 may be a silicon oxide layer formed through a thermal oxidation process, and a thickness thereof may be about 40 angstroms to 300 angstroms. On the other hand, as is known, flash memory devices may have gate insulating films of various thicknesses and materials, and methods for forming them are well established. The lower gate insulating film 110 may be formed using at least one of known gate insulating film forming techniques of such a flash memory device.

The lower gate layer 120 is formed of at least one of conductive materials to be used as a gate electrode. For example, the lower gate layer 120 may be formed of a conductive material such as doped polycrystalline silicon.

The lower gate pattern 125 and the lower gate insulating layer 110 may be used as the ground selection line GSL and the capacitor dielectric layer CD, respectively. To this end, the lower gate layer 120 and the auxiliary lower gate layer 130 formed in the cell array region are not etched in the patterning step.

The upper gate layers 201, 202, 203, 204, and 205 and the gate interlayer insulating layers 211, 212, 213, 214, 215, and 216 are alternately formed on the lower gate pattern 125. At this time, the upper gate layers 201 to 205 stacked while being spaced apart from each other by the gate interlayer insulating layers 211 to 216 constitute the upper gate structure 200, and the gate interlayer insulating layers 211 ˜ interposed therebetween. 216 constitutes a gate interlayer dielectric structure 210.

According to the present invention, the upper gate layers 201 to 205 are used as the word line planes WL_PT or the string select lines SSL. Therefore, as described above, the gap between the upper gate layers 201 to 205 (that is, the thickness of the gate interlayer insulating layers 211 to 216) is a range smaller than the maximum width of the inversion region generated in the active pillar PL. It may be formed to have. In addition, the upper gate layers 201 to 205 may be formed of at least one of conductive materials so as to be used as a gate electrode. (E.g., doped polycrystalline silicon.)

Since the upper gate layers 201 to 205 are used as gates of the memory cell transistors according to the present invention, their thickness determines the channel length of the memory cell transistors. Since the upper gate layers 201 to 205 are formed through a deposition process, the channel length may be more precisely controlled than when formed using a patterning technique. In addition, since the longitudinal direction of the channel of the memory cell transistors is perpendicular to the semiconductor substrate 100, the degree of integration of the semiconductor memory device according to the present invention is independent of the thickness of the upper gate layers 201 to 205. Therefore, the upper gate layers 201 to 205 may be selected in a range capable of preventing technical problems due to a short channel effect.

The gate interlayer insulating films 211 to 216 may be formed of a silicon oxide film. The generation of the inversion region by the potential applied to the upper gate layers may be controlled by a fringe field (FF) due to the voltage applied to the gate conductive layers. To facilitate the generation of such an inversion region, the gate interlayer insulating films 211 to 216 may further include high dielectric films. The high dielectric film may be one of the high dielectric films (eg, silicon nitride film and silicon oxynitride film) having a higher dielectric constant than the silicon oxide film. In this case, the upper gate layers 201 to 205 and the lower gate pattern 125 constitute gate conductive layers.

Meanwhile, the number of thin films constituting the upper gate structure 200 and the gate interlayer insulating structure 210, their respective thicknesses, their respective materials, etc., are related to the electrical characteristics of the memory cell transistors and technical difficulties in the process of patterning them. In consideration of these, various modifications may be made.

Referring to FIG. 26, the openings 220 exposing the upper surface of the semiconductor substrate 100 in the cell array area by patterning the upper gate structure 200, the gate interlayer insulating structure 210, and the lower gate pattern 125. ).

On the other hand, when the sidewalls of the openings 220 are formed to be inclined, non-uniformity in electrical characteristics of the memory cells may appear because channel widths of the memory cell transistors are changed. To minimize this, that is, so that the openings 220 can have vertical sidewalls, the patterning process for forming the openings can be performed using an anisotropic etching technique. According to the modified embodiment, in order to improve the uniformity of the inter-cell electrical characteristics, the upper gate layers 201 to 205 may be formed to have different thicknesses.

Referring to FIG. 27, the gate insulating film 230 is conformally formed on the resultant product in which the openings 220 are formed. The gate insulating film 230 may be at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, and may be formed of one of other known insulating materials used as the gate insulating film.

According to an embodiment of the present invention, the gate insulating layer 230 may include a thin film for storing information. For example, as illustrated in FIGS. 23 and 24, the gate insulating layer 230 or GI may include a blocking insulating layer 231, a charge storage layer 232, and a tunnel insulating layer 233 that are sequentially stacked. The charge storage film 232 may be a silicon nitride film or a silicon oxynitride film having charge trap sites, and is used as a thin film for storing information. The tunnel insulating film 233 may be a thermal oxide film or a chemical vapor deposition silicon oxide film, and the blocking insulating film 231 may include at least one of materials having a higher dielectric constant than the tunnel insulating film 233. The blocking insulating film 231, the charge storage film 232, and the tunnel insulating film 233 may be formed using or modified by techniques disclosed in the known literature.

Meanwhile, as described above, the semiconductor substrate 100 is electrically connected to the active pillars 300 and PL filling the openings 220. To this end, since it is required to expose the upper surface of the semiconductor substrate 100, to form the spacers 240 as an etching mask in the opening 220. The spacers 240 are formed to cover the inner wall of the gate insulating layer 230 in the opening 220 to reduce etch damage to the gate insulating layer 230 in a subsequent patterning process of etching the gate insulating layer 230. Let's do it.

According to an embodiment, the spacers 240 may be one of materials that can be removed while minimizing etching damage to the gate insulating layer 230 and GI. For example, when the gate insulating layer GI in contact with the spacers 240 is a silicon oxide layer, the spacers 240 may form a silicon nitride layer. According to a modified embodiment, the spacers 240 may be formed of the same material as the active pillar PL. For example, the spacers 240 may be formed of amorphous or polycrystalline silicon. In this case, the spacer 240 may be used as the active pillar PL without a separate removal process.

Referring to FIG. 28, the exposed gate insulating layer 230 is etched using the spacers 240 as an etch mask. Accordingly, the top surface of the semiconductor substrate 100 is exposed at the bottom of the openings 220. In this case, the etch stop layer 160 may be removed during or before etching the gate insulating layer 230.

 Subsequently, active pillars 300 are formed to fill the opening 220. According to the present invention, the active pillars 300 are formed of the same material as the semiconductor substrate 100. According to an embodiment, the active pillar 300 and the semiconductor substrate 100 may be silicon having a single crystal structure continuously connected without crystal defects. To this end, the active pillars 300 may be grown from the exposed semiconductor substrate 100 using one of epitaxial techniques. In this case, when the spacers 240 are formed of silicon, the spacers 240 may be monocrystallized during the epitaxial process to form a part of the active pillar 300.

According to another embodiment, before forming the active pillars 300, the spacers 240 are removed while minimizing etching damage to the gate insulating layer 230 and GI. Subsequently, a semiconductor film is formed to contact the semiconductor substrate 100 at the bottom of the opening 220 while covering the gate insulating layers 230. The semiconductor film may be formed using one of chemical vapor deposition techniques and is used as the active pillar 300. In this case, the semiconductor film may be formed of polycrystalline or amorphous silicon, and a discontinuous interface in the crystal structure may be formed between the semiconductor substrate 100 and the semiconductor film (ie, 300).

In this case, the semiconductor layer may be formed to fill the opening 220 in which the gate insulating layer 230 is formed, as shown in FIG. 29. However, according to the modified embodiment, as shown in FIG. 24, the gate insulating layer 230 may be formed to conformally cover the opening 220. In the latter case, the semiconductor film (ie, the active pillar 300) may be formed in a cylindrical or shell shape, and the internal space thereof may be filled with an insulating material. On the other hand, the thickness of the semiconductor film (ie, the thickness of the shell) may be thinner than the width of the depletion region to be created therein or smaller than the average length of the silicon grains constituting the polycrystalline silicon.

According to the present invention, the active pillars 300 are formed to have the same conductivity type as the semiconductor substrate 100 to which they contact. As a result, since the active pillars 300 do not constitute a diode with the semiconductor substrate 100, the active pillars 300 may have an equipotential with the semiconductor substrate 100.

Referring to FIG. 30, a drain region D used as drain electrodes of cell strings is formed in an upper region of the active pillars 300 and PL.

Subsequently, the uppermost gate layer 205 is patterned to form string select lines SSL. Each of the string select lines SSL is formed to one-dimensionally connect the active pillars PL.

According to an embodiment, the forming of the string select lines SSL may include forming the first conductive layer 270 on the contact plugs 260, and then forming the first conductive layer 270 and the upper gate interlayer. Patterning the insulating layer 216 and the uppermost upper gate layer 205. The first conductive layer 270 may prevent the active pillar PL from being etched in a subsequent process, and may directly contact the upper regions of the active pillars PL (ie, the drain region D). In consideration of such direct contact, the first conductive layer 270 is preferably formed of one of materials capable of ohmic contact with the active pillar.

In the method of manufacturing the semiconductor memory device described with reference to FIGS. 25 to 30, the gate layers 201 to 205 and the string select line SSL may include the plurality of conductive patterns described with reference to FIGS. 3 to 8. It may be formed using the method of forming (GL1 ~ GL6).

31 to 34 are cross-sectional views illustrating a method of manufacturing a semiconductor memory device in accordance with another modified embodiment of the present invention.

Referring to FIG. 31, similar to those described with reference to FIG. 3, the sacrificial layers SC1, SC2, SC3, SC4, SC5, and SC6 and the gate interlayer insulating layers 211, 212, and 213 are formed on the semiconductor substrate 100. , 214, 215, and 216 are formed alternately. That is, the sacrificial layers SC1 to SC6 constituting the sacrificial layer structure SC are stacked while being spaced apart from each other by the gate interlayer insulating layers 211 to 216. The gate interlayer insulating layers 211 ˜ 216 interposed between the sacrificial layers SC1 ˜ SC6 form a gate interlayer insulating structure 210. A buffer layer 110 may be formed between the semiconductor substrate 100 and the sacrificial layers SC1 to SC6 or the gate interlayer insulating layers 211 to 216.

As the gate interlayer insulating films 211 to 216, at least one of known insulating materials may be used. For example, the gate interlayer insulating films 211 to 216 may include at least one of a silicon oxide film and a silicon nitride film. The sacrificial layers SC1 to SC6 are formed of materials that can be selectively removed while minimizing etching of the gate interlayer insulating layers 211 to 216.

The gate interlayer insulating structure 210 and the sacrificial film structure SC are patterned to form openings 50 exposing the top surface of the semiconductor substrate 100. According to this embodiment, each of the openings 50 may be formed in a line or stripe shape instead of a hole shape. In addition, the openings 50 may have different widths depending on the distance from the semiconductor substrate 100.

The semiconductor film 300 covering the inner wall of the opening 50 is formed. According to this embodiment, the semiconductor film 300 may be formed to conformally cover the inner wall of the opening 50 using chemical vapor deposition techniques, and the remaining space inside the opening may be formed of an insulating material 310 (eg, For example, silicon oxide film, silicon nitride film or air). Meanwhile, according to the modified embodiment, the semiconductor film 300 may be formed using epitaxial technology to fill the openings 50. The opening 50 may be filled with the semiconductor film 300.

Referring to FIG. 32, the gate interlayer insulating structure 210 and the sacrificial layer structure SC are again patterned to expose the upper surface of the semiconductor substrate 100 or the buffer layer 110 between the openings 50. The gate isolation region 225 is formed. That is, the preliminary gate isolation region 225 is formed between the adjacent semiconductor films 300, and is preferably formed at the center thereof. As a result, the sidewalls of the gate interlayer insulating films 211 to 216 and the sacrificial films SC1 to SC6 are exposed by the preliminary gate isolation region 225.

The sacrificial layers SC1 ˜ SC6 exposed by the preliminary gate isolation region 225 are removed. As a result, gate regions 226 that partially expose sidewalls of the semiconductor film 300 are formed between the gate interlayer insulating films 211 to 216. Since the buffer layer 110 is removed while the sacrificial layers SC1 ˜ SC6 are removed, the upper surface of the semiconductor substrate 100 may be exposed in the preliminary gate isolation region 225 and the gate region 226.

Removing the sacrificial layers SC1 ˜ SC6 may use an etching recipe having etch selectivity with respect to the gate interlayer insulating layers 211 ˜ 216, the semiconductor substrate 100, the semiconductor layer 300, and the insulating material 310. It can be carried out by. In addition, the removing of the sacrificial layers SC1 to SC6 may be performed by a dry or wet method, but isotropic etching is preferably used.

The gate insulating layer 230 is formed on the resultant product in which the gate regions 226 are formed. The gate insulating layer 230 may include a blocking insulating layer, a charge storage layer, and a tunnel insulating layer. According to this embodiment, the tunnel insulating film may be formed to cover at least the sidewall of the semiconductor film 300 exposed through the gate region, and the charge storage film and the blocking insulating film may be formed to conformally cover the resultant product in which the tunnel insulating film is formed. have.

Referring to FIG. 33, a conductive gap fill layer filling the preliminary gate isolation region 225 and the gate region 226 is formed on the resultant product on which the gate insulating layer 230 is formed. The conductive gapfill film may be formed using at least one of thin film forming techniques that provide excellent step coverage, and may be at least one of polycrystalline silicon film, silicide films, and metal films.

Subsequently, the conductive gap fill film is anisotropically etched using the uppermost gate interlayer insulating film 216 or the gate insulating film 230 as an etching mask. Accordingly, in the preliminary gate isolation region 225, a gate isolation region 225 ′ exposing sidewalls of the vertically separated conductive gapfill layers is formed. Vertically separated conductive gap pick layers are formed in the gate regions 226 and form electrically separated gate layers 201, 202, 203, 204, 205, and 206. The electrically separated gate layers 201 to 206 may constitute the gate structure 200 and may be used as the above-described horizontal patterns HP.

Thereafter, a gapfill insulating layer 180 filling the gate isolation region 225 ′ is formed. The gap fill insulating layer 180 is preferably a silicon oxide film, but is not limited thereto, and may be formed of at least one of various other insulating materials.

Referring to FIG. 34, the semiconductor layers 300 are patterned to form vertical patterns VP. According to this embodiment, since the vertical patterns VP are used as active regions constituting the memory cell string, the vertical patterns VP need to be horizontally separated. To this end, the forming of the vertical patterns VP may include forming a mask pattern (not shown) across the openings 50 or the gate isolation region 225 ′ and using the mask pattern as an etching mask. And etching the semiconductor film 300.

In addition, in this etching step, the top gate interlayer insulating film 216 may be used as an etching mask. Accordingly, holes may be formed in the regions between the mask patterns in the gate isolation region 225 ′ to expose sidewalls of the gate structure 200. After the holes are filled with the insulating material 305, the upper interconnections 270 are formed to electrically connect the separated vertical patterns VP. The upper wires 270 may be used as bit lines. Meanwhile, before forming the upper interconnections 270, the drain regions D may be formed by implanting impurities having a different conductivity type from the semiconductor substrate 100 into the upper region of the vertical pattern VP.

In the method of manufacturing the semiconductor memory device described with reference to FIGS. 31 to 34, the gate layers 201 to 206 may be formed by forming the plurality of conductive patterns GL1 to GL6 described with reference to FIGS. 3 to 8. It can be formed using the method.

35 to 38 are cross-sectional views illustrating another method of manufacturing a semiconductor memory device in accordance with another modified embodiment of the present invention.

35 to 38, the opening 50 according to this embodiment is formed in the form of a hole, and in this respect, it is distinguished from the embodiment described above with reference to FIGS.

Meanwhile, according to this embodiment, the vertical patterns VP are formed to fill the openings 50 separated from each other. As a result, the final shape of the vertical pattern in the previous embodiment is determined in the step of patterning the semiconductor films 300, but the final shape of the vertical pattern in this embodiment is defined by the opening 50 in the form of a hole. .

In this embodiment, the thicknesses of the electrically separated gate films 201 to 206 are defined by the sacrificial films SC1 to SC6.

There may be a difference corresponding to twice the thickness of the gate insulating layer 230 between the thicknesses of the sacrificial layers SC1 ˜ SC6 and the thicknesses of the separated gate layers 201 ˜ 206. The thickness of SC6) may be formed in consideration of this difference in thickness.

In the method of manufacturing the semiconductor memory device described with reference to FIGS. 35 to 38, the gate layers 201 to 206 may be formed by forming the plurality of conductive patterns GL1 to GL6 described with reference to FIGS. 3 to 8. It can be formed using the method.

39 is a schematic block diagram illustrating an example of a memory system including a nonvolatile memory device according to example embodiments.

Referring to FIG. 39, the memory system 1100 may include a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, It can be applied to a memory card or any device capable of transmitting and / or receiving information in a wireless environment.

The memory system 1100 includes a controller 1110, an input / output device 1120 such as a keypad, a keyboard, and a display, a memory 1130, an interface 1140, and a bus 1150. Memory 1130 and interface 1140 are in communication with one another via bus 1150.

The controller 1110 includes at least one microprocessor, digital signal processor, microcontroller, or other similar process device. Memory 1130 may be used to store instructions performed by the controller. The input / output device 1120 may receive data or a signal from the outside of the system 1100 or output data or a signal to the outside of the system 1100. For example, the input / output device 1120 may include a keyboard, a keypad, or a display device.

The memory 1130 includes a nonvolatile memory device according to embodiments of the present invention. The memory 1130 may also further include other types of memory, volatile memory that can be accessed at any time, and various other types of memory.

The interface 1140 transmits data to the communication network or receives data from the network.

40 is a schematic block diagram illustrating an example of a memory card including a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 40, a memory card 1200 for supporting a high capacity of data storage capability includes a flash memory device 1210 according to the present invention. The memory card 1200 according to the present invention includes a memory controller 1220 that controls the exchange of all data between the host and the flash memory device 1210.

The SRAM 1221 is used as the operating memory of the processing unit 1222. The host interface 1223 includes a data exchange protocol of a host that is connected to the memory card 1200. Error correction block 1224 detects and corrects errors contained in data read from multi-bit flash memory device 1210. The memory interface 1225 interfaces with the flash memory device 1210 of the present invention. The processing unit 1222 performs various control operations for exchanging data of the memory controller 1220. Although not shown in the drawings, the memory card 1200 according to the present invention may further be provided with a ROM (not shown) for storing code data for interfacing with a host. It is self-evident to those who have acquired knowledge.

41 is a schematic block diagram illustrating an example of an information processing system equipped with a nonvolatile memory device according to the present invention.

Referring to FIG. 41, the flash memory system 1310 of the present invention is mounted in an information processing system such as a mobile device or a desktop computer. The information processing system 1300 according to the present invention includes a flash memory system 1310 and a modem 1320, a central processing unit 1330, a RAM 1340, and a user interface 1350 electrically connected to a system bus 1360, respectively. It includes. The flash memory system 1310 may be configured substantially the same as the above-described memory system or flash memory system. The flash memory system 1310 stores data processed by the CPU 1330 or data externally input. In this case, the above-described flash memory system 1310 may be configured as a semiconductor disk device (SSD), in which case the information processing system 1300 can stably store a large amount of data in the flash memory system 1310. As the reliability increases, the flash memory system 1310 can save resources required for error correction and provide a high-speed data exchange function to the information processing system 1300. Although not shown, the information processing system 1300 according to the present invention may be further provided with an application chipset, a camera image processor (CIS), an input / output device, and the like. Self-explanatory to those who have learned.

In addition, the flash memory device or the memory system according to the present invention may be mounted in various types of packages. For example, a flash memory device or a memory system according to the present invention may be a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in-line package. (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline ( SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer- It can be packaged and mounted in the same manner as Level Processed Stack Package (WSP).

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention belongs may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. You will understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

1 is a cross-sectional view of a 3D semiconductor memory device according to example embodiments.

FIG. 2 illustrates a modified embodiment of the 3D semiconductor memory device shown in FIG. 1.

3 to 8 illustrate a method of manufacturing a semiconductor memory device according to embodiments of the present invention.

9 is a perspective view illustrating a semiconductor device according to an embodiment of the present invention.

10 is a cross-sectional view illustrating a data storage pattern according to an embodiment of the present invention.

11 is a circuit diagram illustrating a cell array structure of a semiconductor memory device according to an embodiment of the present invention.

12 is a perspective view illustrating a portion of a cell array of a semiconductor memory device according to an embodiment of the present invention.

13 to 18 are perspective views illustrating a method of manufacturing a semiconductor memory device in accordance with an embodiment of the present invention.

19 is a circuit diagram illustrating an electrical connection structure of intermediate wirings according to an exemplary embodiment of the present invention.

20 and 21 are perspective views illustrating an electrical connection structure of intermediate wirings according to an exemplary embodiment of the present invention.

22 is a perspective view illustrating a cell array structure of a semiconductor memory device according to another embodiment of the present invention.

23 and 24 are perspective views for explaining in detail the active pillar and the gate insulating film according to another embodiment of the present invention.

25 to 30 are cross-sectional views illustrating a method of manufacturing a semiconductor memory device in accordance with other embodiments of the present invention.

31 to 34 are cross-sectional views illustrating a method of manufacturing a semiconductor memory device in accordance with another modified embodiment of the present invention.

35 to 38 are cross-sectional views illustrating another method of manufacturing a semiconductor memory device in accordance with another modified embodiment of the present invention.

39 is a schematic block diagram illustrating an example of a memory system including a nonvolatile memory device according to example embodiments.

40 is a schematic block diagram illustrating an example of a memory card including a nonvolatile memory device according to an embodiment of the present invention.

41 is a schematic block diagram illustrating an example of an information processing system equipped with a nonvolatile memory device according to the present invention.

Claims (10)

A substrate including a first contact region and a second contact region spaced apart from each other; And Including a plurality of conductive patterns stacked in sequence, Each of the conductive patterns, A wiring portion parallel to an upper surface of the substrate; And A contact extension part extending from one end of the wiring part along a direction passing through the upper surface of the substrate; At least one contact extension of the conductive patterns is disposed in the first contact region, and at least another contact extension of the conductive lines is disposed in the second contact region. The method of claim 1, Each of the conductive patterns further includes a dummy extension part extending from the other end of the wiring part in a direction penetrating the upper surface of the substrate. The method of claim 2, In one conductive pattern, the length of the dummy extension is shorter than the length of the contact extension. The method of claim 2, And the contact extension portion of the conductive pattern is disposed between the dummy extension portions of adjacent conductive patterns. The method of claim 1, And the distances between the top surface of the substrate and the top surfaces of the contact extensions are substantially the same. The method of claim 1, The lengths of the wiring portions gradually decrease as the wiring portions of the conductive patterns become farther from the upper surface of the substrate. The method of claim 1, And wiring lines crossing the wiring portions on the plurality of conductive patterns and connected to each of the contact extension portions of the conductive patterns. The method of claim 7, wherein The contact extensions of the conductive patterns disposed in the odd layer are connected to the wiring line on the first contact region. And contact extension portions of the conductive patterns disposed on the even layer are connected to the wiring line on the second contact region. The method of claim 1, And the angle between the wiring portion and the contact extension portion is 90 degrees to 130 degrees. The method of claim 1, The substrate further comprises a cell array region between the first contact region and the second contact region, The semiconductor memory device may include semiconductor patterns penetrating the wiring portions of the conductive patterns; And And a data storage layer pattern interposed between the semiconductor pattern and the conductive pattern.

Images