KR20100097793A - Field effect transistor using iii-v compound semiconductor and fabricating method of the same - Google Patents

Abstract

The present invention relates to a FET such as HEMT that requires a gate recess on a III-V compound semiconductor heterojunction structure, and in particular, a separate etching process for the gate recess can be omitted or simplified, resulting in increased yields due to process shortening. In addition, the present invention relates to a FET using a III-V compound semiconductor and a method of manufacturing the same, which can secure the reproducibility of the gate recess and improve the reliability of the device.

Specifically, the present invention is a substrate; A cap layer made of a III-V compound semiconductor material and sequentially stacked on the substrate to include a cap layer stacked on the high band gap layer to form a gate recess made of a III-V compound semiconductor material including a buffer layer, a channel layer, a high band gap layer, and Sb. Heterojunction structure of the III-V compound semiconductor; Source and drain regions in ohmic contact with the cap layer; And it provides a FET using a III-V compound semiconductor comprising a Schottky junction metal gate to the gate recess and a method of manufacturing the same.

Description

Field Effect Transistor using III-V compound semiconductor and fabricating method of the same}

The present invention relates to a field effect transistor (FET) using a III-V compound semiconductor and a method of manufacturing the same. More specifically, the present invention relates to a FET such as a HEMT (High Electron Mobility Transistor) that requires a gate recess on a heterojunction structer of a III-V compound semiconductor. For the FET using the III-V compound semiconductor and its manufacturing method that can increase the yield according to the process shortening, secure the reproducibility of the gate recess and improve the reliability of the device can be omitted or simplified the separate etching process for will be.

In response to the recent full-scale informatization era, the semiconductor field for large-capacity information processing has been followed, and in line with this, efforts for high-integration and high-speed operation of the Complementary Metal Oxide Semiconductor deVice (CMOS) have continued.

In particular, as the trend of miniaturization, light weight, and thinning of various electronic devices has continued, the scaling down and performance improvement of CMOS have emerged as a current issue, and the size reduction of Si-based CMOS, which has been widely used in the past, has become a FET (Field). Reduces the effect channel length of the Effect Transistor, causing punch through and short channel effects and exponentially controlling the tunneling effect due to the reduction of the thickness of the gate insulating film. To increase.

Accordingly, FETs using III-V compound semiconductors, which have higher high electron mobility and saturated drift velocity than Si, have attracted attention as a new method for size reduction and performance improvement of CMOS. In particular, high electron mobility transistors (modified doping) (High Electron Mobility Transistor (hereinafter referred to as HEMT)) is attracting attention.

A general HEMT is essential for the III-V compound semiconductor heterojunction structure including a buffer layer, a channel layer, a high band gap layer, and a cap layer, which are sequentially stacked on a substrate. The source and drain regions are in ohmic contact with the cap layer, and a gate recess is provided between the source and drain regions to form a metal gate and a high band gap layer. Schottky is spliced.

In order to manufacture HEMT, a buffer layer (for example, intrinsic GaAs) and a channel layer (for example, intrinsic AlGaAs or InGaAs / AlGaAs), which are typically made of a III-V compound semiconductor material, on a semi-insulating substrate (substrate, for example GaAs, etc.), Selective crystal growth (selectiVe) of high bandgap layer (eg doped AlGaAs) and cap layer (eg doped GaAs) is performed in order to complete the heterojunction structure of the III-V compound semiconductor, followed by metal deposition followed by photolithography. Source and drain regions are realized through photo-lithography, etching, and annealing. Subsequently, a portion of the cap layer between the source and drain regions is removed by separate photolithography and gate recess etching to secure the gate recess, and then metal gate is realized through photolithography and etching following additional metal deposition.

Accordingly, FETs using III-V compound semiconductors, particularly HEMTs, require gate recess etching for the Schottky junction between the metal gate and the semiconductor, but the process is very important and difficult.

In other words, the gate recess etching is an important process that determines the reliability of the finished HEMT, and changes the device characteristics even with a small error of about 1-2 nm. Accordingly, at present, a selective etching method according to an etching rate between the high band gap layer and the cap layer is mainly used.

However, since the thickness of the cap layer is usually a small range of several nm or less, reproducibility is greatly reduced according to various etching conditions such as temperature, time, and string, while dry etching using reactive ion etching (ReactiVe Ion Etching: In the case of RIE), it is very time consuming and costly due to separate equipment mobilization, and there is a high possibility of damaging the thin film due to ion collision. In the case of wet etching, the characteristics of the device are often deteriorated by causing side damage of the cap layer. .

Therefore, in order to implement a FET using III-V compound semiconductors such as HEMT having high reproducibility and reliability, an improved gate recess etching method is urgently needed.

The present invention has been made to solve the above problems, by omitting or simplifying a separate etching process for the gate recess to increase the yield according to the process shortening as well as to improve the reproducibility and improve the device reliability The purpose is to present.

The present invention to achieve the above object, the substrate; A cap layer made of a III-V compound semiconductor material and sequentially stacked on the substrate, the cap layer made of a III-V compound semiconductor material including a buffer layer, a channel layer, a high band gap layer, and Sb to provide a gate recess; Heterojunction structure of the III-V compound semiconductor; Source and drain regions in ohmic contact with the cap layer; And it provides a FET device using a III-V compound semiconductor comprising a metal gate Schottky junction to the gate recess.

In this case, the high band gap layer is made of a III-V compound semiconductor material excluding Sb, and further comprises an etch stop layer interposed between the high band gap layer and the cap layer made of a III-V compound semiconductor material except Sb. The III-V compound semiconductor material is characterized in that it comprises AlGaAs, GaAs, InGaAs, InAs, GaSb.

In addition, the present invention comprises the steps of (a) stacking a buffer layer, a channel layer, a high band gap layer made of a III-V compound semiconductor material on the substrate; (b) stacking a cap layer made of III-V compound semiconductor material including Sb on the high band gap layer to implement a heterojunction structure of the III-V compound semiconductor; (c) ohmic contacting the source and drain regions spaced apart from each other on the cap layer; (d) applying a photoresist to cover the source and drain regions and the cap layer and selectively exposing with a mask; (e) developing the photoresist with a developer containing TMAH to form a photoresist pattern exposing the source and drain regions, and simultaneously removing a cap layer between the source and drain regions exposed by the photoresist pattern; Forming a gate recess; (f) removing the photoresist pattern; And (g) a Schottky junction of the metal gate to the gate recess, to provide a method for manufacturing a FET device using a III-V compound semiconductor.

At this time, the developer of step (e) is characterized in that consisting of 97 to 99% by weight of water and 1 to 3% by weight of TMAH based on the total weight, the high-bandgap layer of step (a) is And an etch stop layer made of the III-V compound semiconductor material excluding Sb on the high bandgap layer after the step (a) and before the step (b) after the step (a). In addition, the group III-V compound semiconductor material is characterized in that it comprises AlGaAs, GaAs, InGaAs, InAs, GaSb.

The present invention has the advantage of eliminating or simplifying an additional etching process for the gate recess in the FET such as HEMT requiring the gate recess on the III-V compound semiconductor heterojunction structure.

That is, the present invention uses the III-V compound semiconductor including Sb as the cap layer of the III-V compound semiconductor heterojunction structure, while using a TMAH aqueous solution as the developer for the photoresist pattern on the cap layer.

As a result, the gate recess can be implemented during the development of the photoresist without a separate gate recess etching process, which increases the yield according to process shortening, secures the reproducibility of the gate recess, and improves the reliability of the device. have.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic cross-sectional view of HEMT, which is an example of a FET using a III-V compound semiconductor according to the present invention. (Hereinafter, referred to as HEMT according to the present invention.)

As can be seen, the HEMT according to the present invention is a III-V compound semiconductor heterojunction comprising a buffer layer 22, a channel layer 24, a high band gap layer 26, and a cap layer 28, which are sequentially stacked on the substrate 2. Gate recesses between the source and drain regions 42 and 44 in ohmic contact with the structure 20 and the cap layer 28 of the III-V compound semiconductor heterojunction structure 20. And a metal gate 50 that is coupled to the high bandgap layer 28 and the Schottky through 32.

Looking at each of them in detail:

First, the buffer layer 22 and the channel layer 24 of the substrate 2 and the III-V compound semiconductor heterojunction structure 20 may be based on general technical concepts.

That is, the substrate 2 may be made of a semi-insulating material such as GaAs, the buffer layer 22 may be made of a III-V compound semiconductor material such as intrinsic GaAs, and the channel layer 24 may be made of III, such as intrinsic AlGaAs. -V compound may be made of a semiconductor material. For reference, if necessary, the channel layer 24 may exhibit a pseudomorphic structure by double stacking of InGaAs and AlGaAs for band discontinuity, and the substrate 2, III-V compound semiconductor heterojunction structure. The buffer layer 22 and the channel layer 24 of the 20 may be made of all known materials.

Next, the high band gap layer 26 of the III-V compound semiconductor heterojunction structure 20 is made of a III-V compound semiconductor material excluding Sb, and the cap layer 28 is made of a III-V compound semiconductor material including Sb. . The high band gap layer 26 and the cap layer 28 are doped with high concentration impurities, respectively.

That is, in the HEMT according to the present invention, the high band gap layer 26 of the III-V compound semiconductor heterojunction structure 20 is limited to the III-V compound semiconductor material excluding Sb such as AlGaAs, which is heavily doped, and the cap layer 28. Silver is characterized by being limited to III-V compound semiconductor material containing Sb, such as GaSb. This is to omit or simplify the gate recess etching, which will be described later.

The cap layer 28 is in ohmic contact with the source and drain regions 42 and 44 spaced apart from each other, and the high band gap layer 26 is partially exposed from the cap layer 28 between the source and drain regions 42 and 44. A gate recess 32 is provided to bond the metal gate 50 and the high band gap layer 28 to the Schottky junction.

On the other hand, Figure 2 is a schematic cross-sectional view of the HEMT according to a modification of the present invention.

Since the same reference numerals are given to the same parts that play the same role as the components described with reference to FIG. 1, the HEMT according to the modified example of the present invention is a III-V compound semiconductor heterojunction structure 20. A separate etch stop layer 30 having a thickness of 5 to 30 nm is interposed between the high band gap layer 26 and the cap layer 28.

In this case, the etch stop layer 30 is not limited to the III-V compound semiconductor material except for Sb, for example, InAs, but the material forming the high band gap layer 26 is not limited.

That is, the present invention is directed to a FET such as a HEMT that requires a gate recess 32 on the heterojunction structure 20 of the III-V compound semiconductor, the characteristic of which is the cap layer on which the gate recess 32 is formed. In (28), III-V compound semiconductor material containing Sb is used, and the underlying layer uses III-V compound semiconductor material except Sb.

This simplifies a separate etching process for the gate recess 32.

3 to 8 are each a process cross-sectional view of a FET using a III-V compound semiconductor according to the present invention, it is shown for the HEMT described in Figure 1 for convenience. Reference is made together to FIGS. 1 and 2.

First, as shown in FIG. 3, after preparing the substrate 2, a buffer layer 22, a channel layer 24, and a high band gap layer 26 for the III-V compound semiconductor heterojunction structure 20 are formed through selective crystal growth. The cap layer 28 is implemented.

At this time, the selective crystal growth may be applied to a known technical idea, the substrate 2 is optionally a semi-insulating material such as GaAs, the buffer layer 22 is a III-V compound semiconductor material such as intrinsic GaAs, the channel layer 24 May be made of a III-V compound semiconductor material such as intrinsic AlGaAs, respectively. The high band gap layer 26 is made of III-V compound semiconductor material except Sb, such as AlGaAs, and is heavily doped (n ⁺ ), and the cap layer 28 is made of III-V compound semiconductor material containing Sb, such as GaSb. It is heavily doped (n ⁺ ).

For reference, if necessary, it is possible to interpose a 5 to 30 nm thick etch stop layer 26 made of a III-V compound semiconductor material except Sb, such as InAs, between the high band gap layer 28 and the cap layer 28, in this case, The high bandgap layer 26 need not be limited to III-V compound semiconductor materials except Sb, as discussed above with reference to FIG.

Next, as shown in FIG. 4, source and drain regions 42 and 44 spaced apart from each other are formed in the cap layer 28 of the III-V semiconductor compound heterojunction structure 20.

In this case, the source and drain regions 42 and 44 are implemented in the order of deposition of a metal thin film, photolithography or lift-off, patterning by etching, and annealing. A photoresist pattern is applied to a thin film, that is, a photoresist, which is a photosensitive material, is applied to the thin film, and then exposed with a mask and developed with a developer to selectively expose the underlying metal layer. Collectively, the process of obtaining.

As a result, the source and drain regions 42 and 44 spaced apart from each other on the cap layer 28 may be obtained by subsequent etching, and the source and drain regions 42 and 44 may be removed by annealing after removing the residual photoresist pattern. This is done.

Next, a photoresist is applied to cover the source and drain regions 42 and 44 and the cap layer 28 exposed therebetween, as shown in FIG.

In this case, the photoresist is classified into a positive type (positiVe) in which the lighted portion is removed by the developer and a negative type in which the non-lighted portion is removed by the developer, but is referred to as a negative type for convenience.

Next, as shown in FIG. 6, the mask 70 is disposed on the photoresist film 60 covering the source and drain regions 42 and 44 and the cap layer 28, and then exposed.

In this case, the mask 70 includes a blocking unit 72 that blocks light and a transmission unit 74 that transmits light, and the exposure is performed by directly contacting the mask 70 and the photoresist layer 60. type), a proximity type or projection type that separates the mask 70 from the photoresist film 60 to a certain degree, a step and repeat type or a step and repeat method of reduction projection exposure. A step and scan type is possible.

Next, as shown in FIG. 7, development is carried out with a predetermined developer.

In this case, the present invention uses a solution of Tetra Methyl Ammonium Hydroxide (TMAH) as a developer, and the TMAH solution is preferably a mixture of 97 to 99% by weight of water based on total weight and 1 to 3% by weight of TMAH based on total weight. Indicates. Here, TMAH is a substance contained in an organic-based developer such as AZ300, and it has been found through the experiments and studies of the applicant that there is a characteristic of etching the III-V compound semiconductor containing Sb.

As a result, when the photoresist film (see 60 in FIG. 6) is developed with a TMAH aqueous solution, a photoresist pattern 62 having a portion removed between the source and drain regions 42 and 44 is obtained, and at the same time, the photoresist pattern 62 A portion of the underlying cap layer 28 exposed by is removed together to obtain a gate recess 62. For reference, according to the experiments and studies of the applicants, the TMAH aqueous solution shows selective etching characteristics only for the III-V compound semiconductor containing Sb. Unlike the cap layer 28, the TMAH aqueous solution is made of the III-V compound semiconductor material except for Sb. The high band gap layer 26 (or the etch stop layer 30 of FIG. 2) is not damaged.

However, when the cap layer 28 is exposed to TMAH aqueous solution for too long, unnecessary side damage may occur, so that the etching time is 20 to 30 seconds for the cap layer 28 in the range of several nm, assuming a dipping method at room temperature. Do.

Next, as shown in FIG. 8, if the remaining photoresist pattern (see 62 of FIG. 7) is removed, and the metal gate 50 is formed in the gate recess 32, the HEMT according to the present invention described with reference to FIG. 1 is described. Is completed.

In this case, for the metal gate 50, a process of depositing a metal thin film selected from Ti, Au, and Al, photolithography, patterning by etching, and removing residual photoresist may be performed.

In addition, the above description is only an example of this invention, The technical idea of this invention is not limited to this. That is, the present invention is directed to FETs such as HEMT that require the gate recess 32 on the heterojunction structure 20 of the III-V compound semiconductor, and a separate etching process for the gate recess 32 is performed. In order to omit or simplify, the III-V compound semiconductor containing Sb is used as the cap layer 28, and TMAH aqueous solution is used as a developing solution for the photoresist pattern on the cap layer 28.

As a result, there may be various modifications in the scope and details of the present invention, but if these modifications fall within the technical scope of the present invention, they should be included within the scope of the present invention. It is clearly stated in the claims.

1 is a schematic cross-sectional view showing an example of a FET using a III-V compound semiconductor according to the present invention.

Figure 2 is a schematic cross-sectional view showing a modification of the FET using III-V compound semiconductor according to the present invention.

3 to 8 are cross-sectional views of manufacturing processes for one example of a FET using a III-V compound semiconductor according to the present invention.

<Explanation of symbols for the main parts of the drawings>

2: substrate 20: III-V compound semiconductor heterojunction structure

22: buffer layer 24: channel layer

26: high band gap layer 28: cap layer

30: etch stop layer 32: gate recess

42, 44 Source and drain region 50 Metal gate

60 photoresist film 62 photoresist pattern

70: mask

Claims (9)

Board; A cap layer made of a III-V compound semiconductor material and sequentially stacked on the substrate, the cap layer made of a III-V compound semiconductor material including a buffer layer, a channel layer, a high band gap layer, and Sb to provide a gate recess; Heterojunction structure of the III-V compound semiconductor; Source and drain regions in ohmic contact with the cap layer; And FET using a III-V compound semiconductor comprising a metal gate is a Schottky junction to the gate recess. The method according to claim 1, The high band gap layer is a FET using a III-V compound semiconductor made of a III-V compound semiconductor material except Sb. The method according to claim 1, A FET using a III-V compound semiconductor made of a III-V compound semiconductor material other than Sb, further comprising an etch stop layer interposed between the high band gap layer and the cap layer. The method according to any one of claims 1 to 3, The III-V compound semiconductor material is a FET using a III-V compound semiconductor including AlGaAs, GaAs, InGaAs, InAs, GaSb. (a) sequentially depositing a buffer layer, a channel layer, and a high band gap layer made of a III-V compound semiconductor material on the substrate; (b) depositing a cap layer of III-V compound semiconductor material including Sb on the high bandgap layer; (c) ohmic contacting the source and drain regions spaced apart from each other on the cap layer; (d) applying a photoresist to cover the source and drain regions and the cap layer and selectively exposing with a mask; (e) developing the photoresist with a developer containing TMAH to form a photoresist pattern exposing the source and drain regions, and simultaneously removing a cap layer between the source and drain regions exposed by the photoresist pattern; Forming a gate recess; (f) removing the photoresist pattern; And and (g) Schottky bonding a metal gate to the gate recess. The method according to claim 5, The developer of step (e), FET manufacturing method using a III-V compound semiconductor consisting of 97 to 99% by weight of water and 1 to 3% by weight of TMAH based on the total weight. The method according to claim 5, The high band gap layer of step (a) is a FET manufacturing method using a III-V compound semiconductor made of a III-V compound semiconductor material except Sb. The method according to claim 5, After the step (a) and before the step (b), the FET manufacturing method using a III-V compound semiconductor further comprising the step of laminating an etch stop layer made of III-V compound semiconductor material except Sb on the high band gap layer . The method according to any one of claims 5 to 8, The III-V compound semiconductor material is a FET manufacturing method using a III-V compound semiconductor containing AlGaAs, GaAs, InGaAs, InAs, GaSb.

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