KR20100077434A - Liquid crystal display and driving method thereof - Google Patents

Abstract

According to an embodiment of the present invention, a liquid crystal panel includes subpixels arranged in a matrix in a display area and dummy pixels disposed in a non-display area; A gate driver supplying a gate signal to the liquid crystal panel; A data driver supplying a data signal to the liquid crystal panel; Gate wirings that are wired to the liquid crystal panel and transfer gate signals output from the gate driver; And data lines wired to the liquid crystal panel and transferring data signals output from the data driver, wherein the data driver copies the m-second data signals supplied to the m-second data wires at a last time. Provided is a liquid crystal display including a signal converter for supplying to the m-th data line positioned, and copying the third data signal supplied to the third data line and supplying the third data signal to the first data line.

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY AND DRIVING METHOD THEREOF}

Embodiments of the present invention relate to a liquid crystal display and a driving method thereof.

With the development of information technology, the market for a display device, which is a connection medium between a user and information, is growing. Accordingly, flat panel displays (FPDs), such as liquid crystal displays (LCDs), organic light emitting diodes (OLEDs), and plasma display panels (PDPs), may be used. Usage is increasing. Among them, a liquid crystal display device capable of realizing high resolution and capable of large size as well as small size is widely used.

Here, the liquid crystal display device is classified into a light receiving display device. Such a liquid crystal display may display an image by receiving a light source from a backlight unit disposed under the liquid crystal panel. Such a liquid crystal display device is largely composed of a transistor array substrate and a color filter substrate. A transistor including a gate, a semiconductor layer, a source and a drain, and a subpixel including a pixel electrode connected to a source or a drain of the transistor are formed on the transistor array substrate. A color filter, a black matrix, and the like are formed on the color filter substrate.

Conventional liquid crystal displays remove flicker due to a decrease in the luminance component and the frequency component of the AC component caused by the inversion of a specific frame while eliminating the interlace afterimage technique that is a problem in a television (TV). Measures should be taken to eliminate the phenomenon.

Embodiments of the present invention for solving the above-mentioned problems of the background art, while eliminating the interlaced afterimage technology that is a problem in television, flicker due to the reduction of the frequency component and the luminance difference of the AC component caused by the inversion of a particular frame The present invention provides a liquid crystal display and a driving method thereof capable of eliminating the phenomenon.

Embodiments of the present invention provide a liquid crystal panel including subpixels arranged in a matrix form in a display area and dummy pixels disposed in a non-display area. A gate driver supplying a gate signal to the liquid crystal panel; A data driver supplying a data signal to the liquid crystal panel; Gate wirings that are wired to the liquid crystal panel and transfer gate signals output from the gate driver; And data lines wired to the liquid crystal panel and transferring data signals output from the data driver, wherein the data driver copies the m-second data signals supplied to the m-second data wires at a last time. Provided is a liquid crystal display including a signal converter for supplying to the m-th data line positioned, and copying the third data signal supplied to the third data line and supplying the third data signal to the first data line.

The dummy pixels include m-th dummy pixels arranged to correspond to odd rows of the m-th column so as to receive a data signal from the m-th data line, and dummy data of the first column to receive a data signal from the first data line. It may include first dummy pixels disposed to correspond to even rows.

The m-th data signal may be supplied to the m-th dummy pixels, and the first data signal may be supplied to the first dummy pixels.

The data lines may be wired so that subpixels arranged in odd lines may receive data signals from data lines passing through the corresponding lines, and the subpixels arranged in even lines may be wired so as to receive data signals from data lines passing through the next column. have.

The signal converter may control the polarity control signal supplied to the data driver so that the m-th data signal and the first data signal are supplied to the m-th data line and the first data line.

The sub pixels may be arranged in order of red, green, and blue sub pixels in the direction in which the data lines are wired.

On the other hand, an embodiment of the present invention, the step of supplying a gate signal to the gate wirings wired to the liquid crystal panel; And supplying a data signal to the data wires wired to the liquid crystal panel, copying the m-second data signal supplied to the m-th data wire, and supplying the data signal to the m-th data wire located last. A method of driving a liquid crystal display device is provided by copying a third data signal supplied to a third data line and supplying the third data signal to a first data line.

The m-th data signal may be supplied to m-th dummy pixels positioned in the non-display area of the liquid crystal panel, and the first data signal may be supplied to first dummy pixels located in the non-display area of the liquid crystal panel. have.

Embodiments of the present invention can eliminate flicker generation due to a decrease in the luminance component and the frequency component of the AC component caused by the inversion of a specific frame while eliminating the interlaced afterimage technique that is a problem in a television. There is an effect of providing a liquid crystal display device and a driving method thereof.

Hereinafter, with reference to the accompanying drawings, the specific content for the practice of the present invention will be described.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, the liquid crystal display according to the exemplary embodiment of the present invention includes a liquid crystal panel 110, a timing controller 120, a gate driver 130, a data driver 140, a lamp driver 150, and a lamp. The unit 160 may be included.

In the liquid crystal panel 110, a liquid crystal layer is formed between two substrates. The liquid crystal panel 110 includes subpixels R, G, and B arranged in a matrix by a cross structure of the gate lines G1 to Gn and the data lines D1 to Dm. The sub pixels R, G, and B may be arranged in the order of red, green, and blue sub pixels R, G, and B in the direction in which the data lines D1 to Dm are wired.

Gate wirings G1 to Gn, data wirings D1 to Dm, TFTs and a storage capacitor Cst are formed on the first substrate of the liquid crystal panel 110, and the second substrate of the liquid crystal panel 110 is formed. A black matrix, a color filter, and the like are formed on the top. The liquid crystal layer is driven by an electric field formed between the pixel electrode and the common electrode connected to the TFT. On the other hand, the common electrode is formed on the second substrate in the case of the vertical electric field driving method, such as twisted nematic (TN) mode and vertical alignment (VA) mode, and is in The same horizontal electric field driving method is formed on the first substrate together with the pixel electrode. The polarizing plate is attached to the outside of the first substrate and the second substrate of the liquid crystal panel 110, and the pre-tilt angle of the liquid crystal is provided inside the first substrate and the second substrate of the liquid crystal panel 110. An alignment film for setting is formed.

The timing controller 120 supplies the digital video data RGB to the data driver 140. The timing controller 120 may transmit the digital video data and the mini LVDS clock to the data driver 140 by mini-low voltage differential signaling (LVDS).

The timing controller 120 multiplies the timing signals such as the vertical sync signal Vsync, the horizontal sync signal Hsync, the data enable signal Data Enable, and the dot clock CLK by n times to multiply the input frame frequency at 60 Hz. An operation timing of the data driver 140 and the gate driver 130 may be controlled at a frame frequency multiplied by n times n (n is a positive integer of 2 or more). Since the timing controller 120 may determine the frame period by counting the data enable signal of one horizontal period, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync among the timing signals input to the timing controller 120. ) May be omitted.

The liquid crystal panel 110 displays video data at a frame frequency of 60 × n Hz such as a frame frequency of 120 Hz, a frame frequency of 180 Hz, or a frame frequency of 240 Hz by the frame frequency multiplication of the timing controller 120 to increase the video response speed. You can do it fast. The frame double speed driving technique of the timing controller 120 is proposed by Korean Patent Application Publication No. 10-2008-0002304, Korean Patent Application Publication No. 10-2008-0063435, Korean Patent Application No. 10-2008-0112933, etc. previously proposed by the present applicant. It can be applied by double speed restraint driving technology. The control signals generated by the timing controller 120 include a gate timing control signal for controlling the operation time of the gate driver 130 and a data timing control signal for controlling the operation timing of the data driver 140 and the polarity of the data voltage. It may include.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (Gate Output Enable, GOE), and the like. The gate start pulse GSP is applied to the gate drive IC generating the first gate pulse (or scan pulse). The gate shift clock GSC is a clock signal commonly input to gate drive ICs and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output of the gate drive ICs. The gate timing control signal is multiplied by n times according to the frame frequency by the timing controller 120.

The data timing control signal includes a source start pulse (Source, Start Pulse, SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable signal (Source Output Enable, SOE). It includes. The source sampling clock SSC and the source output enable signal SOE are multiplied according to the frame frequency by the timing controller 120, but the polarity control signal POL is divided by n so that the frequency is later than the frame frequency. The source start pulse SSP controls a data sampling start time of the data driver 140. The source sampling clock SSC is a clock signal that controls a sampling operation of data in the data driver 140 based on a rising or falling edge. The polarity control signal POL controls the vertical polarity of the data voltage output from the data driver 140. The source output enable signal SOE controls the output of the data driver 140. If the digital video data and the mini LVDS clock are transmitted between the timing controller 120 and the data driver 140 in the mini LVDS scheme, the first clock generated after the reset signal of the mini LVDS clock serves as a start pulse, so that the source start pulse ( SSP) may be omitted.

The lamp driver 150 may control the lamp unit 160 by receiving the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync from the timing controller 120.

The lamp unit 160 includes a Cold Cathode Fluorescent Lamp (CCFL), a Hot Cathode Fluorescent Lamp (HCFL), an External Electrode Fluorescent Lamp (EEFL), and a Light Emitting Diode (Light Emitting). Diode: LED) may be selected from, but is not limited thereto.

Hereinafter, subpixels and dummy pixels disposed in the liquid crystal panel will be described with reference to FIG. 2.

2 is a schematic layout view of subpixels and dummy pixels disposed in a liquid crystal panel.

As shown in FIG. 2, the liquid crystal panel 110 includes subpixels SP disposed in a matrix form in the display area AA and dummy pixels DP1 and DPm disposed in the non-display area NA. It may include. The subpixels SP disposed in the display area AA are defined as actual pixels representing an image on the liquid crystal panel 110, and the dummy pixels DP1 and DPm disposed in the non-display area NA It is defined as dummy pixels that do not represent an image on the liquid crystal panel 110.

The subpixels SP disposed on the liquid crystal panel 110 may receive a gate signal from the gate driver 130 connected to the gate lines (not shown), and the data driver connected to the data lines D1 to Dm. The data signal may be supplied from the 140.

The data lines D1 to Dm are wired so that subpixels arranged in odd lines receive a data signal from the data line passing through the corresponding line, and the subpixels arranged in even lines receive the data signal from the data line passing through the next column. It can be wired to be supplied. For example, in the case of the subpixels arranged on the odd line of the second data line, the second pixel is connected to the second data line D2 passing through the line so that the data signal can be supplied from the second data line D2. In the case of the subpixels arranged on the even lines, the subpixels are connected to the third data line D3 passing through the next line to receive the data signal from the third data line D3.

The dummy pixels DP1 and DPm include the N-th dummy pixels DPm disposed corresponding to the odd rows of the N-th column so as to receive a data signal from the N-th data line Dm, and the first data line. The first dummy pixels DP1 may be disposed to correspond to even rows of the first column so as to receive a data signal from the D1.

Hereinafter, the data driver will be described with reference to FIG. 3.

3 is a configuration diagram of a data driver.

As shown in FIG. 3, the data driver includes a shift register 141, a data register 142, a first latch 143, a second latch 144, and a digital-to-analog converter (hereinafter referred to as “DAC”). 145, an output unit 146, and the like.

The shift register 141 shifts the data sampling clock according to the source sampling clock SSC supplied from the timing controller 120. In addition, the shift register 141 transfers a carry signal CAR to a shift register 141 of a source driver IC of a neighboring next stage.

The data register 142 temporarily stores the digital video data RGB supplied from the timing controller 120 and supplies the data RGB to the first latch 143. The first latch 143 samples and latches the digital video data RGB according to a data sampling clock sequentially supplied from the shift register 141, and then simultaneously outputs the latched data RGB. The second latch 144 latches the data RGB supplied from the first latch 143 and then synchronizes with the second latch 144 of other source drive ICs in response to the source output enable signal SOE. The latched data RGB is simultaneously output.

The DAC 145 may include a P-decoder supplied with the positive gamma reference voltage GH, an N-decoder supplied with the negative gamma reference voltage GL, and an output of the P-decoder in response to the polarity control signal POL. It contains a multiplexer to select the output of the N-decoder. The P-decoder decodes the digital video data RGB supplied from the second latch 144 and outputs a positive gamma compensation voltage corresponding to the gray level value of the data, and the N-decoder from the second latch 144. The supplied digital video data RGB is decoded, and a negative gamma compensation voltage corresponding to the gray scale value of the data is output. The multiplexer alternately selects a positive gamma compensation voltage and a negative gamma compensation voltage in response to the polarity control signal POL, and outputs the selected positive / negative gamma compensation voltage as a positive / negative analog video data voltage. .

The output unit 146 shorts the neighboring data output channels during the high logic period of the source output enable signal SOE, outputs an average value of the neighboring data voltages, and charges the charge share voltage through the output buffer. ) Is supplied to the data lines D1 to Dm, and then the positive / negative analog video data voltage is supplied to the data lines D1 to Dm.

The signal converter 148 copies the m-th data signal supplied to the m-second data line Dm-2, and supplies the copied m-th data signal to the m-th data line Dm positioned last. The polarity control signal POL may be controlled to copy the third data signal supplied to the third data line D3 and to supply the first data line D1. Accordingly, the m-th data signal may be supplied to the m-th dummy pixels DPm, and the first data signal may be supplied to the first dummy pixels DP1. The signal converter 148 may be configured to copy the data signal in the above form using a flip register, but is not limited thereto. In addition, in the exemplary embodiment, the signal converter 148 is included in the data driver 140, but it may be located outside the data driver 140.

Hereinafter, the pattern of the liquid crystal panel according to the output waveform of the data signal output from the data driver will be described separately into Comparative Examples and Examples.

4 is a diagram for explaining a comparative example, FIG. 5 is a diagram for explaining an embodiment of the present invention, FIG. 6 is an output waveform diagram of a data signal according to a comparative example, and FIG. 7 is data according to an embodiment. 8 is a diagram illustrating a pattern of a panel according to an output waveform of the data signal illustrated in FIG. 7.

4 and 5, in the comparative example and the embodiment, the subpixels SP and the dummy pixels DP1 and DPm are arranged in the same manner as described above with reference to FIG. 2.

The comparative example and the embodiment described above can eliminate the interlace afterimage technology which is a problem in the television (TV). In addition, it is possible to eliminate a flicker generation phenomenon due to the reduction of the frequency component and the luminance difference of the AC component caused by the inversion of a specific frame.

However, the comparative example and the embodiment are similar in that the data driver is controlled to copy a part of a specific data signal and supply it to another data wiring in order to solve the above problem. However, the method according to the comparative example has a disadvantage in that the first and last vertical lines displayed on the panel may display a brighter or darker screen than other areas. On the other hand, the method according to the embodiment has the advantage that all vertical lines displayed on the panel can display the same screen. Hereinafter, a comparative example and an Example are demonstrated.

First, in the comparative example shown in FIG. 4, the data driver is supplied to the m-th data line Dm-1 as the data signal to be supplied to the m-th data line Dm of the odd line. Copy the first data signal and supply it. The m-th data signal supplied to the m-th data line Dm positioned at the end of the odd-numbered line is copied and supplied as the data signal to be supplied to the first data line D1 of the even line.

In the comparative example, the last data signal supplied to the screen driving is the m-th dummy pixel DPm of the first line-> m-th subpixel SPm-1 of the second line-> third line M-th dummy pixel DPm of the m-th subpixel SPm−1 of the fourth line. And the data signal supplied before the last on the screen drive is the m-second sub-pixel (SPm-2) of the first line-> m-third sub-pixel (SPm-3)-> three of the second line The m-th subpixel SPm-2 of the first line is supplied in order of the m-th subpixel Spm-3 of the fourth line.

In the comparative example, assuming that the black series is 10 and the white series is 250, the output waveform of the data signal according to the driving method of the comparative example is described numerically as follows.

Referring to FIG. 6 (Dm), the last data signal supplied on the screen driving is the m-th dummy pixel DPm of the first line: "250"-> m-th sub-pixel of the second line (SPm-1): "250"-> mth dummy pixel of the third line DPm: "250"-> m-1th subpixel of the fourth line SPm-1: "250" Appears.

Referring to FIG. 6 (Dm-1), the data signal supplied before the last on the screen driving is the m-th subpixel SPm-2 of the first line: “0”-> of the second line. M-th subpixel SPm-3: "250"-> m-th subpixel of third line SPm-2: "0"-> m-th sub-3rd of fourth line Pixel SPm-3: Appears in the order of "250".

In the case of the driving method according to the comparative example, as shown in FIG. 6 (Dm), the voltage corresponding to "250" of the data signal supplied last in the screen driving is maintained. However, as shown in FIG. 6 (Dm-1), the voltages corresponding to "0" and "250" are repeated for the data signal supplied before the last time in the screen driving. In this case, it can be seen that the rising time of the voltage corresponding to the data signal supplied last before the screen driving appears relatively faster than the voltage corresponding to the data signal supplied last in the screen driving.

When the data signal output from the data driver is the same, the liquid crystal panel should display the same black series value on odd lines and the same white series value on even lines. As shown in "PT" of (a) of FIG. 8, the m-th subpixels SPm-1, which receive the data signal supplied before the last one during screen driving, are positioned on different even lines. The gray level is brighter than the sub pixels. This is because, as described above, the rising time of the voltage corresponding to the data signal supplied before the last time of the screen driving is relatively fast.

On the other hand, in the embodiment shown in FIG. 5, the data driver is supplied to the m-th data line Dm-2 as the data signal to be supplied to the m-th data line Dm of the odd line. Copy and supply the second data signal. The third data signal supplied to the third data line D3 is copied and supplied as the data signal to be supplied to the first data line D1 of the even line.

In the exemplary embodiment, the last data signal supplied to the screen driving is the m-th dummy pixel DPm of the first line-> m-th sub-pixel SPm-1 of the second line-> third line M-th dummy pixel DPm of the m-th subpixel SPm−1 of the fourth line. And the data signal supplied before the last on the screen drive is the m-second sub-pixel (SPm-2) of the first line-> m-third sub-pixel (SPm-3)-> three of the second line The m-th subpixel SPm-2 of the first line is supplied in order of the m-th subpixel Spm-3 of the fourth line.

In the embodiment, assuming that the black series is 10 and the white series is 250, the output waveform of the data signal according to the driving method of the embodiment will be described as follows.

Referring to FIG. 7 (Dm), the last data signal supplied on the screen driving is the mth dummy pixel DPm of the first line: "0"-> m-1th subpixel of the second line. (SPm-1): "250"-> mth dummy pixel of the third line DPm: "0"-> m-1th subpixel of the fourth line (SPm-1): "250" Appears.

Referring to FIG. 7 (Dm-1), the data signal supplied before the last on the screen driving is the m-second sub-pixel SPm-2 of the first line: "0"-> of the second line. M-th subpixel SPm-3: "250"-> m-th subpixel of third line SPm-2: "0"-> m-th sub-3rd of fourth line Pixel SPm-3: Appears in the order of "250".

In the driving method according to the embodiment, as shown in (Dm) and (Dm-1) of FIG. 7, the data signal supplied to the last on the screen driving and the data signal supplied before the last on the screen driving are Voltages corresponding to "0" and "250" are repeated. In this case, it can be seen that the rising time of the voltage corresponding to the data signal supplied last on the screen driving and the voltage corresponding to the data signal supplied before the last on the screen driving are the same.

When the data signal output from the data driver is the same, the liquid crystal panel should display the same black series value on odd lines and the same white series value on even lines. As shown in " PT " of FIG. 8 (b), the embodiment includes the m-th-th sub-pixels SPm-1, which receive the data signal supplied before the last of the screen driving, and other even lines. The same gray level is expressed as the subpixels positioned at. This is because, as described above, the rising time of the voltage corresponding to the data signal supplied last and the data signal supplied last before the screen driving are the same.

The above embodiment may solve a phenomenon in which a specific area of the panel becomes brighter or darker than another area when using gray scale fixed in a black or white solid pattern as dummy data.

As described above, embodiments of the present invention remove flicker due to a decrease in the luminance component and the frequency component of an AC component caused by the inversion of a specific frame while eliminating an interlace afterimage technique which is a problem in a television. There is an effect of providing a liquid crystal display device and a driving method thereof capable of eliminating flicker occurrence.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. Therefore, the embodiments described above are to be understood as illustrative and not restrictive in all aspects. In addition, the scope of the present invention is shown by the claims below, rather than the above detailed description. Also, it is to be construed that all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts are included in the scope of the present invention.

1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention.

2 is a schematic layout view of subpixels and dummy pixels disposed in a liquid crystal panel;

3 is a configuration diagram of a data driver.

4 is a view for explaining a comparative example.

5 is a view for explaining an embodiment of the present invention.

6 is an output waveform diagram of a data signal according to a comparative example.

7 is an output waveform diagram of a data signal according to an embodiment.

8 is a view illustrating a pattern of a panel according to an output waveform of a data signal shown in FIG. 7;

<Explanation of symbols on main parts of the drawings>

110: liquid crystal panel 120: timing control unit

130: gate driver 140: data driver

150: lamp driving unit 160: lamp unit

141: shift register 142: data register

143: first latch 144: second latch

145: digital to analog converter 146: output unit

148: signal converter

Claims (8)

A liquid crystal panel including sub pixels arranged in a matrix form in the display area and dummy pixels arranged in the non-display area; A gate driver supplying a gate signal to the liquid crystal panel; A data driver supplying a data signal to the liquid crystal panel; Gate wirings connected to the liquid crystal panel to transfer gate signals output from the gate driver; And And data lines wired to the liquid crystal panel and transferring data signals output from the data driver. The data driver, Copies the m-th data signal supplied to the m-th data line, supplies it to the m-th data line located last, and copies the third data signal supplied to the third data line. And a signal converter for supplying the first data line. The method of claim 1, The dummy pixels, M-th dummy pixels arranged to correspond to odd rows of the m-th column so as to receive a data signal from the m-th data line; And first dummy pixels arranged to correspond to even rows of the first column to receive a data signal from the first data line. The method of claim 2, The m-th data signal is supplied to the m-th dummy pixels, And the third data signal is supplied to the first dummy pixels. The method of claim 1, The data wires, Sub-pixels arranged in odd lines are wired to receive data signals from data lines passing through the corresponding lines. And sub-pixels arranged in even lines are wired to receive a data signal from a data line passing through a next column. The method of claim 1, The signal converter, The m-th data signal and the first data signal And a polarity control signal supplied to the data driver so as to be supplied to the mth data line and the first data line. The method of claim 1, The subpixels, And red, green, and blue sub pixels in the direction in which the data lines are wired. Supplying a gate signal to gate wirings wired to the liquid crystal panel; And The data signal is supplied to the data wires wired to the liquid crystal panel, and the m-th data signal supplied to the m-second data wire is copied and supplied to the m-th data wire positioned last. And a third data signal supplied to the third data line is copied and supplied to the first data line. The method of claim 7, wherein The m-th data signal is supplied to m-th dummy pixels positioned in the non-display area of the liquid crystal panel, And the first data signal is supplied to first dummy pixels positioned in a non-display area of the liquid crystal panel.

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