KR20100070082A - Thin film transistor substrate and method of fabricating thereof - Google Patents

Abstract

Provided are a thin film transistor array panel having reduced number of masks and reduced defects, and a method of manufacturing the same. The thin film transistor array panel includes a gate wiring formed on an insulating substrate and including a gate electrode, an oxide active layer pattern formed on the gate wiring, and a source electrode and a drain electrode overlapping the gate electrode to form a transistor. And a data line formed on the oxide active layer pattern and a pixel electrode electrically connected to the drain electrode, wherein the oxide active layer pattern is formed in the transistor region and the pixel region.

Description

Thin film transistor substrate and method for manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array panel and a method of manufacturing the same, and more particularly, to a thin film transistor array panel having a reduced number of masks and a defect.

Liquid crystal display (LCD) is one of the most widely used flat panel display (FPD), and consists of two display panels with electrodes formed thereon and a liquid crystal layer interposed therebetween. A display device adjusts the amount of light transmitted by rearranging liquid crystal molecules of a liquid crystal layer by applying a voltage to an electrode.

One of the two display panels described above is a thin film transistor array panel, and a plurality of wirings are formed on the insulating substrate of the thin film transistor array panel. Representative methods for forming such wirings include a photolithography method in which constituent materials are laminated and patterned through a mask process. However, since the photolithography method involves many processes such as thin film deposition, photoresist coating, mask alignment, exposure, development, etching, strip, and the like, it causes an increase in processing time and a rise in product cost.

The lift-off method is researched as a method of reducing the number of such mask processes. For example, when forming the passivation layer and the pixel electrode of the thin film transistor array panel, first, the passivation layer is patterned using a photoresist pattern, a conductive material is laminated on the entire surface of the substrate, and then a photoresist pattern and a stripper are used. The conductive material for the upper pixel electrode is removed at the same time to form the pixel electrode.

However, although the process reduces the number of masks, the active layer pattern under the passivation layer may also be etched during the patterning of the passivation layer to cause wiring defects. In addition, when the gate insulating layer and the active layer pattern of the pixel area are removed during the process, an area in which the liquid crystal is not rubbed may be generated due to a step generated in the thin film transistor array panel, thereby reducing light transmittance.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a thin film transistor array panel in which the number of masks is reduced and defects are reduced.

Another object of the present invention is to provide a method of manufacturing a thin film transistor array panel in which the number of masks is reduced and defects are reduced.

The technical objects of the present invention are not limited to the above-mentioned technical problems, and other technical subjects not mentioned can be clearly understood by those skilled in the art from the following description.

A thin film transistor array panel according to an embodiment of the present invention for achieving the above technical problem,

Method of manufacturing a thin film transistor array panel according to an embodiment of the present invention for achieving the another technical problem,

Other specific details of the invention are included in the detailed description and drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Thus, in some embodiments, well known process steps, well known device structures and well known techniques are not described in detail in order to avoid obscuring the present invention. Like reference numerals refer to like elements throughout.

The terms spatially relative, "below", "beneath", "lower", "above", "upper" May be used to readily describe a device or a relationship of components to other devices or components. Spatially relative terms are to be understood as including terms in different directions of the device in use or operation in addition to the directions shown in the figures. For example, when flipping a device shown in the figure, a device described as "below" or "beneath" of another device may be placed "above" of another device. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in other directions, so that spatially relative terms can be interpreted according to orientation.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, “comprises” and / or “comprising” refers to the presence of one or more other components, steps, operations and / or elements. Or does not exclude additions.

Unless otherwise defined, all terms (including technical and scientific terms) used in the present specification may be used in a sense that can be commonly understood by those skilled in the art. In addition, the terms defined in the commonly used dictionaries are not ideally or excessively interpreted unless they are specifically defined clearly.

Hereinafter, a thin film transistor array panel according to a first exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2. 1 is a layout view of a thin film transistor array panel according to a first exemplary embodiment of the present invention. FIG. 2 is a cross-sectional view of a thin film transistor array panel according to a first exemplary embodiment of the present invention, taken along line AA ′ of FIG. 1.

1 and 2, the thin film transistor array panel includes various elements such as a thin film transistor formed on the insulating substrate 10.

The insulating substrate 10 may be made of glass or plastic such as soda lime glass or boro silicate glass.

Gate wirings 22 and 26 that transmit gate signals are formed on the insulating substrate 10. The gate lines 22 and 26 include a gate line 22 extending in one direction, for example, a horizontal direction, and a gate electrode 26 of the thin film transistor protruding from the gate line 22 to form a protrusion.

One end of the gate lines 22 and 26 may have a gate line end 29 formed by widening the width of the gate line 22. The gate wiring end 29 is connected to a gate pad portion 83 described later.

In addition, storage wirings 27 and 28 including a storage line 27 and a storage electrode 28 are formed on the insulating substrate 10. The storage line 27 may be formed in a horizontal direction substantially in parallel with the gate line 22. The storage electrode 28 may be branched from the storage line 27 to overlap the data line 62. The storage line 27 overlaps the pixel electrode 82, which will be described later, to form a storage capacitor that improves charge retention capability of the pixel.

The shape and arrangement of the storage wirings 27 and 28 may be modified in various forms, and when the storage capacitance generated due to the overlap of the pixel electrode 82 and the gate line 22 is sufficient, the storage wirings 27 and 28 may be modified. ) May not be formed.

The gate wirings 22 and 26 and the storage wirings 27 and 28 include aluminum-based metals such as aluminum (Al) and aluminum alloys, silver-based metals such as silver (Ag) and silver alloys, copper (Cu) and copper alloys, and the like. It may be made of a copper-based metal, molybdenum-based metals such as molybdenum (Mo) and molybdenum alloy, chromium (Cr), titanium (Ti), tantalum (Ta) and the like. In addition, the gate wirings 22 and 26, the storage line 27, and the storage electrode 28 may have a multilayer structure including two conductive layers (not shown) having different physical properties. One of these conductive films is a low resistivity metal such as aluminum-based metal, silver, so as to reduce the signal delay or voltage drop of the gate wirings 22 and 26 and the storage line 27 and the storage electrode 28. It consists of a series metal, a copper series metal, etc. In contrast, the other conductive layer is made of a material having excellent contact properties with other materials, in particular zinc oxide (ZnO), indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metals, chromium, titanium, tantalum and the like. A good example of such a combination is a chromium bottom film and an aluminum top film and an aluminum bottom film and a molybdenum top film. However, the present invention is not limited thereto, and the gate wirings 22 and 26 and the storage wirings 27 and 28 may be made of various metals and conductors.

A gate insulating film 30 made of, for example, silicon nitride (SiNx) is formed on the insulating substrate 10, the gate wirings 22 and 26, and the storage wirings 27 and 28. The gate insulating film 30 of this embodiment is formed on the entire surface of the insulating substrate 10 except for the gate wiring end 29. Specifically, the gate insulating film 30 is also formed on the pixel region. In the present specification, the “pixel area” means a unit area formed by crossing the gate line 22 and the data line 62.

An oxide active layer pattern 42 made of an oxide of a material selected from Zn, In, Ga, Sn, and a combination thereof is formed on the gate insulating layer 30. In the oxide active layer pattern 42, 'active' means an active material having electrical characteristics when a driving current is applied, and includes both a semiconductor and a metal oxide. For example, the oxide active layer pattern 42 may be made of any one material selected from the group consisting of InZnO, InGaO, InSnO, ZnSnO, GaSnO, GaZnO, GaZnSnO, GaInZnO, HfInZnO, and ZnO. The oxide active layer pattern 42 has excellent semiconductor characteristics by having an effective mobility of about 2 to 100 times greater than the hydrogenated amorphous silicon and having an on / off current ratio of 10 ⁵ to 10 ⁸ . Have. In the oxide active layer pattern 42, since the band gap is about 3.0 to 3.5 eV, leakage photocurrent does not occur with respect to visible light. Therefore, the afterimage of the oxide thin film transistor can be prevented, and since the light blocking film is not required to be formed under the oxide thin film transistor, the aperture ratio of the thin film transistor array panel can be increased. Group 3, group 4, group 5 or transition elements on the periodic table may be further included to improve the characteristics of the oxide semiconductor. In addition, the oxide active layer pattern 42 is in an amorphous state, but has an effective mobility of high charge, and the existing manufacturing process of amorphous silicon can be applied as it is, and thus it can be applied to a large area display device.

The oxide active layer pattern 42 is formed in the thin film transistor region and the pixel region in which the gate electrode 26, the source electrode 65, and the drain electrode 66 overlap. That is, the oxide active layer pattern 42 of the present embodiment is also formed on the pixel region to reduce the step difference between the elements formed on the thin film transistor array panel.

The light transmittance of the oxide active layer pattern 42 may be 80 to 95%. If the light transmittance is less than 80%, the light transmittance of the pixel region may be lowered, resulting in a decrease in light efficiency.

The data lines 62, 65, 66, and 67 are formed on the oxide active layer pattern 42 and the gate insulating layer 30. The data lines 62, 65, 66, 67 are formed in the vertical direction, for example, a data line 62 defining a pixel by crossing the gate line 22, and branched from the data line 62 to be an oxide active layer. A source electrode 65 extending to an upper portion of the pattern 42 and an oxide active which is separated from the source electrode 65 and opposes the source electrode 65 around the channel portion of the gate electrode 26 or the oxide thin film transistor. The drain electrode 66 is formed on the layer pattern 42.

As illustrated in FIG. 2, the data lines 62, 65, 66, and 67 may directly contact the oxide semiconductor pattern 42 to form ohmic contacts. In order to form an ohmic contact, the data lines 62, 65, 66, and 67 may be formed of a single layer or multiple layers made of Ni, Co, Ti, Ag, Cu, Mo, Al, Be, Nb, Au, Fe, Se, or Ta. It is desirable to have a membrane structure. Examples of the multi-layer structure include a double film such as Ta / Al, Ta / Al, Ni / Al, Co / Al, Mo (Mo alloy) / Cu, or Ti / Al / Ti, Ta / Al / Ta, Ti / Al / And triple films such as TiN, Ta / Al / TaN, Ni / Al / Ni, Co / Al / Co and the like. However, the data lines 62, 65, 66, 67 are not limited to the above-described materials, and the data lines 62, 65, 66, 67 and the oxide active layer pattern 42 do not directly contact each other. An ohmic contact layer (not shown) for the ohmic contact may be further included.

The source electrode 65 overlaps at least a portion of the oxide active layer pattern 42, and the drain electrode 66 faces the source electrode 65 with respect to the channel portion of the oxide thin film transistor, and the oxide active layer pattern 42 At least a portion overlaps.

The data line 62 is formed on the gate insulating film 30 and the oxide active layer pattern 42. At one end of the data line 62, a data line end 69 is formed, which is connected to the data pad portion 84. FIG.

An overetch protective film pattern 72 made of, for example, silicon nitride is formed on the data lines 62, 65, 66, 67, and the oxide active layer pattern 42. The overetch protective film pattern 72 of the present embodiment is not formed in the pixel region. Thus, the pixel electrode 82 is exposed to the outside. In the present specification, 'over-etching' means that the etching is concentrated during the formation of a certain element, so that the element does not protrude more than the lower element. The overetching passivation pattern 72 is formed to cover the data line 62 and the source electrode 65 and to cover a part of the drain electrode 66.

A separate contact hole (not shown) is not formed in the overetching passivation pattern 72, and the pixel electrode 82 directly contacts the side portion and the upper portion of the drain electrode 66.

The pixel electrode 82 may be made of a transparent conductor such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a reflective conductor such as aluminum. The pixel electrode 82 to which the data voltage is applied rotates the liquid crystal molecules of the liquid crystal layer (not shown) interposed between the thin film transistor array panel and the common electrode display panel (not shown) by generating an electric field together with the common electrode (not shown). .

Hereinafter, a method of manufacturing a thin film transistor array panel according to a second exemplary embodiment of the present invention will be described in detail with reference to FIGS. 2 and 3 to 11. 3 to 11 are cross-sectional views illustrating a method of manufacturing a thin film transistor array panel according to a second exemplary embodiment of the present invention in a step-by-step manner. For convenience of explanation, in the following embodiments, members having the same functions as the members shown in the drawings of the first embodiment are denoted by the same reference numerals, and therefore description thereof is omitted or simplified.

First, referring to FIGS. 2 and 3, gate wirings 22 and 26 including the gate electrode 26 are formed on the insulating substrate 10. Forming the gate lines 22 and 26 includes forming the storage lines 27 and 28. Specifically, the gate conductive layer is stacked on the insulating substrate 10 using, for example, sputtering, and the like, and then photo-etched to form the gate line 22, the gate electrode 26, and the storage wirings 27 and 28. .

Subsequently, a gate insulating film 30, an oxide active layer 40, and a gate wiring conductive film 60 are laminated on the resultant product. These materials can be deposited using, for example, chemical vapor deposition or sputtering.

Next, a photoresist layer (not shown) is applied and patterned on the data wiring conductive layer 60 to form photoresist patterns 112 and 114 for data wiring formation on the data wiring conductive layer 60. The photoresist patterns 112 and 114 for forming data wirings are formed of two regions having different thicknesses, and the photoresist pattern 112 for forming a data wiring having a thick thickness d1 includes a data line 62 and a source electrode 65. ) And the drain electrode 66 forming region, and the thin data line forming photoresist pattern 114 having a thickness d2 covers the space between the source electrode 65 and the drain electrode 66 and the pixel region. Meanwhile, some regions on the storage wirings 27 and 28 and the gate wiring ends 29 are exposed without being covered by the photoresist patterns 112 and 114 for forming data wirings. As described above, the photoresist patterns 112 and 114 for forming data lines having different thicknesses may be formed using a slit mask or a halftone mask.

Next, referring to FIG. 4, the exposed data wiring conductive layer 60 and the oxide active layer 40 are etched using the photoresist patterns 112 and 114 for forming the data wiring as an etching mask. The etching of the data wiring conductive layer 60 varies depending on the type, thickness, etc. of the data wiring conductive layer 60, but may be wet etching as a preferred example. Since the material constituting the data wiring conductive film 60 and the material constituting the oxide active layer 40 have a large etching selectivity, the oxide active layer pattern 42 is not etched when the data wiring conductive film 60 is etched. . Accordingly, the oxide active layer pattern 42 is etched using a separate etchant. When the hydrogenated amorphous silicon is used as the material constituting the oxide active layer pattern 42, the etching selectivity between the data wiring conductive layer 60 and the hydrogenated amorphous silicon is low, and thus, the hydrogenated amorphous silicon is also removed when the data wiring conductive layer 60 is etched. Since an active layer (not shown) does not remain in the pixel region, a large step may occur in the pixel electrode 82 formed in the pixel region in a subsequent process. In addition, when the hydrogenated amorphous silicon is also removed when the data wiring conductive layer 60 is etched, an undercut may occur under the data wiring conductive layer 60 to cause a wiring defect. This step difference and wiring defect can be prevented by leaving the layer pattern 42 in the lower portion of the pixel region and the conductive film 60 for data wiring.

Next, referring to FIGS. 4 and 5, the photoresist patterns 112 and 114 for forming data wirings are etched back, leaving the photoresist pattern 112 for forming a thick data wiring thick d2. The photoresist pattern 114 for forming data lines with a thin thickness d1 is removed. The thin data line formation photoresist pattern 112 can be removed by, for example, an ashing process using oxygen or the like.

5 and 6, the data wiring conductive film 60 is etched using the remaining photoresist pattern photoresist pattern 112 as an etching mask. As a result, the source electrode 65 and the drain electrode 66 are formed, and the oxide active layer pattern 42 is exposed between the spaced spaces between the source electrode 65 and the drain electrode 66.

Subsequently, referring to FIG. 7, a protective film 70 is laminated on the resultant, for example, using CVD. Photoresist patterns 212 and 214 are formed. The photoresist patterns 212 and 214 include a first region 212 having a thin thickness d3 and a second region 214 having a thick thickness d4. The first region 212 is formed on the passivation layer 70 over a portion of the drain electrode 66 in contact with the pixel electrode (see 82 in FIG. 2). The first region 212 is formed to have a smaller thickness than the second region 214 by exposing the photoresist material with, for example, a slit mask. The second region 214 is entirely blocked by a mask and is not exposed, and exposes the pixel region and the gate wiring end 29.

Next, referring to FIGS. 7 and 8, the protective layer 70 is first etched using the photoresist patterns 212 and 214 as an etching mask to form the protective layer pattern 71 and the gate insulating layer 30. Etch Since the passivation layer 70 and the oxide active layer pattern 42 have a high etching selectivity, the oxide active layer pattern 42 and the gate insulating layer 30 under the etching of the passivation layer 70 in the pixel region are not etched. And remain in the pixel region. The protection layer 70 may be etched by dry etching. In such primary etching, overetching of the passivation layer 70 may hardly occur. The etching gas of the primary etching may include, for example, CF ₄ , SF ₆ , CHF ₃ , O _2, or a combination thereof, and the etching rate may be controlled by adjusting the combination of components or the composition ratio of these combinations.

8 and 9, an etch back process of removing the first region 212 using a stripper is performed. In this case, the thickness of the second region 214 is also reduced.

Next, referring to FIGS. 9 and 10, the protective layer pattern 71 may be secondly etched using the second region 214 as an etching mask to form the overetch protective layer pattern 72. As a result, an undercut in which the second region 214 protrudes from the overetch protection layer pattern 74 occurs in the second region 214, and the drain electrode 66 is exposed. In this case, the secondary etching gas may be the same as the above-described primary etching gas, or a combination of components or a composition ratio of these combinations may be different.

As a result of the above-described primary etching and secondary etching, the drain electrode 66 is exposed and the oxide active layer pattern 42 of the pixel region is exposed. Meanwhile, the gate wiring end 29 exposed during the process described with reference to FIG. 8 is still exposed. In the pixel region, the gate insulating layer 30 and the oxide active layer pattern 42 are present on the insulating substrate 10.

Next, referring to FIGS. 10 and 11, a conductive material 80 for a pixel electrode including zinc oxide, for example, is deposited on the whole surface of the resultant using a deposition method such as sputtering. Specifically, the conductive material 80 for the pixel electrode may be made of ITO or IZO. A portion of the conductive material 80 for the pixel electrode is directly stacked on the thinned second region 214 and the remaining portion is directly on the exposed structure not covered by the second region 214. In this case, the conductive material 80 for the pixel electrode does not have good step coverage, and thus the conductive material 80 for the pixel electrode is not stacked on the undercut formation region of the second region 214 and the overetch protection layer pattern 72. That is, the pixel electrode conductive material 80 stacked in the second region 214 and the pixel electrode conductive material 80 stacked in other portions are not connected to each other and cut at the end of the second region 214. It includes a site. Thereafter, a stripper is injected into the cutout portion of the conductive material 80 for the pixel electrode to remove the second region 214 and the conductive material 80 for the pixel electrode located thereon. Specifically, for example, a stripper containing an amine, glycol, or the like is injected into the above-described incision site by a spray method or a dip method and contacted with the first region 212 of the photoresist patterns 212 and 214. The second region 214 is dissolved to release the second region 214 from the overetch protection film pattern 72, and at the same time, the conductive material 80 for the pixel electrode on the second region 214 is also removed.

As a result, the pixel electrode 82, the gate pad portion 83, and the data pad portion (see 84 in FIG. 1) as shown in FIG. 2 are formed. The pixel electrode 82 of this embodiment is formed on the gate insulating film 30 and the oxide active layer pattern 42 so as to be in direct contact with the oxide active layer pattern 42. Accordingly, fewer steps are generated in the pixel electrode 82, so that wiring defects are reduced, and the area where the liquid crystal is not rubbed is reduced.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

1 is a layout view of a thin film transistor array panel according to a first exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of a thin film transistor array panel according to a first exemplary embodiment of the present invention, taken along line AA ′ of FIG. 1.

3 through 11 are cross-sectional views illustrating a method of manufacturing a thin film transistor array panel according to a second exemplary embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

10: insulating substrate 22: gate line

26: gate electrode 27: storage electrode

28: storage line 29: gate wiring end

30: gate insulating film 40: oxide active layer

42, 44: oxide active layer pattern

60: conductive film for data wiring 62: data line

65 source electrode 66 drain electrode

69: end of data wiring 70: protective film

71: protective film pattern 72: over-etched protective film pattern

82: pixel electrode 83: gate pad portion

84: data pad portion 110: photoresist film

112, 114, 212, and 214: photoresist film pattern

Claims (11)

A gate wiring formed on the insulating substrate and including the gate electrode; An oxide active layer pattern formed on the gate wiring; A data line formed on the oxide active layer pattern, the data line including a source electrode and a drain electrode overlapping the gate electrode to form a transistor; And A pixel electrode electrically connected to the drain electrode; The oxide active layer pattern is formed in the transistor region and the pixel region. The method of claim 1, The thin film transistor array panel of which the light transmittance of the oxide active layer pattern is 80 to 95%. The method of claim 1, A gate insulating film formed on the insulating substrate and the gate wiring; The pixel electrode is formed on the gate insulating layer and the oxide active layer pattern of the pixel region. The method of claim 1, A thin film transistor array panel further comprising an over-etching passivation pattern covering the data line and exposing the pixel electrode. The method of claim 4, wherein The over-etched protective film pattern includes silicon nitride, And the oxide active layer pattern is selected from the group consisting of InZnO, InGaO, InSnO, ZnSnO, GaSnO, GaZnO, GaZnSnO, GaInZnO, HfInZnO, and ZnO. Forming a gate wiring including a gate electrode on the insulating substrate; Forming a data line on the oxide active layer pattern, the data line including an oxide active layer pattern on the gate line and a source electrode and a drain electrode overlapping the gate electrode to form a transistor; And Forming a pixel electrode electrically connected to the drain electrode, The oxide active layer pattern is formed in the transistor region and the pixel region. The method of claim 6, The forming of the gate line may include forming a gate line end formed at one end of the gate line and a storage line overlapping the data line. The method of claim 7, wherein The forming of the oxide active layer pattern and the data line may include: And sequentially depositing an oxide active layer and a data wiring conductive film on the gate wiring, and etching and removing the oxide active layer and the data wiring conductive film on the gate wiring end and the storage wiring. The method of claim 8, The forming of the oxide active layer pattern and the data line may include: And forming the source electrode and the drain electrode spaced apart from each other by etching the conductive layer for data wiring so that the oxide active layer pattern remaining in the transistor region and the pixel region is not etched. The method of claim 6, Forming a gate insulating film on the insulating substrate and the gate wiring; Forming a protective film covering the data line; And And forming a passivation layer pattern by etching the passivation layer in the transistor region and the pixel region so that the gate insulating layer and the oxide active layer pattern remain. The method of claim 10, Overetching the passivation layer pattern to expose at least a portion of the drain electrode; Forming a photoresist pattern on the over-etched protective film pattern; Depositing a conductive material for a pixel electrode on the photoresist pattern; And And lifting the photoresist pattern and the conductive material for the pixel electrode to form a pixel electrode in direct contact with the oxide active layer pattern in the pixel region.

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