KR20100053291A - Memory module, memory channel and memory system - Google Patents

Abstract

PURPOSE: A memory module, a memory channel thereof, and a memory system thereof are provided to reduce the reflection loss in an operating frequency of a memory by interlinking a capacitive element connected to a resistive element in parallel to a transmit line. CONSTITUTION: A memory component(110) stores data. A transmit line(120) transmits data to a memory component. An impendence matching part is formed on the route of the transmit line. The impendence matching part(130) comprises a capacitive element. The resistive element is connected to in a transmission direction of data during a part of period of a transmission line. The capacitive element is connected to the resistive element in parallel.

Description

Memory Modules, Memory Channels, and Memory Systems {MEMORY MODULE, MEMORY CHANNEL AND MEMORY SYSTEM}

The present invention relates to a memory device, and more particularly, to a memory module, a memory channel, and a memory system using an impedance matching technique for improving channel characteristics.

Semiconductor memory devices have been developed with an emphasis on high integration and large capacity based thereon, and central processing devices such as computer systems have been developed with an emphasis on high speed. Therefore, the difference in operating speed between the central processing unit and the memory device is gradually increased, the operating speed of the memory device can be a major cause of limiting the performance of the entire system. In addition, as the memory system becomes faster and lower in power, the operating voltage of the system is gradually decreasing, and the voltage level of the signal used for data input / output in the memory system is also gradually decreasing according to the operating voltage. As the operation speed of a memory system is increased, a decrease in signal integrity due to impedance mismatch in a high speed signal transmission may be a problem, and thus a study on a memory bus channel structure to improve signal fidelity has been conducted.

In general, memory devices include bus channels, such as controllers, memory modules, and transmission lines. One or more memory components configured as a memory cell array for storing data are mounted in the memory module, and a bus channel connects the memory controller to the one or more memory modules through a memory socket. The problem of signal fidelity is generally related to signal transmission in the memory bus channel, which occurs when the signal passing through the bus channel degrades channel characteristics due to impedance mismatch when the memory system operates at a high frequency. Therefore, there is a need for a technology capable of improving signal fidelity as the operating speed of a semiconductor device increases.

Accordingly, one object of the present invention is to provide a memory module with improved signal fidelity.

Another object of the present invention is to provide a memory channel with improved signal fidelity.

It is another object of the present invention to provide a memory system with improved signal fidelity.

A memory module according to an embodiment of the present invention includes a memory component, a transmission line, and an impedance matching unit. The memory component stores data. The transmission line transmits the data to the memory component. The impedance matching unit is formed on a path of the transmission line and includes a capacitive element.

The impedance matching unit may include a resistive element connected in a transmission direction of the data in a portion of the transmission line, and the capacitive element connected in parallel with the resistive element.

In example embodiments, the resistive element and the capacitive element may be connected at an outer layer of a printed board of the memory module. The resistive element and the capacitive element may be elements packaged separately from each other, or may be a single device of two ports packaged together.

In example embodiments, the resistive element may be connected to the outer layer of the printed circuit board, and the capacitive element may be formed in a pattern of a printed substrate of the memory module. The capacitive element may include an upper pattern, a lower pattern, and a via. The upper pattern may be formed on the printed board and may be connected to one end of the resistive element. The lower pattern may be formed under the printed board. The via may connect the lower pattern with the other end of the resistive device.

The impedance matching unit may be connected to each of the memory components by at least the number of transmission bits of the data.

A memory channel according to an embodiment of the present invention is a transmission line for transmitting data to a memory cell array, a resistive element connected in the transmission direction of the data for impedance matching in a portion of the transmission line, and the impedance matching And a capacitive element connected in parallel with the resistive element.

A memory system according to an embodiment of the present invention includes a memory cell array, a host controller, a data bus, a resistive element, and a capacitive element. The memory cell array stores data. The host controller controls the writing and reading of the data. The data bus transfers data to the memory cell array under the control of the host controller. The resistive element is connected in a transmission direction of the data for impedance matching in a portion of the data bus. The capacitive element is connected in parallel with the resistor for the impedance matching.

According to the present invention, a memory module, a memory channel and a memory system connect a resistive element and a capacitive element connected in parallel to a transmission line to reduce reflection loss at an operating frequency of the memory, thereby improving signal fidelity.

In addition, since the resistive element and the capacitive element may be implemented as a package separately or as a pattern of a printed board, various design methods may be applied.

With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms and It should not be construed as limited to the embodiments described in.

As the inventive concept allows for various changes and numerous modifications, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features or numbers are present. It should be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. .

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. The same reference numerals are used for the same constituent elements in the drawings and redundant explanations for the same constituent elements are omitted.

1 is a block diagram illustrating a memory module according to an example embodiment.

Referring to FIG. 1, a memory module 100 according to an embodiment of the present invention includes a memory component 110, a transmission line 120, and an impedance matching unit 130. Memory component 110 includes a memory cell array for storing data. A plurality of memory components 110 may be mounted in one memory module. The transmission line 120 transmits data input through the port to the memory component 110. The impedance matching unit 130 includes a capacitive element 132 and is formed on the path of the transmission line 120 to match the impedance.

The impedance matching unit 130 includes a resistive element 131 and a capacitive element 132. The resistive element 131 is connected in a data transmission direction in a portion of the transmission line 120. For example, the resistive element 131 may be connected in series with the transmission line 120, and may be implemented with a stub resistor or the like. In addition, the resistive element 131 may be connected to a resistor packaged separately. The capacitive element 132 is connected in parallel with the resistive element 131 to match impedance. When the capacitive element 132 is connected to the resistive element 131 in parallel in the impedance matching unit 130, the impedance value is less when the signal is transmitted at a lower frequency than when the resistive element 131 is connected alone. When a signal is transmitted at high frequency, it can have a large impedance value. The impedance matching unit 130 may reduce the reflection loss in the operating frequency range of the memory module.

FIG. 2 is a block diagram illustrating a memory module of FIG. 1 connected to a memory controller through a socket.

Referring to FIG. 2, one or more memory modules 100 and 140 may be connected to the memory controller 210 through sockets 223 and 224. The memory controller 210 controls a data flow that is transmitted to the memory module 221 to be written or read. The transmission line 211 on the motherboard is connected to the transmission lines 120 and 160 of the memory modules 100 and 140 via the memory socket 223. Impedance matching units 130 and 170 are formed in some sections of the transmission lines 120 and 160 on the memory modules 100 and 140 as shown in FIG. 1. The impedance matching units 103 and 170 may be formed in a section between the sockets 223 and 224 and the memory components 110 and 150 among the sections of the transmission lines 211, 120 and 160.

The memory module illustrated in FIG. 2 may be a DDR3 memory module, a DDR4 memory module, or another memory module operating at a high frequency. The impedance matching units 100 and 140 may be connected to each memory component 110 and 150 by the number of transmission bits of data transmitted simultaneously. For example, in the case of a memory module operating in the X4 mode, four impedance matching units may be connected to one memory component, and in the case of a memory module operating in the X8 mode, eight impedance matching units may be connected to one memory component. In some embodiments, the number of impedance matching units may increase or decrease.

Resistance values of the resistive elements 131 and 171 included in the impedance matching units 130 and 170 and capacitances of the capacitive elements 132 and 172 may be experimentally obtained. According to an embodiment, when the on-die termination value is 40 ohms in the DDR3 memory module, the resistance value of the resistive elements 131 and 171 is 25 ohms, and the capacitance value of the capacitive elements 132 and 172 is 6 picofarads. May have

3 is a Smith chart illustrating impedance characteristics according to operating frequencies of a memory module according to the related art and a memory module according to an embodiment of the present invention.

Referring to FIG. 3, when the operating frequency of the memory module is 100 MHz to 3 GHz, the impedance curve 320 of the memory module according to the embodiment of the present invention is matched compared to the impedance curve 310 of the memory module according to the prior art. You can see that it is closer to the matching point.

4 is a diagram illustrating return loss according to a frequency of a memory module according to the related art and a memory module according to an embodiment of the present invention.

Referring to FIG. 4, for example, the return loss 420 of the memory module according to an embodiment of the present invention is further compared to the return loss 410 of the memory module according to the related art in an operating frequency range of 100 MHz to 2 GHz. It can be seen that low.

5 to 7 are block diagrams illustrating an impedance matching unit of a memory module in accordance with an embodiment of the present invention.

Referring to FIG. 5, in the memory module according to an exemplary embodiment, the resistive element 520 and the capacitive element 530 of the impedance matching unit 500 may be implemented by using a packaged element separated from each other. The packaged devices may be connected in parallel to each other at an outer layer of the printed board 510 of the memory module.

Referring to FIG. 6, in the memory module according to another exemplary embodiment, the resistive element 621 and the capacitive element 622 of the impedance matching unit 600 may be packaged together to be implemented as a single element 620 having two ports. Can be. The resistive element 621 and the capacitive element 622 packaged together as a single element 620 connect the two ports to each other at an outer layer of the printed board 610 of the memory module to form the resistive element 621 in the impedance matching unit 620. ) And the capacitive element 622 may be connected in parallel with each other.

Referring to FIG. 7, the resistive element 720 of the impedance matching unit 700 is connected to the outer layer of the printed circuit board 710 of the memory module in accordance with another embodiment, and the capacitive elements 731 and 732 are provided. May be formed as a pattern of the printed board 710 of the memory module.

The capacitive element may include an upper pattern 731, a lower pattern 732, and a via 740. The upper pattern 731 is formed on the printed board 710 and is connected to one end of the resistive element 720. The lower pattern 732 is formed under the printed board 710. The upper pattern 731 and the lower pattern 732 may be used to implement a capacitive element that provides a capacitance between the upper pattern 731 and the lower pattern 732. The via 740 connects the lower pattern 732 to the other end of the resistive element 720. In addition to the via 740, another pattern 733 may be used to connect the lower pattern 732 to the other end of the resistive element 720. In the impedance matching unit 700 of FIG. 7, the upper pattern 731 may be connected in the direction of the memory component, and the via 740 may be connected in the port direction of the memory module, or may be connected in the opposite direction.

8 is a block diagram illustrating a memory system according to an example embodiment.

The block diagram of the memory system 800 of FIG. 8 may correspond to the topology of the memory device of FIG. 2. Referring to FIG. 8, a memory system 800 according to an exemplary embodiment may include a memory cell array 811, 812, 813, 814, a host controller 820, a data bus 831A, 831B, 831C, 832A, 832B, 832C, 833A, 833B, 833C), and impedance matching portions 841, 842.

Data is stored in the memory cell arrays 811, 812, 813, and 814. In the case of a memory module, the memory cell arrays 811, 812, 813, and 814 may be packaged in a memory component and mounted on a printed board of the memory module. The host controller 820 controls the writing and reading of data transmitted to the memory cell arrays 811, 812, 813, and 814. The data buses 831A, 831B, 831C, 832A, 832B, 832C, 833A, 833B, and 833C transfer data of the memory cell arrays 811, 812, 813, and 814 under the control of the host controller 820. Data buses 831A, 831B, 831C, 832A, 832B, 832C, 833A, 833B, and 833C connect the host controller 820 and the memory cell arrays 811, 812, 813, 814 through connectors 851, 852. Can be. The data bus may be divided into several sections, and impedance characteristics may vary according to which section the impedance matching units 841 and 842 are connected. The impedance matching units 841 and 842 included in the memory system 800 of FIG. 8 are similar to the impedance matching unit 130 of the memory module 100 of FIG. 1. That is, the impedance matching unit 841 may include a resistive element connected in a data transmission direction and a capacitive element connected in parallel in a portion of the data bus.

The memory system 800 corresponds to an on-die termination value and a memory cell array of the host controller 120 according to a main mode (not shown) in which the host controller 820 is installed and an impedance value of the memory module. The on-die termination value of the memory module can be determined, and the resistance value of the resistive element of the impedance matching units 841 and 842 and the capacitance value of the capacitive element can be determined according to these values. In one embodiment, each device value for impedance matching may be determined according to an on-die termination value determined by a standard such as JEDEC. For example, a DDR3 memory system operating at 1333 MHz or 1600 MHz, the motherboard and line impedance is 40 ohms, the memory module has a line impedance of 60 ohms, the read on-die termination is 120 ohms, and the write on-die termination is 120 ohms. It can be ohms or 40 ohms. When a plurality of memory modules are connected, the write on-die termination value of the memory module to be written may be 120 ohms, and the other memory modules may be 40 ohms. In this case, the resistor and the capacitive element of the impedance matching part may have values of 25 ohms and 6 picofarads, respectively.

9A to 9D are eye diagrams for simulating a write operation and a read operation for a memory module according to the related art and a memory module according to an embodiment of the present invention.

9A is an eye pattern diagram simulating a write operation at an operating speed of 1333 Mbps for a memory module according to the related art and a memory module according to an embodiment of the present invention.

Referring to FIG. 9A, the aperture per unit interval in the eye pattern diagram simulating the memory module of the present invention is 62.4 percent, which is 62 percent per aperture in the eye pattern diagram of the memory module according to the prior art. That's about 6.4 percent improvement. Herein, the improved percentage value means the ratio of the aperture per unit section of the memory module according to the embodiment of the present invention to the aperture per unit section of the memory module in the related art.

9B is an eye pattern diagram simulating a read operation at an operating speed of 1333 Mbps for a memory module according to the related art and a memory module according to an embodiment of the present invention.

Referring to FIG. 9B, the aperture per unit section in the eye pattern diagram simulating the memory module of the present invention is 50.9 percent, an improvement of about 9.4 percent compared to the 55.7 percent aperture per unit section in the eye pattern diagram of the conventional memory module. .

FIG. 9C is an eye pattern diagram simulating a write operation at an operating speed of 1600 Mbps for a memory module according to the prior art and a memory module according to an embodiment of the present invention.

Referring to FIG. 9C, the aperture per unit interval in the eye pattern diagram simulating the memory module of the present invention is 55.2 percent, which is about 6.6 percent higher than the 59.9 percent aperture per unit interval in the eye pattern diagram of the conventional memory module. .

FIG. 9D is an eye pattern diagram simulating a read operation at an operating speed of 1600 Mbps for a memory module according to the prior art and a memory module according to an embodiment of the present invention.

Referring to FIG. 9D, the aperture per unit section in the eye pattern diagram simulating the memory module of the present invention is 35.3 percent, an improvement of about 29.7 percent compared to the 45.8 percent aperture per unit section in the memory module according to the prior art.

As described above, the memory module, the memory channel and the memory system according to an embodiment of the present invention can reduce the reflection loss at the operating frequency of the memory by connecting the resistive element and the capacitive element connected in parallel thereto to the transmission line. The fidelity of the signal can be improved. In addition, according to the embodiment, the resistive element and the capacitive element may be separately packaged or implemented as a pattern of a printed board, thereby applying various design methods.

A memory module, a memory channel, and a memory system according to an embodiment of the present invention connect a resistive element and a capacitive element connected in parallel to a transmission line to reduce reflection loss and improve signal fidelity at an operating frequency of the memory. In addition, according to the embodiment, the resistive element and the capacitive element may be separately packaged or implemented as a pattern of a printed board, thereby applying various design methods. The signal fidelity improvement technique using the impedance matching unit may be applied to DDR3 memory modules and the like, and may be applied to other memory types such as DDR4 memory modules.

As described above, the present invention has been described with reference to a preferred embodiment of the present invention, but those skilled in the art may vary the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. It will be understood that modifications and changes can be made.

1 is a block diagram illustrating a memory module according to an example embodiment.

FIG. 2 is a block diagram illustrating a memory module of FIG. 1 connected to a memory controller through a socket.

3 is a Smith chart illustrating impedance characteristics according to frequencies of a memory module according to the related art and a memory module according to an embodiment of the present invention.

4 is a diagram illustrating return loss according to a frequency of a memory module according to the related art and a memory module according to an embodiment of the present invention.

5 to 7 are block diagrams illustrating an impedance matching unit of a memory module in accordance with an embodiment of the present invention.

8 is a block diagram illustrating a memory system according to an example embodiment.

9A to 9D are eye diagrams for simulating a write operation and a read operation for a memory module according to the related art and a memory module according to an embodiment of the present invention.

Claims (10)

A memory component in which data is stored; A transmission line for transmitting the data to the memory component; And And an impedance matching part formed on a path of the transmission line and including a capacitive element. The method of claim 1, wherein the impedance matching unit A resistive element connected in a transmission direction of the data in a portion of the transmission line; And And the capacitive element connected in parallel with the resistive element. The method of claim 2, The resistive element and the capacitive element are connected to a printed circuit board outer layer of the memory module. The method of claim 3, The resistive element and the capacitive element are memory modules, characterized in that separated from each other packaged elements. The method of claim 3, And wherein the resistive element and the capacitive element are single ports of two ports packaged together. The method of claim 2, The resistive element is connected to the outer layer of the printed circuit board, and the capacitive element is formed in a pattern of a printed substrate of the memory module. The method of claim 6, wherein the capacitive element An upper pattern formed on the printed board and connected to one end of the resistive element; A lower pattern formed below the printed board; And And a via connecting the lower pattern to the other end of the resistive element. The memory module of claim 2, wherein the impedance matching unit is connected to each of the memory components by at least the number of transmission bits of the data. A transmission line for transferring data to the memory cell array; A resistive element connected in a transmission direction of the data for impedance matching in a portion of the transmission line; And And a capacitive element connected in parallel with said resistive element for said impedance matching. A memory cell array in which data is stored; A host controller which controls the writing and reading of the data; A data bus through which data is transferred to the memory cell array under control of the host controller; A resistive element connected in a transmission direction of the data for impedance matching in a portion of the data bus; And And a capacitive element connected in parallel with said resistor for said impedance matching.

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