KR20090112082A - Programming method of nonvolatile memory device - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides a method of programming a nonvolatile memory device that prevents underprogramming of a memory cell to be programmed. To this end, the present invention provides one circuit including one program operation and one verify operation, and a plurality of circuits. A repeating method for programming a nonvolatile memory device, comprising: searching for an underprogrammed memory cell and compensating for the found underprogrammed memory cell after a final verify operation of the plurality of loops; Improve the reliability of the memory device.

Description

Program method of nonvolatile memory device {METHOD FOR PROGRAMING NON-VOLATILE RANDOM ACCESS MEMORY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacturing technology of semiconductor devices, and more particularly, to a method of programming nonvolatile memory devices.

Among the semiconductor memory devices, nonvolatile memory devices do not erase stored data even when power supply is interrupted. A flash memory device represents a nonvolatile memory device.

1 is a circuit diagram illustrating a nonvolatile memory device.

Referring to FIG. 1, a memory cell block of a nonvolatile memory device includes a plurality of cell strings ST, and each cell string ST is connected to bit lines BL1 to BL3. In this case, for convenience of description, only three bit lines are illustrated, and it is preferable to include more bit lines.

In detail, each cell string ST has a structure in which a drain select transistor DST, memory cells Ca, C1 to Cn, and a source select transistor SST are connected in series. The source select transistor SST is connected to a common source line CSL.

The gates of the drain select transistors DST are connected to each other to form a drain select line DSL, and the gates of the source select transistors SST are connected to each other to form a source select line SSL. In addition, gates of the memory cells Ca to Cc and C1 to Cn are connected to each other to form word lines WL0 to WLn.

Meanwhile, nonvolatile memory devices perform program and erase operations. Recently, in order to narrow threshold voltage distributions of programmed memory cells, an ISPP (Increasement Step Pulse Program) type program operation has been in the spotlight.

The program operation of the ISPP method is as follows.

A program voltage of 15 V or more is applied to the selected word line WL0, and a pass voltage is applied to the remaining word lines WL1 to WLn so that the memory cells C1 to Cn are turned on. In addition, the first program operation is performed by applying a ground voltage (0V) to the bit line.

Subsequently, it is verified whether the threshold voltages of the memory cells Ca to Cc sharing the selected word line WL0 have risen to the target voltage.

If the threshold voltage does not rise to the target voltage, the secondary program operation is performed by raising the level of the program voltage. In addition, no additional program operation is performed on the memory cell whose threshold voltage rises to the target voltage.

However, the program characteristics of the memory cells Ca to Cc sharing the word line WL0 are different from each other. That is, a program speed of a specific memory cell, for example, the first memory cell Ca, a rising speed of a threshold voltage, may be faster than the remaining memory cells Cb and Cc. In this case, after performing the primary program operation, the amount of current flowing through each of the bit lines BL1 to BL3 is changed in the process of performing the verify operation.

For example, although the threshold voltage of the first memory cell Ca has risen higher than the threshold voltages of the remaining memory cells Cb and Cc even though the threshold voltage of the first memory cell Ca has not increased to the target voltage, the current flows to the remaining bit lines BL2 and BL3. The amount of current is greater than the amount of current flowing in the corresponding bit line BL1. Since the common source line CSL between the strings acts as a resistance component, the voltage at the common source line CSL is increased.

As a result, the voltage of the common source line CSL is increased before the precharge voltage of the bit line BL1 is discharged, so that the body bias of the first memory cell Ca is increased. Increases. This is called the noise of the common source line.

In addition, as the body bias of the first memory cell Ca increases, a phenomenon occurs such that the threshold voltage of the first memory cell Ca increases, and the threshold voltage of the first memory cell Ca reaches a target voltage. Although not high, it is determined to be higher than the target voltage. As a result, the first memory cell Ca is not further programmed, and the first memory cell Ca is programmed to be lower than the target voltage. This is called an under program.

When the under program occurs as described above, although the first memory cell Ca corresponds to the cell to be programmed, a malfunction may be detected in an erased state during a read operation, thereby deteriorating the reliability of the nonvolatile memory device. .

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a program method of a nonvolatile memory device which prevents an underprogram of a memory cell to be programmed.

According to one aspect of the present invention, there is provided a loop comprising one program operation and one verify operation, and a method of programming a nonvolatile memory device which repeats the loop a plurality of times, wherein After a final verify operation, there is provided a method of programming a non-volatile memory device comprising the step of retrieving the under-programmed memory cell and the compensation program of the retrieved under-programmed memory cell.

The program method of the nonvolatile memory device of the present invention, which is based on the above-described problem solving means, improves the margin for searching for an underprogrammed memory cell and compensates for the detected underprogrammed memory cell to compensate for the nonvolatile memory device. To improve the reliability.

Prior to describing the embodiment, the present invention is characterized in that after the program operation of the normal ISPP method, the under programmed memory cell is searched, and the searched under programmed memory cell is further programmed.

In particular, the step of searching for the under-programmed memory cell proceeds at a level higher than the voltage level of the final verify operation performed in the ISPP type program operation.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

2 is a flowchart illustrating a program operation of a nonvolatile memory device according to an exemplary embodiment of the present invention.

As shown in FIG. 2, the program operation of the nonvolatile memory device includes the steps of performing a normal ISPP program (S1), a step of shifting the verify voltage level upward (S2), and verifying with an elevated verify voltage. (S3), searching for underprogrammed memory cells (S4), extracting only underprogrammed memory cells (S5), and compensating program for extracted underprogrammed memory cells (S6). ).

Hereinafter, a timing diagram corresponding to the program operation as described above will be described with reference to FIG. 3.

As shown in Figs. 2 and 3, the step S1 of executing a normal ISPP scheme program includes one conference loop LOOP1 including one program operation PGM and one verification operation VER. And the above-described loop LOOP1 is repeated a plurality of times. At this time, in response to an increase in the number of loops, it is preferable to sequentially increase the program voltage level.

Next, an under programmed memory cell generated in a normal ISPP program is searched for. To this end, in the normal ISPP scheme, the voltage level of the final verify operation is shifted upward (S2), the verify is performed at the elevated verify voltage (S3), and the underprogrammed memory cell is searched. (S4) proceeds sequentially.

In this way, after the normal ISPP program operation is performed and the verification is performed with the increased verification voltage, the under programmed memory cell that is not searched in the final verify operation in the normal ISPP program operation may be searched.

4 is a diagram illustrating threshold voltage distribution diagrams of memory cells.

As shown in FIG. 4, the under-programmed memory cell UPGM is substantially a first verify voltage PV1-a first verify voltage PV1 is a verify voltage of a final verify operation in a program operation of a normal ISPP method. . Although the voltage level is lower, the verify operation looks like a voltage level higher than the first verify voltage PV1.

In this case, when the second verification voltage PV2 is verified as in the present invention, the under-programmed memory cell UPGM is located at a voltage level lower than the second verification voltage PV2, so that the search is possible. .

That is, the verification operation proceeding to the second verification voltage PV2 may also be expressed as an operation for sufficiently securing a margin of the verification operation in the program of the normal ISPP method.

The second verification voltage PV2 is higher than the first verification voltage PV1 and is a level capable of sufficiently searching for the underprogrammed memory cell UPGM generated in the verification operation performed by the first verification voltage PV1. It is preferable.

Subsequently, as shown in FIGS. 2 and 3, when the under programmed memory cell is not searched, the program operation of the nonvolatile memory device is terminated. Otherwise, the next step is performed.

That is, the underprogrammed memory cell is extracted (S5).

This is a step that proceeds because if an additional program voltage is applied to a normally programmed memory cell, it can be over programmed. That is, the step of extracting only the under-programmed memory cells to perform an additional program operation.

In addition, the normally programmed memory cell performs a program inhibit operation to prevent an over program.

Next, a step S6 of compensating for the extracted under programmed memory cell is performed.

In this case, it is desirable to evaluate a compensation program voltage level sufficient to prevent overprogramming the underprogrammed memory cell having an increased threshold voltage and apply it to the underprogrammed memory cell. That is, in the step S6 of compensating the underprogrammed memory cell, the compensation program voltage level must be evaluated.

And, in order to prevent overprogramming, the compensation program voltage is preferably at a voltage level lower than the final program voltage in the program of the normal ISPP scheme. This is because, as described above, the undervoltage of the underprogrammed memory cell is insufficient.

After the compensation program is performed, the program operation of the nonvolatile memory device is terminated.

FIG. 5 is a diagram illustrating a threshold voltage distribution diagram of a memory cell obtained through a program method of a nonvolatile memory device according to an exemplary embodiment of the present invention.

Here, the first verification voltage PV1 is a verification voltage level of a program operation of a normal ISPP method, and the second verification voltage PV2 is a voltage level of the verification operation S3 which is performed after the verification voltage is moved upward. .

As shown in FIG. 5, it can be seen that the under programmed memory cell UPGM, which is seen as a voltage level higher than the first verification voltage PV1, has moved to the program level.

This is because the under programmed memory cell UPGM, which has not been searched at the first verification voltage PV1, has been searched at the second verification voltage PV2 at a level higher than the first verification voltage PV1. This is because the programmed memory cell UPGM is compensated for.

Since the normal programmed memory cell is extracted and the compensation program voltage level is evaluated before the compensation program, the increase in the threshold voltage distribution right level is prevented. That is, the increase in the width of the threshold voltage distribution is prevented.

Therefore, after the program operation of the nonvolatile memory device according to the embodiment of the present invention, the width of the threshold voltage distribution of the memory cells decreases around the desired program threshold voltage level.

The embodiment of the present invention as described above is characterized in that after the program operation of the normal ISPP method, the under programmed memory cell is searched and the searched under programmed memory cell is further programmed.

The searching of the under programmed memory cell is performed at a level higher than that of the final verify operation performed in the ISPP program operation and at a voltage level sufficient to search for the under programmed memory cell.

As a result, the margin for searching for the underprogrammed memory cell is improved, and the detected underprogrammed memory cell is compensated for, thereby improving the reliability of the nonvolatile memory device.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill.

1 is a circuit diagram illustrating a nonvolatile memory device.

2 is a flowchart illustrating a program operation of a nonvolatile memory device according to an exemplary embodiment of the present invention.

3 is a timing diagram corresponding to the program operation of FIG.

4 is a diagram illustrating a threshold voltage distribution of memory cells.

5 is a diagram illustrating a threshold voltage distribution of a memory cell obtained through a program method of a nonvolatile memory device according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

S1: step of executing a normal ISPP method

S2: moving up the verify voltage level

S3: Step of performing verification with an increased verification voltage

S4: searching for the under programmed memory cell

S5: extracting only under programmed memory cells

S6: Compensation program for the extracted under programmed memory cell

Claims (5)

In one program loop including one program operation and one verification operation, and a method of programming a nonvolatile memory device repeating the loop a plurality of times, Retrieving an under programmed memory cell after a last verify operation of the plurality of loops; And Compensating for the found underprogrammed memory cell Program method of a nonvolatile memory device comprising a. The method of claim 1, The searching of the under programmed memory cell may include: Shifting the voltage level of the last verify operation upward; And And verifying the underprogrammed memory cell by performing verification with an elevated verification voltage. The method of claim 1, The programming of the compensation method includes the step of evaluating a compensation program voltage level. The method of claim 1, The programming of the compensation method, characterized in that the progress of the program voltage level lower than the voltage level of the last program operation of the plurality of loops. The method of claim 1, And extracting only the searched under programmed memory cells after searching for the under programmed memory cells.

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