KR20090069091A - How to Form an Overlay Vernier - Google Patents

Abstract

According to the present invention, the overlay vernier or alignment key is implemented as a plurality of holes in the SPT process, and the overlay measurement or the exposure process may be aligned in the overlay equipment or the exposure equipment using a light source having a wavelength of about 600 nm. Discuss possible techniques.

Description

Method for forming overlay vernier}

The present invention relates to a method of forming a semiconductor device, and more particularly, to overlay in a overlay device or an exposure device using a light source having a wavelength of about 600 nm by implementing the overlay vernier or alignment key in a plurality of holes in the SPT process An overlay vernier forming method capable of aligning a measurement or an exposure process.

In general, a lithography process is a process of performing exposure and development after applying a photoresist on a wafer, and is performed before an etching process or an ion implantation process requiring a mask.

As semiconductor devices are highly integrated, the size and pitch of patterns constituting a circuit are gradually decreasing.

As semiconductor devices become more integrated, the lithography process technology in the machining process refines the mask design to properly control the amount of light exiting the mask, develop new photosensitizers, and use scanners with high numerical aperture lenses. The technical limitations of the semiconductor device manufacturing apparatus are overcome by efforts such as developing a scanner and developing a modified mask.

However, due to limitations in exposure and resolution ability that proceed with current light sources, for example, KrF, ArF, etc., it is difficult to form a width and an interval of a desired pattern.

Accordingly, various studies for forming a photosensitive film pattern having a fine pattern size and spacing are continued.

One method is a double patterning technology (DPT) method for forming a pattern by performing two lithography processes, and another method is a space patterning technology (SPT) for forming a pattern using a spacer.

On the other hand, since the fabrication process of the integrated device is a process of forming a multi-layered pattern by applying a lithography process or the like, accurate alignment between upper and lower layer patterns is required.

The overlay accuracy is an index indicating the alignment between the upper and lower layer patterns formed at the front and rear stages of the process. This overlay accuracy acts as an important variable according to the high integration of the semiconductor device.

Here, overlay accuracy is measured using an overlay vernier formed in a scribe lane of the wafer.

The overlay vernier consists of the parent vernier (mother) formed in the lower layer in the previous process and the child vernier (son) formed in the current layer in the current process to measure the degree of misalignment to measure the alignment between the two layers. .

Typically, the parent vernier forms a pattern in the shape of a square strip of the same material as the actual pattern, and the vernier forms a square box type trench in a photoresist pattern.

In addition, the parent vernier forms a trench type or mesa type pattern according to the process of the lower layer, and the child vernier forms a trench type pattern to measure the parent vernier of the previous process in the current process. The method of forming the is mainly used.

A typical overlay vernier is an application that is implemented in a bar in bar, box in box, bar in box, or multiple rectangular patterns, depending on the shape of the parent vernier and the child vernier. Interpreted Model).

1A to 1D are cross-sectional views illustrating a method of forming an overlay vernier using a general SPT. Here, (i) is a top view and (ii) shows sectional drawing cut along A-A 'of (i).

Referring to FIG. 1A, a plasma enhanced oxide (PEOXIDE) and a first polysilicon are formed on a semiconductor substrate 110, and the first polysilicon and the plasma oxide layer are etched using a vernier mask. A first polysilicon pattern 114 and a plasma oxide layer pattern 112 having a rectangular mesa shape are formed. Here, the first polysilicon pattern 114 and the plasma oxide layer pattern 112 form a first vernier pattern 116. In addition, the method of forming the first vernier pattern 116 forms a hard mask material layer over the first polysilicon to pattern the first polysilicon. In this case, in general, the hard mask material layer may be formed of amorphous carbon, and a silicon nitride oxide layer (SiON) may be deposited on the amorphous carbon layer as needed. In addition, a photoresist is applied on the hard mask material layer and a photoresist pattern is formed through an exposure process using a vernier mask, and the hard mask material layer is etched using the photoresist pattern as an etching mask to form a hard mask pattern. do. At this time, BARC (Bottom Anti-Reflective Coating) may be applied under the photosensitive film, if necessary. Subsequently, the first polysilicon and the plasma oxide layer are etched using the amorphous carbon hard mask pattern as an etching mask to form the first vernier pattern 116.

Referring to FIG. 1B, a spacer material layer 118 and a second polysilicon 120 are sequentially formed on the semiconductor substrate 110 including the first vernier pattern 116.

1C and 1D, the second polysilicon 120 is etched back to expose the spacer material layer 118 formed on the first vernier pattern 116 to expose the first vernier pattern. The second poly pattern 120a is formed on the outer side of the cover.

The spacer material layer 118 exposed on the first vernier pattern 116 and the space between the first vernier pattern 116 and the second poly pattern 120a using the second poly silicon pattern 120a as an etching mask. The material layer 118 is etched to form the spacer material pattern 118a. Here, the second poly pattern 120a and the spacer material pattern 118a form the second vernier pattern 122, so that a rectangular band shape is formed in an area between the first vernier pattern 116 and the second vernier pattern 122. Trenches 124 are formed to form the parent vernier.

However, in the case of forming an overlay vernier using a typical SPT, when forming a vernier or alignment mark larger than a cell pattern formed in a cell region at one time, it is formed on the spacer of the vernier or alignment mark due to the characteristics of the SPT process. The trench size formed by this is too small to measure with the capabilities of the overlay measurement equipment currently in use.

An object of the present invention is to provide an overlay vernier forming method capable of aligning the overlay measurement or exposure process in the overlay equipment or exposure equipment in the SPT process.

The overlay vernier forming method according to the present invention

Forming a first mask material layer over the semiconductor substrate;

Etching the first mask material layer using a vernier mask to form a first vernier pattern defining a plurality of holes in a region where vernier is formed;

Forming a spacer material layer on the first vernier pattern including the hole;

Forming a second mask material layer over the spacer material layer;

Etching back the second mask material layer to form a second mask pattern in the hole; And

And etching the spacer material layer using the second mask pattern as an etch mask to form a spacer material pattern to form a second vernier pattern formed of the second mask pattern and the spacer material pattern.

The method may further include forming a plasma oxide layer on the semiconductor substrate.

The first mask material layer and the second mask material layer comprise polysilicon,

The forming of the second mask pattern may further include exposing the first vernier pattern by partially etching the spacer material layer formed on the first vernier pattern.

According to the present invention, the overlay vernier or the alignment key is implemented as a plurality of holes in the SPT process, so that the overlay measurement or the exposure process can be aligned even in the overlay equipment or the exposure equipment using a light source having a wavelength of about 600 nm.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the spirit of the present invention is thoroughly and completely disclosed, and the spirit of the present invention to those skilled in the art will be fully delivered. Also, like reference numerals denote like elements throughout the specification.

2A through 2D are cross-sectional views illustrating a method of forming an overlay vernier in an SPT process according to the present invention. Here, (i) is a top view, and (ii) shows sectional drawing cut along BB 'of (i).

Referring to FIG. 2A, a plasma enhanced oxide (PEOXIDE) and a first polysilicon layer (poly Si) are sequentially formed on the semiconductor substrate 210.

Subsequently, the first polysilicon layer and the plasma oxide film are etched using the vernier mask to form the first poly pattern 214 and the plasma oxide film pattern 212, and the first poly pattern 214 and the plasma oxide film pattern 212. A first vernier pattern 216 defining a plurality of holes 215 is formed in the region where the vernier is formed. In this case, in the method of forming the first vernier pattern 216, a hard mask material layer is formed on the first poly pattern 214 to pattern the first poly silicon 214. In this case, in general, the hard mask material layer may be formed of amorphous carbon, and a silicon nitride oxide layer (SiON) may be deposited on the amorphous carbon as needed. In addition, a photoresist is applied on the hard mask material layer, a photoresist pattern is formed through an exposure process using a vernier mask, and the hard mask material layer is etched using the photoresist pattern as an etching mask to form a hard mask pattern. Form. At this time, BARC (Bottom Anti-Reflective Coating) may be applied under the photosensitive film, if necessary. Subsequently, the first polysilicon layer and the plasma oxide layer are etched using the amorphous carbon hard mask pattern as an etching mask to form the first vernier pattern 216.

Referring to FIG. 2B, the spacer material layer 218 and the second polysilicon layer 220 are sequentially formed on the first vernier pattern 216 including the hole 215.

Referring to FIGS. 2C and 2D, the second polysilicon layer 220 is etched back to expose the spacer material layer 218 formed on the first vernier pattern 216. 115, a second poly pattern 220a is formed inside.

The exposed spacer material layer 218 is partially etched to expose the first vernier pattern 216.

The spacer material layer 218 is etched using the second poly pattern 220a as an etching mask to form the spacer material pattern 218a.

Accordingly, a second vernier pattern 222 implemented by the second poly pattern 220a and the spacer material pattern 218a is formed in the hole 215 defined by the first vernier pattern 216.

Here, holes formed of trenches formed between the first vernier pattern 216 and the second vernier pattern 222 form one mother vernier. In this case, the overlay apparatus may recognize a plurality of hole arrays as one parent vernier, and then form a ruler vernier on the parent vernier to measure overlay accuracy.

As described above, in the SPT process, the overlay vernier or alignment key can be implemented as a plurality of holes, so that the overlay measurement or the exposure process can be aligned in the overlay equipment or the exposure equipment using a light source having a wavelength of about 600 nm. Discuss the technique.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

1A to 1D are cross-sectional views illustrating a method of forming an overlay vernier using a general SPT.

2A to 2D are cross-sectional views illustrating a method of forming an overlay vernier according to the present invention.

<Description of the symbols for the main parts of the drawings>

210: semiconductor substrate 212: plasma oxide film pattern

214: first poly pattern 215: hole

216: first vernier pattern 218: spacer material layer

218a: spacer material pattern 220: second polysilicon layer

220a: second poly pattern 222: second vernier pattern

Claims (4)

Forming a first mask material layer over the semiconductor substrate; Etching the first mask material layer using a vernier mask to form a first vernier pattern defining a plurality of holes in a region where vernier is formed; Forming a spacer material layer on the first vernier pattern including the hole; Forming a second mask material layer over the spacer material layer; Etching back the second mask material layer to form a second mask pattern inside the hole; Forming a spacer pattern by etching the spacer material layer by using the second mask pattern as an etch mask to form a second vernier pattern formed of the second mask pattern and the spacer pattern. How to form an overlay vernier. The method of claim 1, And forming a plasma enhanced oxide on the semiconductor substrate. The method of claim 1, And the first mask material layer and the second mask material layer comprise polysilicon. The method of claim 1, The forming of the second mask pattern may further include exposing the first vernier pattern by partially etching the spacer material layer formed on the first vernier pattern.

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