KR20090067794A - Semiconductor memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device that generates a column selection signal for a column operation. A clock synchronous column pulse generation circuit for generating a column pulse signal having a pulse width corresponding to a cycle of a clock signal, and a column selection signal corresponding to the pulse width of the column pulse signal by combining the column pulse signal and an address; And a column select signal generator.

Description

Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE}

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device for generating a column select signal for a column operation.

In general, a semiconductor memory device performs a column operation to enable a column select signal when a CAS command is applied.

In particular, in DDR2, 'tCCD (CAS to CAS command delay)' is two cycles (2tCK), which means that when a CAS command is applied, data should be read or written within two cycles and executed up to precharge for the next operation. . Therefore, the column select signal should be enabled and disabled within two periods after the CAS command is applied.

In addition, since a minimum tCK must be taken into account when generating the column select signal in order to realize high-speed operation, the conventional semiconductor memory device determines the pulse width of the column select signal through a delay line considering the minimum period. do.

That is, as shown in FIG. 1, the conventional semiconductor memory device includes a column pulse generator 10 and a column select signal generator 12, and the column pulse generator 10 includes the read command signals PRDP and write. The command signal PWTP and the burst signal PCASTP are input to generate a column pulse signal YSP having a predetermined pulse width when at least one of these PRDPs, PWTPs, and PCASTPs is enabled, and the column select signal generator 12 generates column pulses. The signal YSP and the address ADDR are combined to output the column selection signal YI corresponding to the pulse width of the column pulse signal YSP.

Here, the column pulse generator 10 includes a delay line considering a minimum period for high frequency operation, and receives and delays at least one of a read command signal PRDP, a write command signal PWTP, and a burst signal PCASTP. And the delayed signal are combined to generate a column pulse signal YSP.

That is, the conventional semiconductor memory device generates the column pulse signal YSP having a constant pulse width through the delay line, and the pulse width of the column pulse signal YSP is determined according to a high frequency clock for high speed operation.

However, the smaller the pulse width of the column selection signal YI generated by the column pulse signal YSP, the more difficult it is to read or write data. Therefore, the pulse width of the column selection signal YI does not need to be small in the case of high frequency operation. . Nevertheless, the conventional semiconductor memory device is set to generate the column selection signal YI having a constant pulse width in response to the high frequency operation, and thus there is a problem that the pulse width of the column selection signal YI is unnecessarily small in the low frequency operation.

In addition, the delay line provided in the column select signal generator 10 may be generally composed of transistors, but since the transistors are sensitive to changes in PVT (Process, Voltage, Temperature), the pulse width of the column pulse signal YSP is also PVT. It can vary greatly in response to changes. Therefore, the pulse width of the column selection signal YI generated in the column pulse signal YSP may cause insufficient time for precharging or insufficient time for reading or writing data.

In order to solve this problem, the delay line provided in the column select signal generator 10 may be composed of resistors and capacitors. However, the column select signal generator 10 may have a layout that is insensitive to PVT change. There is a problem that can occupy a large area.

The present invention provides a semiconductor memory device capable of sufficiently securing data reads or write margins regardless of a clock frequency.

The present invention provides a semiconductor memory device which occupies a small layout area while generating a column select signal that is hardly affected by PVT changes.

In accordance with an aspect of the present invention, a semiconductor memory device includes: a command decoder configured to decode an external command and output a command signal; A clock synchronous column pulse generation circuit configured to receive the command signal and a clock signal and generate a column pulse signal having a pulse width corresponding to a period of the clock signal while being synchronized with the command signal; And a column select signal generator for generating a column select signal corresponding to the pulse width of the column pulse signal by combining the column pulse signal and the address.

The clock signal may be an external clock or an internal clock buffered with an external clock.

The clock synchronous column pulse generation circuit may generate the command signal having a pulse width corresponding to one period of the clock signal.

According to another aspect of the present invention, a semiconductor memory device receives a command signal related to a clock signal and a column selection, and adjusts a pulse width of each command signal in response to a cycle of the clock signal to output internal command signals. Pulse width control section; A column pulse generator configured to combine the internal command signals to generate a column pulse signal corresponding to a pulse width of the internal command signals; And a column select signal generator for generating a column select signal corresponding to the pulse width of the column pulse signal by combining the column pulse signal and the address.

The command signals may include any one of a signal pair consisting of a read command signal and a burst command signal, and a signal pair consisting of a write command signal and the burst command signal.

The clock signal may be an external clock or an internal clock buffered with an external clock.

The pulse width adjusting unit may adjust the pulse widths of the command signals to correspond to one period of the clock signal.

In the above configuration, the pulse width control unit, the transfer unit for transmitting the command signals when the clock signal is a predetermined state; And a latch unit for latching command signals transmitted from the transfer unit and outputting the internal command signals, respectively.

Here, the transfer unit transfers the command signals when the clock signal is in a high level state, and the latch unit transfers the command signals until the external clock signal rises to a high level again after command signals are transferred from the transfer unit. It is preferable to latch the command signals transmitted from and output the internal command signals.

The column pulse generator may logically combine the internal command signals to generate the column pulse signal that is enabled when at least one of the internal command signals is enabled.

The present invention has a configuration in which the pulse width of the column selection signal is automatically adjusted to correspond to the clock frequency by generating a column selection signal corresponding to a cycle of an internal clock buffered by an external clock or an external clock, even if the clock frequency changes. This has the effect of ensuring sufficient data lead or write margin.

In addition, since the present invention generates a column select signal that is synchronized to an external clock or an internal clock buffered external clock, the pulse width of the column select signal is hardly affected by the PVT change, so that normal data read, write, or precharge operation is performed. There is an effect that can be performed.

In addition, the present invention has a configuration that generates a column select signal in synchronization with an external clock or an internal clock buffered by the external clock using transistors, the effect that the column selection signal is insensitive to PVT changes and the layout area can be reduced There is.

The present invention provides a semiconductor memory device which generates a column select signal having a pulse width corresponding to a predetermined period of the clock signal while being synchronized with a clock signal.

Specifically, referring to FIG. 2, the semiconductor memory device according to the present invention includes a command decoder 20, a clock synchronous column pulse generation circuit 22, and a column select signal generator 26.

The command decoder 20 decodes the external commands / CS, / RAS, / CAS and / WE and outputs them as a command signal. The command signal is a read command signal PRDP, a write command signal PWTP, a read command signal PRDP and a burst command. It may be a pair of signals composed of the signal PCASP, or a pair of signals composed of the write command signal PWTP and the burst command signal PCASP. Here, whether the burst command signal PCASP is generated according to the burst length is determined. For example, the burst command signal PCASP may not be generated when the burst length 4 is generated, but may be generated when the burst length 8 is generated.

The clock synchronous column pulse generation circuit 22 receives the command signal and the clock signal CLK and generates a column pulse signal YSP having a pulse width corresponding to the period of the clock signal CLK while being synchronized with the command signal. Here, the clock synchronous column pulse generation circuit 22 preferably generates the command signal having a pulse width corresponding to one cycle 1tCK of the clock signal CLK.

The column select signal generator 26 combines the column pulse signal YSP and the address ADDR to generate a column select signal YI corresponding to the pulse width of the column pulse signal YSP.

In the semiconductor memory device according to the present invention having such a configuration, the clock synchronous column select signal generation circuit 22 receives the clock signal CLK, the read command signal PRDP, the write command signal PWTP, and / or the burst command signal PCASP, A pulse width adjusting unit 23 for adjusting each pulse width corresponding to the period of the clock signal CLK and outputting the internal read command signal IRDP, the internal write command signal IWTP, and / or the internal burst command signal ICASP; The column pulse generator 24 generating a column pulse signal YSP corresponding to the pulse width of the internal command signals IRDP, IWTP, ICASP in response to the command signal IRDP, the internal write command signal IWTP, and / or the internal burst command signal ICASP. It may be configured to include.

Here, as shown in FIG. 3, the pulse width adjusting unit 23 includes a transfer unit 32 and a latch unit 34, and a buffer buffering the clock signal CLK when the clock signal CLK is an external clock. It may further include a portion (30).

Looking at the configuration in detail, the buffer unit 30 may include an inverter INV1 for inverting the clock signal CLK and an inverter INV2 for inverting the output of the inverter INV1.

Then, the transfer unit 32 reads in response to the inverter INV3 for inverting the output of the clock signal CLK or the buffer unit 30, the output of the clock signal CLK or the buffer unit 30, and the output of the inverter INV3. Three-phase inverter TIV1 that inverts and transmits the signal PRDP, and three-phase inverter TIV2 that inverts and transmits the write command signal PWTP in response to the output of the clock signal CLK or the buffer unit 30 and the output of the inverter INV3. And a three-phase inverter (TIV3) inverting and transferring the burst command signal PCASP in response to the output of the clock signal CLK or the buffer unit 30 and the output of the inverter INV3.

The transfer section 32 having such a configuration receives the read command signal PRDP, the write command signal PWTP, and / or the burst command signal PCASP, so that the read command when the clock signal CLK or the output of the buffer unit 30 is in the high level state. The read command signal PRDP, the write command signal PWTP, or the signal PRDP, the write command signal PWTP, or / and the burst command signal PCASP are inverted and transmitted, and the output of the clock signal CLK or the buffer unit 30 is at a low level. / And do not carry the burst command signal PCASP.

The latch unit 34 includes two inverters INV4 and INV5 having a latch structure for latching the output of the three-phase inverter TIV1, two inverters INV6 and INV7 having a latch structure for latching the output of the three-phase inverter TIV2, Two inverters INV8 and INV9 having a latch structure for latching the output of the three-phase inverter TIV3 may be configured.

The latch unit 34 having such a configuration latches the signals transmitted from the transfer unit 32, respectively, and has an internal read command signal having a pulse width corresponding to the clock signal CLK or the period tCK of the output of the buffer unit 30. Output to IRDP, internal write command signal IWTP, and / or internal burst command signal ICASP. At this time, the latch unit 34 latches the signals transmitted from the transfer unit 32 for one period (1 tCK) until the clock signal CLK or the output of the buffer unit 30 rises again to a high level. This is preferred.

On the other hand, as shown in FIG. 4, the column pulse generator 24 includes an inverter INV10 for inverting the internal read command signal IRDP, an inverter INV11 for inverting the internal write command signal IWTP, and an internal burst command signal ICASP. Inverter INV12 for inverting, NAND gate NAND for NAND combining the outputs of inverters INV10 to INV12, inverter INV13 for inverting the output of NAND gate, and inverting the output of inverter INV13 It may be configured to include an inverter (INV14) for outputting the column pulse signal YSP.

The column pulse generator 24 having the above configuration enables and outputs the column pulse signal YSP when at least one of the internal read command signal IRDP, the internal write command signal IWTP, and the internal burst command signal ICASP is enabled. The pulse width of the output column pulse signal YSP is the same as the pulse width of the internal read command signal IRDP, the internal write command signal IWTP, and the internal burst command signal ICASP.

Referring to the configuration of Figures 2 to 4, the operation of the semiconductor memory device according to the present invention will be described in detail as follows.

First, when command signals / CS, / RAS, / CAS and / WE are input from the outside, the command decoder 20 decodes these / CS, / RAS, / CAS and / WE to read the command signal PRDP and the write command. To generate a signal PWTP, and / or a burst command signal PCASP. For example, when the burst length is 4 and the read operation, the read command signal PRDP is generated. When the bus length is 8 and the read operation, the read command signal PRDP and the burst command signal PCASP are generated. For reference, the read command signal PRDP, the write command signal PWTP, and the burst command signal PCASP are long pulse signals that are not synchronized with the clock signal CLK.

Assuming that the read command signal PRDP is generated in the command decoder 20, the read command signal PRDP is input to the pulse width adjusting unit 23, and the pulse width adjusting unit 23 is connected to the clock signal CLK or the buffer unit 30. Only when the output is in the high level state, the read command signal PRDP is transferred to the latch section 34 to latch. Through this process, the internal read command signal IRDP corresponding to the clock signal CLK or the period tCK of the output of the buffer unit 30 is generated, and the internal read command signal IRDP is generated by the pulse width adjusting unit 23. It is preferable to have a pulse width corresponding to one cycle 1tCK of the output of the CLK or the buffer unit 30.

The internal read command signal IRDP is input to the column pulse generator 24 and output as the column pulse signal YSP. At this time, the pulse width of the internal read command signal IRDP is maintained as it is and output as the column pulse signal YSP. That is, the pulse width of the column pulse signal YSP is maintained at one cycle 1tCK of the clock signal CLK or the output of the buffer unit 30.

The column pulse signal YSP generated by the column pulse generator 24 is combined with the address ADDR through the column select signal generator 26 and output as the column select signal YI corresponding to the pulse width of the column pulse signal YSP.

The column selection signal YI generated by the column pulse generator 24 connects the bit line pair and the input / output line pair of the corresponding memory cell to control the data carried in the bit line pair to be transmitted to the input / output line pair.

As described above, the semiconductor memory device according to the present invention has a configuration of generating a column selection signal corresponding to a predetermined period of an external clock or an internal clock buffered by an external clock.

Accordingly, since the pulse width of the column selection signal is also changed in response to the clock frequency variation, the period margin of the column selection signal is sufficiently secured during low-speed operation, that is, when the external clock is low, so that data read or write can be sufficiently performed. There is.

In addition, since the semiconductor memory device according to the present invention generates a column select signal synchronized with an external clock or an internal clock buffered, the pulse width of the column select signal is insensitive to PVT variation. This is because the external clock or the internal clock buffered by the external clock is almost always affected by the PVT change and is constantly input.

For example, when DDR2 generates a column select signal corresponding to one cycle (1tCK) of an external clock or an internal clock buffered according to the present invention, the pulse width of this column select signal affects the PVT change. Since one cycle is maintained almost without receiving, there is an effect that a period margin 1tCK for data read or write and a period margin 1tCK for precharge can be sufficiently secured.

In addition, since the semiconductor memory device according to the present invention generates a column selection signal synchronized with an external clock or an internal clock buffered by using transistors, it is necessary to use a resistor and a capacitor to be affected by the minimum PVT change as in the prior art. There is no. Therefore, the present invention has the effect of reducing the layout area waste due to the use of resistors and capacitors.

While the invention has been shown and described with respect to particular embodiments, it will be readily apparent to those skilled in the art that the invention is not limited thereto but may be variously modified and modified. For example, in the configuration of FIG. 2, the position of the pulse width adjusting unit 23 and the column pulse generating unit 24 is changed so that the command signals PRDP, PWTP, and PCASP output from the command decoder 20 are the column pulse generating unit 24. Column PR signal YSP having a pulse width corresponding to the period of the clock signal CLK, which is inputted first to the first and outputted as a combined signal of these PRDP, PWTP, and PCASP. The configuration output to may be disclosed.

1 is a block diagram showing a circuit involved in generating a column select signal of a conventional semiconductor memory device.

2 is a block diagram showing a circuit involved in generating a column select signal of a semiconductor memory device according to the present invention;

3 is a circuit diagram showing a detailed configuration of the pulse width adjusting section 23 of FIG.

4 is a circuit diagram showing a detailed configuration of the column pulse generator 24 of FIG.

Claims (13)

A command decoder for decoding an external command and outputting the command signal as a command signal; A clock synchronous column pulse generation circuit configured to receive the command signal and a clock signal and generate a column pulse signal having a pulse width corresponding to a period of the clock signal while being synchronized with the command signal; And And a column select signal generator configured to combine the column pulse signal and the address to generate a column select signal corresponding to the pulse width of the column pulse signal. The method of claim 1, And the clock signal is an external clock. The method of claim 1, And the clock signal is an internal clock in which an external clock is buffered. The method of claim 1, And the clock synchronous column pulse generation circuit generates the command signal having a pulse width corresponding to one period of the clock signal. A pulse width adjusting unit which receives a command signal related to a clock signal and a column selection and adjusts a pulse width of each command signal to correspond to a cycle of the clock signal and outputs the internal command signals; A column pulse generator configured to combine the internal command signals to generate a column pulse signal corresponding to a pulse width of the internal command signals; And And a column select signal generator configured to combine the column pulse signal and the address to generate a column select signal corresponding to the pulse width of the column pulse signal. The method of claim 5, wherein And the command signals include one of a signal pair consisting of a read command signal and a burst command signal, and a signal pair consisting of a write command signal and the burst command signal. The method of claim 5, wherein And the clock signal is an external clock. The method of claim 5, wherein And the clock signal is an internal clock in which an external clock is buffered. The method of claim 5, wherein The pulse width adjusting unit controls the pulse width of the command signals to correspond to one period of the clock signal. The method of claim 5, wherein The pulse width adjusting unit, A transfer unit transferring the command signals when the clock signal is in a predetermined state; And And a latch unit for latching the command signals transmitted from the transfer unit to output the internal command signals. The method of claim 10, The transfer unit transfers the command signals when the clock signal is in a high level state. The method of claim 11, And the latch unit latches the command signals transmitted from the transfer unit and outputs the internal command signals until the external clock signal rises to a high level again after the command signals are transferred from the transfer unit. The method of claim 5, wherein And the column pulse generator logically combine the internal command signals to generate the column pulse signal that is enabled when at least one of the internal command signals is enabled.

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