KR20090049373A - Operation method of nonvolatile memory device - Google Patents

Abstract

The present invention relates to a method of operating a nonvolatile memory device, comprising: dividing word lines of a memory cell array into two or more word line groups; And reading data of a selected memory cell for each word line group by applying a bit line precharge voltage set differently for each word line group.

Read emotion, bit line precharge, sensing

Description

Method of operation a non volatile memory device

The present invention relates to a method of operating a nonvolatile memory device, and more particularly, to a method of operating a nonvolatile memory device to read more accurate data by adjusting a data read evaluation time according to a word line.

One type of nonvolatile memory device, a NAND flash memory device, includes a memory cell array, a row decoder, and a page buffer. The memory cell array includes a plurality of word lines and columns defined along rows and a plurality of bit lines extending along columns and a plurality of cell strings corresponding to the bit lines, respectively.

One side of the memory cell array includes a row decoder connected to string selection lines, word lines, and a common source line, and a page buffer connected to a plurality of bit lines is located on the other side.

Recently, in order to further improve the density of such flash memories, studies on multiple bit cells capable of storing a plurality of data in one memory cell have been actively conducted. This type of memory cell is referred to as a multi level cell (hereinafter referred to as MLC). In contrast, a single bit memory cell is referred to as a single level cell (hereinafter referred to as SLC).

Flash memory cells of a flash memory device include a current path formed between a source drain on a semiconductor substrate, and a floating gate and a control gate formed between an insulating film on the semiconductor substrate. In general, a program of a flash memory cell generally grounds a source / drain region of a memory cell and a semiconductor substrate, that is, a bulk region, and applies a positive high voltage to the control gate, thereby fowling node tunneling between the floating gate and the substrate. By means of generating Nordheim tunneling (hereinafter FN tunneling). In F-N tunneling, electrons in the bulk region are accumulated in the floating gate by a high voltage electric field applied to the control gate, thereby increasing the threshold voltage of the memory cell.

In order to read the data stored in the flash memory device, an initialization is first performed, followed by precharging the bit line to precharge the sensing node of the page buffer (not shown) to a high level.

In order to turn on the bit line select transistor of the bit line select unit of the page buffer, a select signal having a V1 level is input. Therefore, the selected bit line becomes a potential obtained by subtracting the threshold voltage Vt from the voltage V1.

The precharge voltage applied to the sensing node is turned off, and a bit line selection signal having a V2 level is applied to the selected bit line selection transistor. At this time, if the potential of the bit line connected to the word line is smaller than V2-Vt, the bit line select transistor is turned off to maintain the high level. If the potential of the bit line is greater than V2-Vt, the bit line select transistor is turned on. When turned on, the potential is changed through charge sharing with the sensing node. A time for waiting for a potential change with a sensing node by applying a V2 potential to the bit line selection transistor is called a read evaluation time. In the current page buffer circuit, instead of the bit line selection transistor, a separate page buffer sensing transistor is configured between the sensing node and the bit line.

Accordingly, an aspect of the present invention is to provide a method of operating a nonvolatile memory device, which reads data of a nonvolatile memory device so that a read time may be different for each word line to enable more accurate data reading.

Method of operating a nonvolatile memory device according to a feature of the present invention,

A data read operation method of a nonvolatile memory device, comprising: dividing word lines of a memory cell array into two or more word line groups; And reading data of a selected memory cell for each word line group by applying a bit line precharge voltage set differently for each word line group.

The reading may include precharging each bit line for a different time set for each word line group; During the set read evaluation time, causing the voltage of the precharged bit line to change according to a program state of a selected memory cell; And sensing the voltage of the bit lines and reading data of the memory cell according to the result.

The precharge voltage is set to be gradually lower in the order of groups far from the common source line.

In the precharge operation, a precharge voltage is provided to the bit line through a switching element that is turned on during the precharge time.

Method of operating a nonvolatile memory device according to another aspect of the present invention,

A data read operation method of a nonvolatile memory device, comprising: dividing word lines of a memory cell array into two or more word line groups; And precharging the bit lines of the word line groups, and reading data of the selected memory cell by feeling data of the selected memory cell during a read emotion time set differently for each group.

The reading may include precharging bit lines of the word line group; Causing the voltage of the precharged bit line to change according to a program state of the selected memory cell during a read emotion time set for each word line group; And sensing the voltage of the bit lines and reading data of the memory cell according to the result.

The read emotion time is set to be longer and longer in the order of groups far from the common source line.

A method of operating a nonvolatile memory device according to another aspect of the present invention,

In the data read operation method of a nonvolatile memory device,

Dividing word lines of the memory cell array into two or more word line groups; And reading data of a selected memory cell using a bit line precharge voltage set differently for each word line group and a read emotion time set differently for each group.

The reading may include: precharging the bit line precharge voltages set for each word line group; Causing the voltage of the precharged bit line to change according to a program state of the selected memory cell during a read emotion time set for each word line group; And sensing the voltage of the bit lines and reading data of the memory cell according to the result.

The precharge voltage is set to be gradually lower in the order of groups far from the common source line.

The read emotion time is set to be longer and longer in the order of groups far from the common source line.

A method of operating a nonvolatile memory device according to another aspect of the present invention,

A data read operation method of a nonvolatile memory device, comprising: dividing word lines of a memory cell array into two or more word line groups; And reading data of a selected memory cell for each word line group by applying a bit line precharge time set differently for each word line group.

As described above, the method of operating the nonvolatile memory device according to the present invention divides word lines into groups and applies different read evaluation times for each group, or applies precharge voltages to set data read conditions suitable for each word line characteristic. Provide accurate data reading.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

1A is a block diagram illustrating the structure of a flash memory device.

Referring to FIG. 1A, referring to FIG. 1A, a flash memory device 100 may include a memory cell array 110 in which a plurality of memory cells for data storage are formed of a bit line BL and a word line WL. and. The page buffer unit 120 is connected to a pair of bit lines of the memory cell array 110 and includes a plurality of page buffer circuits to program and read data.

Some of the word lines constituting the memory cell array 110 are divided into a first word line group and the remaining word lines into a second word line group to perform sensing. For example, if the memory cell array 110 includes the first to thirty-second word lines WL0 to WL31, the first to sixteenth word lines WL0 to WL15 may be divided into a first word line group. The sixteenth to thirty-second word lines WL16 to WL31 may be defined as a second word line group. The word line group may be divided into two or more.

In addition, the flash memory device 100 may include an X decoder 140 for selecting a word line of the memory cell array 110 according to an input address, and a Y decoder 130 for selecting the page buffer unit 120 according to an input address. ).

The page buffer circuits of the page buffer unit 120 read data by applying different sensing voltages to the first word line group and the second word line group of the memory cell array 110.

The voltage providing unit 150 and the memory cell array 110, the page buffer unit 120, the X decoder 140, and the Y decoder 130 provide a voltage for performing a program or data read operation. And a controller 160 for controlling the voltage providing unit 150.

The controller 160 stores information about the word line groups and information on sensing voltages provided by the page buffer circuits of the page buffer unit 120 for each group, in which an algorithm for operation control is stored. The storage unit 161 is included.

Meanwhile, the memory cell array 110 includes a plurality of memory cells that store data. Some of the plurality of memory cells are connected in series to form a cell string, and the cell strings are respectively connected to the plurality of bit lines. The page buffer unit 120 is connected to a pair of bit lines among the plurality of bit lines constituting the memory cell array 110 to perform program, verify, and read operations on the memory cells of the selected bit line. Contains multiple page buffers.

The cell string, bit line, and page buffer circuit are configured as follows.

FIG. 1B is a circuit diagram illustrating a portion of a cell string and a page buffer of FIG. 1A.

Referring to FIG. 1B, the cell string includes first to thirty-second memory cells C0 to C31 connected in series between the first and second NMOS transistors N1 and N2.

The first NMOS transistor N1 is controlled by a source select line as a source select transistor (SST). The second NMOS transistor N2 is a drain select transistor DST and is controlled by a drain select line DST.

The gates of the first to 31st memory cells C0 to C31 are connected to the first to 31st word lines WL0 to WL31. The first to fifteen word lines WL to WL15 are referred to as a first word line group, and the sixteenth to thirteenth word lines WL16 to WL31 are referred to as a second word line group.

The even bit line BLe is connected to the other side of the second NMOS transistor N2. The even bit line BLe is connected to the page buffer circuit 121 together with the odd bit line BLO. The page buffer circuit 121 includes a bit line selector 122, a sensing unit 123, and a latch unit 124.

The bit line selector 122 connects any one of the even bit line BLe and the odd bit line BLO to the sensing unit 123. The sensing unit 123 senses the voltage of the bit line connected by the bit line selection unit 122 to read data and is connected to the latch unit 124 through the sensing node SO. The latch unit 124 temporarily stores read data according to the voltage level of the sensing node SO whose state is changed according to the sensing result of the sensing unit 123, or temporarily stores data for storing in the memory cell.

The sensing unit 123 includes a third NMOS transistor N3. The third NMOS transistor N3 is connected to the bit line selector 122 and the sensing node SO. PBSENSE) is entered.

The control unit 160 of the flash memory device 100 as shown in FIG. 1A stores information about the first word line group and the second word line group in the storage unit 161 and provides the same to each word line group. Information about the sensing voltage level is stored.

In general, when the data of the flash memory device 100 is read, the bit line is first precharged. In order to precharge the bit line, the precharge means included in the latch unit 124 precharges the sensing node SO and applies the sensing voltage PBSENSE to the first voltage V1 to perform a third NMOS transistor ( By turning on N3), the voltage precharged to the sensing node SO is transferred to the bit line to precharge the bit line.

The third NMOS transistor N3 is turned off by applying the sensing voltage PBSENSE to 0 V during an evaluation time for reading, and then changes the voltage state of the bit line according to the program state of the memory cell.

In other words, the read voltage is applied to the word line selected for data reading, the pass voltage is applied to the word line, and the turn-on voltage of the transistor is input to the drain select line and the source select line. Turn on the transistor.

When the drain select transistor is turned on, it is connected to the precharged bit line, and the voltage of the bit line is discharged or maintained in the precharge state depending on whether the memory cell of the selected word line is programmed.

After the readout verification time, the sensing voltage PBSENSE is applied to the second voltage V2 to turn on the third NMOS transistor N3 to transfer the bit line voltage to the sensing node SO.

In this case, when the selected memory cell is not programmed (this may include a memory cell having a lower threshold voltage than the read voltage), the voltage of the bit line is commonly discharged through the source select transistor. In this case, the bit line is discharged to a voltage lower than the second voltage V2 which is the sensing voltage PBSENSE. Therefore, the third NMOS transistor N3 is not turned on by the sensing voltage PBSENSE applied to the second voltage V2.

However, when the memory cell is a program cell, the voltage precharged to the bit line is maintained as it is. Accordingly, the third NMOS transistor N3 is turned on by the sensing voltage PBSENSE applied to the second voltage V2, and the precharge voltage of the bit line is transferred to the sensing node SO.

As described above, in order for the page buffer circuit 121 to read data into the memory cell, the bit line is turned on through the third NMOS transistor N3 turned on by the sensing voltage PBSENSE applied to the first voltage V1. Precharge After the read verification time, the bit line voltage is changed, and the third NMOS transistor N3 is turned on or off by the sensing voltage PBSENSE applied to the second voltage V2 to latch the data of the memory cell. Stored in section 124.

The data read method uses a method of precharging the bit line to the drain select transistor and discharging the bit line voltage to the common source line of the source select transistor. However, even though the memory cells connected to each word line are programmed using the same program voltage, the threshold voltages of the memory cells are recognized differently. This is because each word line has a different distance from the common source line, so that the influence of the voltage precharged on the bit line is different.

Accordingly, in an exemplary embodiment of the present invention, the word line is divided into first and second word line groups, and a different level of sensing voltage is applied to the first word line group and the second word line group to compensate for this problem.

The first word line group provides a sensing voltage in the same manner as a general sensing voltage application method.

2A illustrates a sensing voltage level provided to a first word line group according to an embodiment of the present invention.

FIG. 2A illustrates a voltage level at which the sensing voltage PBSENSE of the sensing unit 123 is applied when sensing data of the first word line group of FIG. 1B. Applied during T1) to allow the bit line to precharge.

Then, the sensing voltage is applied to 0V so that the bit line voltage is changed according to the program degree during the second time T2, and the changed bit line voltage is sensed by applying the second voltage V2.

In addition, the sensing voltage may be applied to the second word line group far from the common source line in two ways.

2B illustrates a sensing voltage level provided to the second word line group according to the first embodiment of the present invention.

Referring to FIG. 2B, the sensing voltage PBSENSE provided to the second word line group according to the first embodiment of the present invention is a method of changing the voltage level precharged to the bit line by reducing the time for precharging the bit line. . Therefore, if the same bit line precharge time is given, the voltage level precharged to the bit line may be changed by changing the sensing voltage PBSENSE.

In the eleventh embodiment of the present invention, the first voltage V1 for bit line precharge is applied in a third time T3 shorter than the first time T1 which is a precharge time of the first word line group.

After the third time T3, the readout is verified by applying the sensing voltage PBSENSE to 0V for the second time T2. The second voltage V2 is provided to sense a change state of the bit line.

According to a method of providing a sensing voltage PBSENSE of a second word line group according to the first embodiment of the present invention, a voltage precharged to a bit line is adjusted by shortening the precharge time to a second word line group far from a common source line. Reduce Thus, even during the same read verify time, the bit line voltage can be sufficiently changed according to the data state of the memory cell.

Next, in applying the sensing voltage PBSENSE of the second word line group, a method of increasing the read emotion time may be used.

2C illustrates a sensing voltage level provided to the second word line group according to the second embodiment of the present invention.

Referring to FIG. 2C, the sensing voltage PBSENSE provided to the second word line group according to the second embodiment of the present invention is applied to the first word line of FIG. 2A by applying the first voltage V1 for a first time. Give the same precharge time as the group.

In addition, a read emotion time is given by applying a sensing voltage PBSENSE of 0V, and a read emotion time is given for a third time T3 longer than the second time T2 which is the read emotion time of the first word line group. After the read emotion time, the sensing voltage PBSENSE is applied to the first voltage V1.

Since the read emotion time is extended to the second time, the second word line group can change the bit line voltage sufficiently precharged.

According to an exemplary embodiment of the present invention, the precharge time or the read emotion time is adjusted to each word line group by dividing the first and second word line groups, but the word line group is divided into more detailed subdivisions, and the precharge time according to each group. Alternatively, by adjusting the read emotion time, it is possible to provide an environment for more accurate data reading.

In addition, information on the precharge time or the read emotion time of the bit line applied to each word line is stored in the storage unit 161 of the controller 160 and arbitrarily changed by the user outside the flash memory device. It is also possible to apply.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1A is a block diagram illustrating the structure of a flash memory device.

FIG. 1B is a circuit diagram illustrating a portion of a cell string and a page buffer of FIG. 1A.

2A illustrates a sensing voltage level provided to a first word line group according to an embodiment of the present invention.

2B illustrates a sensing voltage level provided to the second word line group according to the first embodiment of the present invention.

2C illustrates a sensing voltage level provided to the second word line group according to the second embodiment of the present invention.

* Brief description of the main parts of the drawings *

100 flash memory device 110 memory cell array

120: page buffer unit 130: Y decoder

140: X decoder 150: voltage provider

160: control unit

Claims (12)

In the data read operation method of a nonvolatile memory device, Dividing word lines of the memory cell array into two or more word line groups; And Reading data of a selected memory cell for each word line group by applying a bit line precharge voltage set differently for each word line group Method of operating a nonvolatile memory device comprising a. The method of claim 1, The reading step, Precharging each bit line for a different time set for each word line group; During the set read evaluation time, causing the voltage of the precharged bit line to change according to a program state of a selected memory cell; And Sensing the voltage of the bit lines and reading data of the memory cell according to the result Method of operating a nonvolatile memory device comprising a. The method of claim 1, And the precharge voltage is set to be lower in the group order far from the common source line. The method of claim 1, The precharge operation, And a precharge voltage is provided to the bit line through a switching device that is turned on during the precharge time. In the data read operation method of a nonvolatile memory device, Dividing word lines of the memory cell array into two or more word line groups; And Precharging the bit lines of the word line groups, and reading data of the selected memory cell by feeling data of the selected memory cell during a read emotion time set differently for each group. Method of operating a nonvolatile memory device comprising a. The method of claim 5, The reading step, Precharging the bit lines of the word line group; Causing the voltage of the precharged bit line to change according to a program state of the selected memory cell during a read emotion time set for each word line group; And Sensing the voltage of the bit lines and reading data of the memory cell according to the result Method of operating a nonvolatile memory device comprising a. The method of claim 5, wherein And the read emotion time is set longer and longer in a group order away from a common source line. In the data read operation method of a nonvolatile memory device, Dividing word lines of the memory cell array into two or more word line groups; And Reading data of a selected memory cell using a bit line precharge voltage set differently for each word line group and a read emotion time set differently for each group Method of operating a nonvolatile memory device comprising a. The method of claim 8, The reading step, Precharging the bit line precharge voltages set for each word line group; Causing the voltage of the precharged bit line to change according to a program state of the selected memory cell during a read emotion time set for each word line group; And Sensing the voltage of the bit lines and reading data of the memory cell according to the result Method of operating a nonvolatile memory device comprising a. The method of claim 8, And the precharge voltage is set to be lower in the group order far from the common source line. The method of claim 8, And the read emotion time is set longer and longer in a group order away from a common source line. In the data read operation method of a nonvolatile memory device, Dividing word lines of the memory cell array into two or more word line groups; And Reading data of a selected memory cell for each word line group by applying a bit line precharge time set differently for each word line group Method of operating a nonvolatile memory device comprising a.

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