KR20090044411A - Manufacturing method of charge trap element - Google Patents

Abstract

A method for manufacturing a charge trap element according to the present invention includes a high voltage gate in a high voltage region of a substrate including a cell region and a peripheral circuit region having a low voltage region where a low voltage MOS transistor is disposed and a high voltage region where a high voltage MOS transistor is disposed. Forming an insulating film, forming a tunneling layer on the substrate in the cell region and the low voltage region, on the high voltage gate insulating film in the high voltage region, and forming a charge trap layer, a shielding layer, and a control gate electrode film on the tunneling layer; Removing the control gate electrode film and the shielding layer in the peripheral circuit region, forming the gate electrode film on the control gate electrode film in the cell region and the charge trap layer in the peripheral circuit region, and performing gate patterning, Tunneling layer, charge trap layer, shielding layer, control gate electrode film and gate electrode film are sequentially stacked on the area Forming a unit cell; forming a low voltage gate stack in which a tunneling layer, a charge trap layer, and a gate electrode film are sequentially stacked in a low voltage region; and a high voltage gate insulating film, a tunneling layer, a charge trap layer, and a gate electrode in a high voltage region. Forming a high voltage gate stack in which the films are sequentially stacked.

Charge trap element (CTD), cell region, peripheral circuit region, substrate damage, high temperature oxidation

Description

Method of fabricating a charge trap device

The present invention relates to a method of manufacturing a nonvolatile memory device, and more particularly, to a method of manufacturing a charge trap device.

The floating gate structure employed in non-volatile memory (NVM) devices presents limitations due to integration levels that do not meet the high performance demanded in recent years. Accordingly, recently, interest in charge trapping devices (CTDs) having a charge trapping layer has been amplified. The charge trap element employs a charge trap layer in place of the existing floating gate. The charge trap layer is a layer for storing charges flowing in the channel region in the substrate and passing through the tunneling layer under certain conditions. Examples of the charge trap device include a SONOS (Silicon / Oxide / Nitride / Oxide / Silicon) structure or a MANOS (Metal / Al ₂ O ₃ / Nitride / Oxide / Silicon) structure depending on the type of the stacking material.

In the unit cell structure of the charge trap element, a tunneling layer is disposed on a substrate, and a charge trap layer is disposed thereon. A blocking layer is disposed on the charge trap layer. The control gate electrode is disposed on the shielding layer, and the word line is disposed thereon. As with other semiconductor memories such as DRAM (DRAM), the charge trap element also includes a cell region in which the unit cells are arranged, and a peripheral circuit region for controlling the unit cells in the cell region. As described above, a plurality of unit cells are disposed in the cell region, and metal oxide semiconductor (MOS) transistors are disposed in the peripheral circuit region. In particular, the MOS transistor in the peripheral circuit region can be classified into a high voltage MOS transistor and a low voltage MOS transistor. Since a relatively high voltage is applied to the high voltage MOS transistor, the thickness of the gate oxide film employed in the high voltage MOS transistor is also relatively thick.

In forming a charge trap device having a peripheral circuit region in which a high voltage MOS transistor and a low voltage MOS transistor are disposed, and a cell region in which unit cells are arranged, in the case of forming the unit cells first and then forming transistors in the peripheral circuit region, A problem arises that oxidation of transition metals occurs in a unit cell by a high temperature oxidation process which is inevitably involved in the formation of transistors in the peripheral circuit region, particularly in the formation of a gate oxide film. Therefore, the unit cells in the cell region cannot be formed first, and the MOS transistor in the peripheral circuit region is formed first. Specifically, a gate oxide film of a high voltage MOS transistor, a gate oxide film and a gate electrode film of a low voltage MOS transistor are deposited. Subsequently, the substrate surface of the cell region is exposed using a mask layer pattern exposing the cell region. The tunneling layer, the charge trap layer, the shielding layer, and the control gate electrode film are deposited on the exposed cell region substrate. However, in this case, the substrate may be damaged during the etching of the gate electrode film, for example, the polysilicon film, which is deposited to expose the substrate of the cell region, and in this case, dislocations may occur on the substrate to cause program disturb. It can act as a cause of program disturb.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method for manufacturing a charge trap device capable of improving the stability of a device by suppressing substrate damage causing a program disturb.

A method of manufacturing a charge trap device according to an embodiment of the present invention includes a high voltage of a substrate including a cell region and a peripheral circuit region having a low voltage region in which a low voltage MOS transistor is disposed and a high voltage region in which a high voltage MOS transistor is disposed. Forming a high voltage gate insulating film in the region, forming a tunneling layer on the substrate in the cell region and the low voltage region, and on the high voltage gate insulating film in the high voltage region, and a charge trap layer, a shielding layer, and a control gate electrode on the tunneling layer. Forming a film, removing the control gate electrode film and the shielding layer in the peripheral circuit region, forming a gate electrode film on the control gate electrode film in the cell region and the charge trap layer in the peripheral circuit region, and gate patterning Tunneling layer, charge trap layer, shielding layer, control gate electrode film and gate electrode film in the cell region Forming a unit cell stacked sequentially, forming a low voltage gate stack in which a tunneling layer, a charge trap layer, and a gate electrode film are sequentially stacked in a low voltage region, and a high voltage gate insulating film, a tunneling layer, and a charge trap layer in a high voltage region. And forming a gate stack for the high voltage in which the gate electrode films are sequentially stacked.

The high voltage gate insulating film and the tunneling layer may be formed of an oxide film.

The charge trap layer may be formed of a silicon nitride film.

The shielding layer may be formed of a high dielectric constant material film or a silicon oxide film.

The control gate electrode film may be formed of a metal film or a polysilicon film.

The gate electrode film may include a polysilicon film.

The method may further include forming a capping layer on the control gate electrode layer before removing the control gate electrode layer and the shielding layer of the peripheral circuit region. In this case, the capping film may be formed of a polysilicon film or a silicon nitride film.

After forming the gate electrode film, the method may further include forming a low resistance layer on the gate electrode film.

The gate patterning may be performed by etching until the charge trap layer is exposed in the peripheral circuit region and the metal film is exposed in the cell region, forming a mask layer pattern covering the peripheral circuit region, and a mask. And etching the control gate electrode film, the shielding layer, and the charge trap layer in the cell region exposed by the film pattern.

According to the present invention, a high voltage gate insulating film is formed in the peripheral circuit region, in particular, the high voltage region, before forming the unit cell in the cell region, so that subsequent high temperature oxidation process after the unit cell formation is not involved, and also gate patterning of the peripheral circuit region is performed. Since the gate stacked films of the unit cells in the cell region have been previously stacked, substrate damage caused by gate patterning of the peripheral circuit region is suppressed.

Referring to FIG. 1, a high voltage gate oxide film 112 is formed in a region (hereinafter, high voltage region) HVT in which a high voltage MOS transistor is to be formed in the peripheral circuit region PERI of the substrate 100. In the peripheral circuit region PERI of the substrate 100, in addition to the high voltage region, a region in which a low voltage MOS transistor is to be formed (hereinafter, referred to as a low voltage region) LVT. In addition to the peripheral circuit region PERI, the substrate 100 also includes a cell region CELL in which unit cells are formed. In order to form the high voltage gate oxide film 112, a mask layer pattern (not shown) covering the cell region CELL and the low voltage region LVT and exposing the high voltage region HVT is formed. Next, on the substrate of the high voltage region HVT exposed by the mask film pattern, a relatively thick high voltage gate oxide film 112 is formed using a conventional method, such as a thermal oxidation method or an oxide film deposition method. After the high voltage gate oxide film 112 is formed on the surface of the substrate 100 in the high voltage region HVT, the mask film pattern is removed.

Next, an element isolation film 102 for inter-element insulation is formed. The device isolation layer 102 may be formed as a trench device isolation layer, but is not limited thereto. In some cases, different types of device isolation layers may be formed in the cell region CELL, the low voltage region LVT, and the high voltage region HVT. It may be formed. Subsequently, a relatively thin oxide film 114 is formed as a tunneling layer on the substrate 100 in the cell region CELL and the low voltage region LVT and on the high voltage gate oxide film 112 in the high voltage region HVT. The oxide film 114 functions as a tunneling layer in the cell region CELL, functions as a low voltage gate oxide film in the low voltage region LVT, and together with the high voltage gate oxide film 112 in the high voltage region HVT. It functions as a gate oxide film for high voltage.

Referring to FIG. 2, a silicon nitride film 120 is formed on the oxide film 114 as a charge trap layer. A high-k material film 130 is formed on the silicon nitride film 120 as a shielding layer, and a metal film 140 is formed thereon as a control gate electrode film. The high dielectric constant material layer 130 may include at least one of an Al ₂ O ₃ film, an HfO _x film, and a ZrO _x film. In another example, a silicon oxide film may be used as the shielding layer. The metal film 140 may include at least one of a TiN film, a TaN film, and a WN film. In another example, a polysilicon film may be used instead of the metal film 140 as the control gate electrode film. Subsequently, a polysilicon film 150 is formed on the metal film 140 as a capping film for protecting the metal film 140. In another example, a silicon nitride film may be used instead of the polysilicon film, and in some cases, the formation of the polysilicon film 150 or the silicon nitride film may be omitted. Next, a mask layer pattern 160 is formed on the polysilicon layer 150. The mask layer pattern 160 covers the cell region CELL while exposing the peripheral circuit region PERI.

Referring to FIG. 3, etching of the exposed portions of the peripheral circuit region PERI is performed using the mask layer pattern 160 of FIG. 2 as an etching mask. This etching is performed using a dry etching method. This etching is performed on the polysilicon layer 150, the metal layer 140, and the high dielectric constant material layer 130 in the peripheral circuit region PERI, and the silicon nitride layer 120 in the peripheral circuit region PERI is exposed. Is performed until. In particular, at the boundary between the cell region CELL and the peripheral circuit region PERI, the inclination is 110 to 160 degrees. After the etching is completed, the mask layer pattern 160 of FIG. 2 and the polysilicon layer 150 of FIG. 2 are removed. Next, a polysilicon film 170 is formed on the entire surface, that is, on the metal film 140 in the cell region CELL and on the silicon nitride film 120 in the peripheral circuit region PERI. The polysilicon film 170 is used as a word line in a unit cell of the cell region CELL and as a gate electrode film in a high voltage MOS transistor and a low voltage MOS transistor in the peripheral circuit region PERI. Next, a low resistance layer 180 is formed on the polysilicon film 170. In one example, the low resistance layer 180 is formed of a tungsten silicide (WSi) film. In another example, the low resistance layer 180 is formed of a tungsten (W) / tungsten nitride (WN) film.

Referring to FIG. 4, gate patterning is performed in a cell region CELL and a peripheral circuit region PERI by performing etching using a mask layer pattern (not shown) as an etch mask for gate patterning. In an example, the cell region CELL is etched until the metal layer 140 is exposed until the gate patterning is completely performed in the peripheral circuit region PERI. In this case, since the silicon nitride film 120 serves as an etch barrier layer in the peripheral circuit region PERI, sufficient etching is performed on the low resistance layer 180 and the polysilicon film 170. Next, the peripheral circuit region PERI is covered with the mask layer pattern, and then the metal layer 140, the high dielectric constant material layer 130, and the silicon nitride layer 120 exposed in the cell region CELL are etched.

After such gate patterning, the cell region CELL has an oxide film 114 as a tunneling layer, a silicon nitride film 120 as a charge trap layer, a high dielectric constant material film 130 as a shielding layer, and a metal film as a control gate electrode film. 140, a gate stack 210 of a unit cell in which a polysilicon film 170 as a word line and a low resistance layer 18 are sequentially stacked is formed. In the low voltage region LVT of the peripheral circuit region PERI, an oxide film 114, a silicon nitride film 120, a polysilicon film 170, and a low resistance layer 180 are sequentially stacked. 220 is formed. In addition, the high voltage gate oxide film 112, the oxide film 114, the silicon nitride film 120, the polysilicon film 170, and the low resistance layer 180 are sequentially stacked in the high voltage region HVT of the peripheral circuit region PERI. The gate stack 230 of the high voltage MOS transistor is formed. Although not shown in the drawings, ion implantation is performed to form an impurity region such as a source / drain, and a normal contact and wiring process is performed.

1 to 4 are cross-sectional views illustrating a method of manufacturing a charge trap device according to the present invention.

Claims (10)

Forming a gate insulating film for a high voltage in a high voltage region of a substrate including a cell region, a peripheral circuit region having a low voltage region in which a low voltage MOS transistor is disposed and a high voltage region in which a high voltage MOS transistor is disposed; Forming a tunneling layer on the substrate in the cell region and the low voltage region and on the gate insulating film for the high voltage in the high voltage region; Forming a charge trap layer, a shielding layer, and a control gate electrode layer on the tunneling layer; Removing the control gate electrode film and the shielding layer of the peripheral circuit area; Forming a gate electrode film on the control gate electrode film of the cell region and the charge trap layer of the peripheral circuit region; And By performing gate patterning, a unit cell in which a tunneling layer, a charge trap layer, a shielding layer, a control gate electrode layer, and a gate electrode layer are sequentially stacked is formed in the cell region, and the tunneling layer, the charge trap layer, and the gate are formed in the low voltage region. Forming a low voltage gate stack in which electrode layers are sequentially stacked, and forming a high voltage gate stack in which high voltage gate insulating layers, tunneling layers, charge trap layers, and gate electrode layers are sequentially stacked in the high voltage region. Method for manufacturing a trap element. The method of claim 1, And the high voltage gate insulating film and the tunneling layer are formed of an oxide film. The method of claim 1, And the charge trap layer is formed of a silicon nitride film. The method of claim 1, And the shielding layer is formed of a high dielectric constant material film or a silicon oxide film. The method of claim 1, And the control gate electrode film is formed of a metal film or a polysilicon film. The method of claim 1, And the gate electrode film comprises a polysilicon film. The method of claim 1, And forming a capping film on the control gate electrode film before removing the control gate electrode film and the shielding layer of the peripheral circuit region. The method of claim 7, wherein The capping film is a method of manufacturing a charge trap device formed of a polysilicon film or silicon nitride film. The method of claim 1, And forming a low resistance layer on the gate electrode film after the gate electrode film is formed. The method of claim 1, wherein performing the gate patterning comprises: Etching until the charge trap layer is exposed in the peripheral circuit region and the metal film is exposed in the cell region; Forming a mask layer pattern covering the peripheral circuit region; And And etching the control gate electrode film, the shielding layer, and the charge trap layer in the cell region exposed by the mask layer pattern.

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