KR20090043750A - LCD Display - Google Patents

Abstract

The present invention relates to a liquid crystal display device which can prevent a deterioration in image quality while forming a storage capacitor, and includes a plurality of data lines; First and second gate lines positioned to intersect the plurality of data lines; A plurality of common voltage lines alternately positioned with the plurality of data lines; A pixel electrode formed for each pixel region defined by the data line, each common voltage line, each first gate line, and each second gate line; And a plurality of branch lines extending from the common voltage line toward each pixel electrode and overlapping the pixel electrode.

LCD, DLS, common voltage line, auxiliary capacitor, liquid crystal capacitor, branch line

Description

Liquid crystal display device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of preventing image deterioration while forming a storage capacitor.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which pixel regions are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged to cross each other, and a pixel region is positioned in an area defined by vertical crossings of the gate lines and the data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed in the liquid crystal panel.

Each of the pixel electrodes is connected to the data line via a source terminal and a drain terminal of a thin film transistor (TFT) which is a switching element. The thin film transistor is turned on by a scan pulse applied to a gate terminal via the gate line, so that the data signal of the data line is charged to the pixel voltage.

Hereinafter, a conventional liquid crystal display device will be described with reference to the accompanying drawings.

1 is a view showing several pixel cells included in a conventional liquid crystal display.

A conventional liquid crystal display device, as shown in FIG. 1, crosses a plurality of gate lines GLn-1, GLn, GLn + 1 and the gate lines GLn-1, GLn, GLn + 1. A plurality of data lines DL, a pixel electrode PE formed in each pixel region defined by each of the gate lines GL and each of the data lines DL, and each of the gate lines GL. ) And a thin film transistor (TFT) formed near the intersection of each data line (DL).

In each pixel region, a storage capacitor is formed to stably maintain image data for one frame period. The storage capacitor includes a pixel electrode PE and a gate line GLn-1, GLn, and GLn + 1 overlapping each other. Formed in part. Specifically, the n-th gate line for driving the pixel electrode PE of the pixel region located in the n-th pixel row HLn and the pixel electrode PE positioned in the n-th pixel row HLn-1. At the portion where GLn-1) overlaps, a storage capacitor is formed.

Therefore, in order to form such a storage capacitor, the pixel electrode PE extends toward the front gate line side so as to overlap the front gate line. The pixel electrode PE of the row HLn-1 is located more closely. Accordingly, signal interference due to a coupling phenomenon occurs between two adjacent pixel electrodes PE, resulting in a problem of deterioration in image quality.

The present invention has been made to solve the above problems, and alternately positioned data lines and common voltage lines, and forming a pixel electrode between each data line and each common voltage line, wherein the common voltage It is an object of the present invention to provide a liquid crystal display device capable of preventing deterioration of image quality by extending branch lines branched from a line to the pixel electrode side so as to overlap the pixel electrode to form a storage capacitor.

A liquid crystal display according to the present invention for achieving the above object, a plurality of data lines; First and second gate lines positioned to intersect the plurality of data lines; A plurality of common voltage lines alternately positioned with the plurality of data lines; And a pixel electrode formed for each pixel region defined by the data line, the common voltage line, the first gate line, and the second gate line. And a plurality of branch lines extending from the common voltage line toward each pixel electrode and overlapping the pixel electrode.

The liquid crystal display according to the present invention as described above has the following effects.

The liquid crystal display according to the present invention includes a plurality of alternating data lines, a plurality of common voltage lines, and pixel electrodes formed between the data lines and each common voltage line. In this case, in order to form a storage capacitor, branch lines branch from the common voltage line to overlap the pixel electrode. Therefore, in the present invention, since the storage capacitor can be formed without making the distance between adjacent pixel electrodes close, it is possible to prevent signal interference due to the coupling phenomenon between the adjacent pixel electrodes. In conclusion, according to the present invention, it is possible to prevent deterioration of image quality.

FIG. 2 is a view showing a liquid crystal display device according to an exemplary embodiment of the present invention. Specifically, FIG. 2 shows a configuration of a lower substrate of the liquid crystal display device.

In the liquid crystal display according to the exemplary embodiment of the present invention, as shown in FIG. 2, a plurality of data lines DL arranged in one direction and a plurality of data lines DL arranged alternately with the data lines DL are arranged. And a plurality of first and second gate lines GL1 and GL2 arranged to cross common voltage lines CL and the plurality of data lines DL and the plurality of common voltage lines CL. .

Although not shown, the liquid crystal display according to the exemplary embodiment of the present invention further includes an upper substrate corresponding to the lower substrate. A color filter layer, a common electrode, and a black matrix layer are formed on the upper substrate.

The color filter layer is formed on each pixel area PED of the upper substrate, the black matrix layer is formed on the entire surface of the upper substrate except for the pixel area PED, and the common electrode is the pixel area PED. And a front surface of the upper substrate including the black matrix layer. The liquid crystal layer is formed between the upper substrate and the lower substrate configured as described above.

The data lines DL and the common voltage line CL are arranged in parallel with each other, and each data line DL is positioned between each common voltage line CL. Although not shown in the drawings, the common voltage lines CL may be positioned between the data lines DL.

2 illustrates an arbitrary two pixel rows, one pixel row including a plurality of data lines DL, a plurality of common voltage lines CL, a plurality of pixel electrodes PE, A first gate line GL1 for driving the first thin film transistors TFT1 and a second gate line GL2 for driving the second thin film transistors TFT2 are included.

Here, all the pixel rows HL1, HL2,... HLn share the data lines DL and the common voltage line CL.

The pixel rows HL1, HL2, ... HLn will be described in more detail as follows.

On the other hand, since the structures of all the pixel rows HL1, HL2, ..., HLn are the same, the first pixel row HL1 will be representatively described.

Each of the first thin film transistors TFT1 is formed near the intersection of the first gate line GL1 and each data line DL. The first thin film transistor TFT1 is turned on according to the gate signal from the first gate line GL1 to supply the data signal from the data line DL to the pixel electrode PE.

Each of the second thin film transistors TFT2 is formed near the intersection of the second gate line GL2 and each data line DL. The second thin film transistor TFT2 is turned on according to the gate signal from the second gate line GL2 to supply the data signal from the data line DL to the pixel electrode PE.

In this case, since the gate signal is sequentially supplied to the first gate line GL1 and the second gate line GL2, the first gate line GL1 is driven first, and then the second gate line GL2 is driven.

Therefore, first thin film transistors TFT1 connected to the first gate line GL1 are first turned on, and second thin film transistors TFT2 connected to the second gate line GL2 are turned on.

The first thin film transistor TFT1 and the second thin film transistor TFT2 are commonly connected to one data line DL, and data signals are sequentially supplied to the data line DL.

That is, when the first gate signal is supplied to the first gate line GL1, a first data signal is supplied to the data line DL, and a second gate signal is supplied to the second gate line GL2. At the point of time, a second data signal is supplied to the data line DL.

For example, a pixel cell provided on the leftmost of the pixel cells included in the first pixel row HL1 is defined as a first pixel cell, and a pixel cell immediately adjacent to the first pixel cell is defined as a second pixel cell. When the pixel cell is defined, the first data signal of the data line DL is supplied to the pixel electrode PE of the first pixel cell through the first thin film transistor TFT1 when the first gate signal is turned on. When the second gate signal is turned on, the second data signal of the data line DL is supplied to the pixel electrode PE of the second pixel cell through the second thin film transistor TFT2.

Here, the pixel cells provided in the first pixel row HL1 will be described in more detail as follows.

First, with this structure, one pixel region PED in the present invention is connected to the common voltage line CL, the data line DL, the first gate line GL1, and the second gate line GL2. It is defined as the area surrounded by. Pixel cells are formed in each pixel area PED, each pixel cell including a thin film transistor TFT1 or TFT2, a pixel electrode PE, a common electrode, a liquid crystal capacitor, and a storage capacitor capacitor SC1 or SC2. The even-numbered pixel cells of the pixel cells include the first thin film transistor TFT1 and the first storage capacitor capacitor SC1 connected to the first gate line GL1, and the odd pixel cells include the second gate. A second thin film transistor TFT2 and a second auxiliary capacitance capacitor SC2 connected to the line GL2 are included.

The liquid crystal capacitor is a capacitor having a first electrode made of the pixel electrode PE, a second electrode made of the common electrode, and a liquid crystal layer formed between the pixel electrode PE and the common electrode.

The first and second storage capacitors SC1 and SC2 may include a first electrode made of the pixel electrode PE, a second electrode made of the common voltage line CL, and a common voltage with the pixel electrode PE. It is a capacitor having an insulating film formed between the lines CL.

In detail, the common voltage line CL includes a plurality of branch lines BL. The branch lines BL are integrally formed with the common voltage line CL, and the branch lines BL branch from the common voltage line CL and extend toward the pixel electrode PE. First or second storage capacitors SC1 and SC2 are formed at a portion where the branch line BL overlaps the pixel electrode PE.

The pixel electrode PE of each pixel area PED is a polygon including first to fourth sides d1 to d4. The first side d1 is adjacent to the common voltage line CL. The second side d2 is adjacent to the first gate line GL1, the third side d3 is adjacent to the second gate line GL2, and the fourth side d4 is the data line. Adjacent to (DL). One branch line BL overlaps the pixel electrode PE to include at least one of the first to fourth sides d1 to d4.

FIG. 3 is a diagram illustrating a first embodiment of a structure of any two adjacent pixel cells of FIG. 2, and FIG. 4 is a cross-sectional view taken along lines I to I of FIG. 3 and along lines II to II of FIG. 3. .

As illustrated in FIG. 3, the first branch line BL1 extending from one side of the common voltage line CL may include the first and the first pixels of the first pixel electrode PE1 positioned at one side of the common voltage line CL. A portion of the first pixel electrode PE1 is overlapped to include the three sides and the fourth sides d1, d3, and d4. In this case, the first branch line BL1 is located closer to the second gate line GL2 than the first gate line GL1. The first storage capacitor SC1 is formed at a portion where the first branch line BL1 and the first pixel electrode PE1 overlap (hatched portions). As shown in FIG. 4B, the first storage capacitor SC1 includes the first pixel electrode PE1 and the first branch line BL1, the first pixel electrode PE1 and the first pixel capacitor PE1. A protective film 335 formed between one line BL1 is formed.

The second branch line BL2 extending from the other side of the common voltage line CL may include first, second, and fourth portions of the second pixel electrode PE2 positioned on the other side of the common voltage line CL. A portion of the second pixel electrode PE2 is overlapped to include the sides d1, d2, and d4. In this case, the second branch line BL2 is located closer to the first gate line GL1 than the second gate line GL2. A second storage capacitor SC2 is formed at a portion where the second branch line BL2 and the second pixel electrode PE2 overlap (hatched portions). As shown in FIG. 4A, the second storage capacitor SC2 includes the second pixel electrode PE2 and the second branch line BL2, the second pixel electrode PE2 and the second pixel capacitor PE2. The passivation layer 335 is formed between two lines BL2.

3 and 4, the first thin film transistor TFT1 includes the gate electrode GE protruding from the first gate line GL1 and the source electrode SE protruding from the data line DL. The drain electrode DE is electrically connected to the first pixel electrode PE1, the semiconductor layer 333, and the ohmic contact layer 334.

The second thin film transistor TFT2 is electrically connected to the gate electrode GE protruding from the second gate line GL2, the source electrode SE protruding from the data line DL, and the second pixel electrode PE2. The drain electrode DE, the semiconductor layer 333, and the ohmic contact layer 334 are connected to each other.

Here, the non-described '400' of FIG. 4 represents the lower substrate.

FIG. 5 is a diagram illustrating a second embodiment of the structure of any two adjacent pixel cells of FIG. 2, and FIG. 6 is a cross-sectional view taken along lines I to I and lines II to II of FIG. 5. .

As illustrated in FIG. 5, the first branch line BL1 extending from one side of the common voltage line CL may include the first side of the first pixel electrode PE1 positioned at one side of the common voltage line CL. A part of the first pixel electrode PE1 is overlapped to include d1). The first storage capacitor SC1 is formed at a portion where the first branch line BL1 and the first pixel electrode PE1 overlap (hatched portions). As shown in FIG. 6A, the first storage capacitor SC1 includes the first pixel electrode PE1 and the first branch line BL1, the first pixel electrode PE1, and the first pixel capacitor PE1. A protective film 335 formed between one line BL1 is formed.

The second branch line BL2 extending from the other side of the common voltage line CL includes the first side d1 of the second pixel electrode PE2 positioned at the other side of the common voltage line CL. A part of the second pixel electrode PE2 is overlapped. A second storage capacitor SC2 is formed at a portion where the second branch line BL2 and the second pixel electrode PE2 overlap (hatched portions). As shown in FIG. 6B, the second storage capacitor SC2 includes the second pixel electrode PE2 and the second branch line BL2, the second pixel electrode PE2 and the second pixel capacitor PE2. The passivation layer 335 is formed between two lines BL2.

FIG. 7 is a diagram illustrating each pixel cell of FIG. 3 or FIG. 5 as an electrical equivalent circuit. As shown in the drawing, the first pixel cell includes a first thin film transistor TFT1 and a first liquid crystal capacitor 501. ), And a first storage capacitor capacitor SC1, and the second pixel cell includes a second thin film transistor TFT2, a second liquid crystal capacitor 502, and a second storage capacitor capacitor SC2. Here, reference numeral 555 not illustrated in FIG. 5 represents a common electrode.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

1 is a view showing several pixel cells provided in a conventional liquid crystal display device.

2 is a view showing a liquid crystal display device according to an embodiment of the present invention.

3 illustrates a first embodiment of the structure of any two adjacent pixel cells of FIG.

4 is a cross-sectional view taken along the lines of I-I and II-II of FIG. 3;

FIG. 5 illustrates a second embodiment of the structure of any two adjacent pixel cells of FIG. 2.

FIG. 6 is a cross-sectional view taken along the lines of I-I and II-II of FIG. 5; FIG.

7 is an electrical equivalent circuit of each pixel cell of FIG. 3 or 5;

* Explanation of symbols on the main parts of the drawings

GL1: first gate line GL2: second gate line

DL: Data line PE: Pixel electrode

HL1: first pixel row HL2: second pixel row

SC1: first auxiliary capacitor SC2: second auxiliary capacitor

TFT1: first thin film transistor TFT2: second thin film transistor

CL: Common Voltage Line

Claims (9)

Multiple data lines; First and second gate lines positioned to intersect the plurality of data lines; A plurality of common voltage lines alternately positioned with the plurality of data lines; And, A pixel electrode formed for each pixel region defined by the data line, each common voltage line, each first gate line, and each second gate line; And, And a plurality of branch lines extending from the common voltage line toward each pixel electrode and overlapping the pixel electrode. The method of claim 1, And each data line is formed between each common voltage line. The method of claim 1, And wherein each common voltage line is formed between each data line. The method of claim 1, The pixel electrode of each pixel region is a polygon including first to fourth sides; And, The first side is adjacent to the common voltage line, the second side is adjacent to the first gate line, the third side is adjacent to the second gate line, and the fourth side is adjacent to the data line. ; And one branch line overlaps the pixel electrode such that at least one of the first to fourth sides is included. The method of claim 4, wherein The branch line extending from one side of an arbitrary common voltage line overlaps a part of the pixel electrode to include the first, third and fourth sides of the pixel electrode located on one side of the arbitrary common voltage line. Located closer to the second gate line than the first gate line; And, The branch line extending from the other side of the arbitrary common voltage line overlaps a part of the pixel electrode to include the first, second, and fourth sides of the pixel electrode positioned on the other side of the arbitrary common voltage line, And a second gate line closer to the first gate line than the second gate line. The method of claim 4, wherein Branch lines extending from one side of an arbitrary common voltage line overlap a portion of the pixel electrode such that a first side of the pixel electrode located on one side of the arbitrary common voltage line is included; And, The branch line extending from the other side of the arbitrary common voltage line overlaps a portion of the pixel electrode to include the first side of the pixel electrode located on the other side of the arbitrary common voltage line. The method of claim 1, And each pixel electrode positioned at both sides of an arbitrary data line is sequentially supplied with a data signal through the arbitrary data line. The method of claim 1, A first switching element formed near the intersection between the first gate line and each data line; And, And a second switching element formed near the intersection between the second gate line and each data line. The method of claim 1, The common voltage line, the data line, and the branch line are all formed of the same material.

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