KR20090009724A - Memory cell structures, memory cell arrays, memory devices, memory controllers, memory systems, and methods of operating them - Google Patents

Abstract

The present invention discloses memory cell structures, memory arrays, memory devices, memory controllers, and memory systems that use bipolar junction transistor (bipolar junction transistor (BJT)) operation. The apparatus includes a memory array having a plurality of memory cells and a controller, each of the plurality of memory cells having a first node connected to each of at least one bit line, at least one source line, and at least one word line, a second node; And a floating body transistor having a node and a gate node, wherein the controller is configured to perform a refresh operation in response to a refresh command by selecting one of at least one source line and at least one bit line. When stored in a memory cell connected to the selected line, a first current caused by the bipolar junction transistor operation flows.

Description

Memory cell structures, memory cell arrays, memory devices, memory controllers, memory systems, and methods of operating them {Memory cell structures, memory cell arrays, memory devices, memory controllers, memory systems, and method of operating the same}

The present invention relates to memory cell structures, memory cell arrays, memory devices, memory controllers, memory systems, and methods of operating them having a transistor without a capacitor.

A typical memory, for example a dynamic semiconductor memory device (DRAM), has one transistor and one capacitor. However, due to the size of capacitors, especially capacitors, there is a limit to the size reduction of a general memory. As a result, memories have been developed with memory transistors with one transistor 1T and no capacitors, referred to as “capacitor-less” memories, and have been developed as a general capacitorless dynamic semiconductor memory device. The capacitor-less 1T DRAM, which is mentioned later, may comprise an electrically floating body.

In general, conventional capacitorless memory utilizes an SOI wafer with silicon on an insulator and accumulates multiple carriers (holes or electrons) in the floating body region, or emits multiple carriers from the floating body region. Identify the data that controls the area voltage. If a majority carrier is accumulated in the floating body region, this state is represented as data "1", and conversely, if a majority carrier is emitted from the floating body region, this state is represented as data "0".

There are two kinds of operation of a general capacitorless memory device. One uses metal oxide semiconductor transistor (MOS) operating characteristics and the other uses bipolar junction transistor (BJT) operating characteristics. In general, it is disclosed that bipolar junction transistor operation has high speed operation and / or better charge retention properties than MOS operation.

It is an object of the present invention to provide memory cell structures, memory cell arrays, memory devices, memory controllers, memory systems, and methods of operating the same having a single transistor without a capacitor for bipolar junction transistor operation. have.

Embodiments illustrate memory cell structures, memory arrays, memory devices, memory controllers, and memory systems, and methods of operating them, including memory cell structures, memory arrays, memory devices, memory controllers, and It is shown that memory systems use bipolar junction transistor (BJT) operation.

Embodiments represent a memory array having a plurality of memory cells and a memory device having a control unit, each of the plurality of memory cells being connected to at least one bit line, at least one source line, and at least one word line, respectively; And a floating body transistor having a node, a second node, and a gate node, wherein the controller selects one of the at least one source line and the at least one bit line to perform a refresh operation in response to the refresh command. When the first data is stored in the memory cell connected to the selected line, the first current caused by the bipolar junction transistor operation flows.

An embodiment represents a memory array having a plurality of memory cells and a memory device having a control unit, each of the plurality of memory cells being connected to at least one bit line, at least one source line, and at least one word line, respectively; And a floating body transistor including a node, a second node, and a gate node, wherein the controller applies a bit line write voltage to at least one bit line and a source line voltage to at least one source line according to data information. The write operation is performed by applying a word line write voltage to at least one word line.

An embodiment illustrates a memory structure including a gate structure and an insulator silicon (SOI) structure including a substrate, an insulator, and a silicon layer, wherein the silicon layer includes impurity implanted first and second nodes, a floating body region, and a first structure. And a buffer region between the one of the second nodes and the floating body region, wherein the buffer region has an impurity concentration lower than that of the adjacent node and the floating body region, and the buffer region includes all one of the first and second nodes. Covering the boundary, a gate structure is formed over the silicon layer.

Embodiments illustrate a memory structure including a gate structure and a silicon structure over an insulator comprising a substrate, an insulator and a silicon layer, wherein the silicon layer is formed between the first and second nodes implanted with impurities, between the first node and the second node. A floating body region having a floating body length, and a buffer region between one of the first and second nodes and the floating body region, the gate structure having a gate length formed over the silicon layer, the buffer region being an adjacent node Or has an impurity concentration lower than that of the floating body region, and the floating body length is longer than the gate length.

Embodiments represent a memory structure comprising a silicon structure on an insulator comprising a substrate, an insulator and a silicon layer, wherein the silicon layer is impurity implanted emitter / source and collector / drain, floating body region, emitter / source and floating body. An auxiliary body region between the regions and a gate structure on top of the silicon, the auxiliary body region having a lower impurity concentration than the floating body region.

An embodiment represents a memory structure including a gate structure and a silicon structure over an insulator comprising a substrate, an insulator and a silicon layer, wherein the silicon layer is adjacent to the impurity implanted first and second nodes, the floating body region, and the floating body region. An elongated body region, and the gate structure is formed over the silicon layer.

An embodiment illustrates a memory cell structure including an insulating layer over a substrate, a silicon pattern formed over the insulating layer, the silicon pattern including a first node, a second node, and a floating body region, and a gate surrounding the floating body region. The length of P is shorter than the length of the floating body region, and the voltage difference between the voltages applied to the first and second nodes with respect to the set voltage applied to the gate induces a bipolar junction operation.

An embodiment encompasses a silicon pattern over an insulating layer including an insulating layer over the substrate, a first node, a second node, a floating body region and an extended body region over the floating body region, and a floating body region and an extended body region. A memory cell structure including a gate structure is shown.

An embodiment illustrates a method of controlling a memory device including memory cells without a plurality of capacitors, the method providing a mode register set (MRS) instruction that specifies one of a block refresh operation, a partial refresh operation, and a refresh operation. Providing a refresh command for the request.

An embodiment represents a memory controller having a register that stores an MRS instruction for selecting one of a block refresh and a partial refresh operation.

An embodiment represents a capacitorless memory device that includes a register that stores information for selecting one of a block refresh and a partial refresh operation.

An embodiment illustrates a memory cell structure comprising a silicon structure on an insulator comprising a substrate, an insulator, and a silicon layer, wherein the silicon layer includes first and second nodes, a floating body region, and a gate on the floating body region. The length of the gate is shorter than the length of the floating body region, and the voltage difference between the voltages applied to the first node and the second nodes with respect to the set voltage applied to the gate induces a bipolar junction operation.

An embodiment is a memory device having a plurality of memory cells and a control unit, each of which comprises a first node and a second node connected to each of at least one bit line, at least one source line, and at least one word line. And a gate, wherein the controller is configured to perform a read operation by selecting one of the at least one source line and not selecting one of the at least one word line, and if the first data is connected to the selected source line If stored at, the first current caused by the bipolar junction operation flows.

The memory cell structures, memory arrays, and memory devices of the present invention have an increased charge retention time, and thus, a refresh period can be increased, and bipolar junction transistor operation can be made more smoothly.

The memory system of the present invention does not require a separate command for transmitting a row address, and can transmit a row address and a column address simultaneously during a write command and a read command, thereby enabling high-speed operation. Thus, the control of the memory controller of the present invention is simplified.

The operation method of the present invention is simple and easy to control the operation of the bipolar junction transistor. In particular, it is possible to perform a partial refresh operation and a block refresh operation by controlling a bit line or a source line during the refresh operation, and although the block refresh operation takes longer for the refresh operation than the partial refresh operation, the two operations are longer. Both reduce the time required for the refresh operation.

Hereinafter, memory cell structures, memory cell arrays, memory devices, memory controllers, memory systems, and a method of operating the same will be described with reference to the accompanying drawings.

1A illustrates the structure of an embodiment of a memory cell without a capacitor in a horizontal structure. As shown in FIG. 1A, a memory cell without a capacitor having a horizontal structure includes a substrate 10, for example, the substrate may be a P conductive type or an N conductive type substrate. In the case of an NMOS transistor, the substrate 10 is a P conductive substrate.

The memory cell includes an insulating layer 12 on the substrate 10, which is an insulator in a silicon on insulator (SOI) arrangement. The memory cell includes a first node 14 and a second node 16 on the insulating layer 12. In the MOS operation, the first and second nodes 14 and 16 may be referred to as the source S and the drain D. In bipolar junction transistor BJT operation, the first and second nodes 14 and 16 may be referred to as emitter E and collector C. The first and second nodes 14 and 16 can be interchanged. As an example, the first and second nodes 14 and 16 may be N conductive or P conductive. If it is an NMOS transistor, the first and second nodes 14 and 16 may be N conductive.

The memory cell includes a floating body region 18 between the first and second nodes 14 and 16 and on the insulating layer 12, the conductivity type of the floating body region 18 being the first and second nodes. It may be of a different conductivity type than the ones 14 and 16. In an embodiment of an NMOS transistor, the floating body region 18 may be P conductive. As a result, the bipolar junction transistor BJT shown in FIG. 1A is an NPN conductive bipolar junction transistor. The floating body region 18 is electrically separated from the substrate 12 by the insulating layer 12 and floated. As shown in FIG. 1A, the floating body region 18 may have a floating body length L1.

The memory cell may further include a gate structure G including the gate insulating layer 20 and the gate 22, and the gate 22 may have a gate length L2. As shown in FIG. 1A, a capacitorless memory cell having a floating structure having a floating body region 18 may be formed on an insulating layer 12 additionally formed on a silicon substrate 10. As mentioned above, the emitter / source E / S or collector / drain C / D may be relative to one another. As a result, in the embodiment, the first node and the second node will be described in terms.

In general, emitter / source E / S is a node to which a relatively low voltage is applied, and collector / drain C / D is a node to which a relatively high voltage is applied. In general, L1 represents the distance between emitter / source E / S and collector / drain C / D, and L2 represents the gate length. In embodiments, L2 is longer than L1. It is generally used for self-alignment technology or lightly doped drain (LDD) technology to form emitter / source E / S and collector / drain (C / D), and heat treatment is applied for stabilization. Because.

1B illustrates an embodiment of a memory cell without a capacitor of vertical structure. As shown in FIG. 1B, a capacitorless memory cell having a vertical structure has a substrate 10, a first node 14, a floating body region 18, and a second node 16 perpendicular to the substrate 10. Are stacked. Floating body region 18 is electrically floating. As shown in FIG. 1B, the floating body region 18 may have a floating body length L1.

The gate insulating layer 10 and the gate 22 may surround the floating body region 18. For example, the gate insulating layer 10 and the gate 22 may be in contact with all or part of two or more surfaces of the floating body region 18. As an example, L2 is longer than L1.

If the memory cell without the capacitor of the vertical structure is an NMOS transistor, the first and second nodes 14 and 16 may be of the first conductivity type, for example, the N conductivity type, and the floating body region 18 may be formed. It may be of two conductivity type, for example, P conductivity type. In addition, the vertical capacitor structure may have an SOI substrate or may have a general bulk substrate as shown in FIG. 1B.

2 shows an equivalent circuit of the capacitorless memory cell of FIGS. 1A and 1B. As shown in Fig. 2, the equivalent circuit includes one NMOS transistor and one NPN bipolar junction transistor. For example, the emitter / source (E / S), collector / drain (C / D) and gate (G) of FIGS. 1A and 1B form an NMOS transistor. Likewise, the emitter / source E / S, collector / drain (C / D) and electrical floating region 18 (or base B) of FIGS. 1A and 1B form an NPN type bipolar junction transistor. As shown in FIG. 2, a coupling capacitor CC is formed between the gate G of the NMOS transistor and the base B of the bipolar junction transistor.

In an embodiment, bipolar junction transistors are used to program / write as well as to read and refresh memory cells. The bipolar junction transistor reads the data state of the memory cell to program / write the data state to the memory cell, and generates a bipolar transistor current that is used to refresh the data state of the memory cell.

3 illustrates a DC characteristic of a memory cell without a capacitor according to an embodiment of the present invention. As shown in Fig. 3, for example, when Vg is set to OV, -1V, -2V, respectively, Vds (or Vce) can rise from 0V to a voltage higher than OV, and logIds (or Ice) are μA. It is changed in units. As shown in FIG. 3, the left line of the graph for each gate voltage may be used to designate data “1”, and the right line may be used to designate data “0”. The difference between the left line designating data “1” and the right line designating data “0” can be referred to as the sensing margin for each gate voltage. There are more carriers in the floating body region 18 for data “1” than there are multiple carriers in the floating body region 18 for data “0”. In particular, FIG. 3 shows a sharp change in current flow when Vds is 1.5V or more for all three gate voltages. Rapid current increase is described below.

As shown in Figures 2 and 3, increasing the voltage Vds is the forward bias between emitter / source (E / S) and base (B) and the reverse between base (B) and collector / drain (C / D). The potential of the electrically floating region 18 or the body B, which causes the bias, is increased. Thus, the bipolar junction transistor is turned on. As a result, electrons move through the body B from the emitter / source (E / S) to the junction between the base B and the collector / drain (C / D), which electrons collide with the silicon barrier at the junction. And electron-hole pairs. This may be referred to as impact ionization or band-to-band tunneling.

For each electron-hole pair, electrons move to the collector / drain (C / D), and holes move to the base (B). Then, the voltage of the base B increases, and more electrons from the emitter / source E / S are injected into the floating body region, and through the body B, the base B and the collector / drain C / D) to reach the junction. The above-described operation is performed repeatedly, and due to the positive feedback, the multiplication can be large, which may be referred to as "avalanche generation". As a result of the positive feedback, holes accumulate in the floating body region, which state may be referred to as data state "1".

As shown in FIG. 3, bipolar junction transistor operation occurs faster when Vg = 0V than when Vg = −1V and Vg = −2V. This means that the body has a higher potential of Vg = 0 V and a lower Vg base (B) and emitter / source (E / S) between the high Vg base (B) and the emitter / source (E / S). This is because the forward bias is reached faster than the voltage between. Similarly, bipolar junction transistor operation of data "1" occurs faster than bipolar junction transistor operation of data "0".

4 illustrates a memory device according to an exemplary embodiment of the present invention, and FIG. 4 illustrates a memory device including a memory array 150, a row controller 52, and a column controller 54.

The memory array 150 includes memory cells MC1 ˜ MCi without a plurality of capacitors, and each memory cell is connected to the row controller 52 and the column controller 54. Each of the row controller 52 and the column controller 54 receives a write command WR, a read command RD, a refresh command REF, and / or address signals ADD. Each memory cell is also connected to word lines WL1, ..., WLi, source lines SL1, ..., SLi, and bit lines BL1, ..., BLj. As shown in FIG. 4, each row of memory cells has a corresponding word line and a corresponding source line, that is, the number of word lines and the number of source lines are the same. This structure may be referred to as a separate source line structure. In the embodiment of Figure 4, the first node is connected to the source line and the second node is connected to the bit line. As shown in FIG. 4, the word lines WL1 to WLi and the source lines SL1 to SLi may be disposed in the same direction, and the bit lines BL1 to BLj may be words. It may be arranged in a direction orthogonal to the lines and source lines.

As shown in FIG. 4, the row controller 52 selects one of the word lines and one of the source lines in response to one of the write command WR, the read command RD, and the refresh command REF. The address ADD may be received for selection. The column controller 54 may receive an address ADD to select one of the bit lines in response to one of the write command WR, the read command RD, and the refresh command REF.

The column controller 54 may provide data information to the selected bit line during the write operation and receive data information from the selected bit line during the read operation. In addition, the column controller 54 may supply a voltage level set to at least one of the bit lines during the refresh operation.

In an embodiment, the refresh command REF may be supplied from an external device or internally generated by counting the refresh period.

Although the row control unit 52 and the column control unit 54 are illustrated separately in FIG. 4, the row control unit 52 and the column control unit 54 may be implemented as one control unit that performs the functions of the two control units.

FIG. 5 illustrates a timing diagram of an embodiment of a row operation of the memory device of FIG. 4. FIG. 5 illustrates a write operation, a read operation, and a refresh operation for writing both data “1” and data “0”. In the following embodiments, the refresh operation may be a block refresh operation or a partial refresh operation. In the block refresh operation, all memory cells are refreshed at the same time, and the block refresh operation may perform the refresh at a high speed, but requires a large amount of current. In a partial refresh operation, the cells are refreshed simultaneously in groups of cells (e.g., 2, 4, or 8), and each group is refreshed sequentially until all memory cells are refreshed. The partial refresh operation requires low current, but cannot perform fast refresh.

As shown in Fig. 5, the sections T0, T3 and T5 designate a maintenance or precharge or standby state before and / or after a write, read or refresh operation, and the sections T1 and T2 are write sections Twrite. , T4 designates a read section Tread, and T6 designates a refresh section Treat. For the bit lines BL1-j during the write operation and the bit line currents iBL1-j during the write, read and refresh operations, in the drawing, the solid lines indicate data “0” for the dotted lines. What is shown is for data "1".

As shown in FIG. 5, data '1' or data '1' is written in the memory cells MC1 connected to one row connected to the word line WL1 and the source line SL1 during the write period Twrite. It is read during the read period Tread. However, this is only an embodiment and can be written and read for memory cells connected to any row.

As shown in FIG. 5, in the period T0 before the write operation, the bit line sustain voltage is applied to the bit lines, for example, OV, and the source line sustain voltage, for example, 0V is applied to the source lines. Is applied, and a word line sustain voltage, for example -1V, is applied to the word lines.

As shown in FIG. 5, in the period T1, if it is desired to write data “0” to the memory cells MC1, the column controller 54 writes a bit line of a first level, for example, 0.5V. The voltage is supplied to the bit lines BL1 to j.

If it is desired to write data “1” to the memory cells MC1, the column controller 54 supplies bit line write voltages of a second level, for example, 0V, to the bit lines BL1 to j. In an embodiment, the second level of the bit line write voltage may be equal to the bit line sustain voltage, eg, 0V.

The memory cells MC2 to i have a bit line holding voltage, eg, OV, a source line holding voltage, eg, 0V, and a word line holding voltage, eg, -1V, corresponding bit lines, source line. And word lines may maintain a data state stored in the memory cells MC2 to i.

At this time, the row controller 52 supplies a source line write voltage, for example, 2V to the source line SL1, and supplies a source line sustain voltage, for example, 0V, to all other source lines SL2 to i. Supply continuously.

The row controller 52 supplies a word line write voltage, for example, OV, to the word line WL1, and continuously supplies the word line holding voltage, eg, -1V, to all other word lines WL2 to i. To supply.

As shown in Fig. 5, first, the bit line write voltage (voltage level depends on the data information to be written) is applied to the bit lines BL1 to j, and then the source line write voltage is applied to the source line SL1. Is applied. Finally, a word line write voltage is applied to the word line WL1. As shown in Fig. 5, when the bit line write voltage, the source line write voltage and the word line write voltage are applied to write data “1”, the voltage i2 flows through the bit lines BL1 to j.

As shown in the timing diagram of Fig. 5, for the data " 1 ", during the period T1, Vds is 2V and Vg is 0V. Thus, according to FIG. 3, the current i2 flowing through the bit lines BL1 to j is caused by the avalanche generation of the bipolar junction transistor operation. For the data "1", during the period T2, Vds is 2V and Vg is -1V. Thus, according to FIG. 3, the current i1 flowing through the bit lines BL1 to j is caused by the avalanche generation of the bipolar junction transistor operation. As illustrated in FIG. 5, the current i1 flowing through the bit lines BL1 to j during the period T2 is smaller than the current i2. This is because the body potential decreases as a result of the coupling effect of the coupling capacitor CC.

As shown in the timing diagram of Fig. 5, for the data " 0 ", during the period T1, Vds is 1.5V and Vg is 0V. Thus, according to FIG. 3, avalanche generation of the bipolar junction transistor operation is not induced, and holes may be emitted to the bit lines BL1 to j by the gate coupling effect. Similarly, for the data "0", during the period T2, Vds is 1.5V and Vg is -1V. Thus, according to FIG. 3, avalanche generation of the bipolar junction transistor operation is not caused, and as a result, no current flows through the bit lines BL1 to j.

The bit line write voltage must be applied before the source line write voltage is applied, which is equivalent to the collector / drain C / D if the source line SL1 changes to 2V before the voltage is applied to the bit line BL1. This is because the voltage between the emitter / source (E / S) becomes 2V. As shown in Fig. 3, the bipolar junction transistor operation is triggered, holes can accumulate in the floating body region B, and as a result, data " 1 " can be rewritten regardless of the data information.

As shown in Fig. 5, the application of the bit line write voltage cannot be instantaneous. The bit line write voltage may begin to be applied before the source line write voltage is applied. Alternatively, the bit line write voltage may reach a predetermined state (eg, the first level) before the source line write voltage is applied.

The source line write voltage must be applied before the word line write voltage is applied. This is because if the word line write voltage is changed to OV before the source line write voltage is applied to the source line SL1, the holes in the floating body region B may be caused by the coupling effect of the coupling capacitor CC. BL1) or source line SL1.

Further, as shown in the timing diagram of FIG. 5, during the period T2, the word line sustain voltage is applied back to the word line WL1 before the source line sustain voltage is applied to the source line SL1. The source line sustain voltage is again applied to the source line SL1 before the bit line sustain voltage is applied to the bit line BL1. In particular, the word line sustain voltage is applied to the word line WL1 before the source line sustain voltage is again applied to the source line SL1, which is applied if the word line sustain voltage is applied before the word line sustain voltage is applied to the word line WL1. When SL1 is changed to 0V, holes in floating body region B are removed to source line SL1 due to the forward bias between floating body region B and source line SL1, resulting in memory cells ( This is because the data “1” written to MC1) may be damaged.

In addition, the source line sustain voltage must be applied to the source line SL1 again before the bit line sustain voltage is applied to the bit line BL1. This is because if the voltage of the bit line BL1 is changed to OV before the source line sustain voltage is applied to the source line SL1, the voltage between the collector / drain C / D and the emitter / source E / S. This is because (Vds) becomes 2V, which causes bipolar junction transistor operation, and as a result, data " 0 " written in the memory cells MC1 may be damaged.

Although FIG. 5 shows that all memory cells connected to the word line WL1 and the bit lines BL1 to j (or BLi) are written one of the data “1” and the data “1”, this is briefly described. For the purpose of explanation, each memory cell may be written with data "1" or data "0" depending on the voltage of the corresponding bit line.

FIG. 5 illustrates a read operation according to an exemplary embodiment of the present invention. As shown in FIG. 5, one row of memory cells in which a read operation is connected to the word line WL1 and the source line SL1 during the period T4. Is performed against.

As shown in FIG. 5, in the period T3 before the read operation, the bit line sustain voltage, for example, 0V, in the bit lines BL1 to j, the source line sustain voltage in the source lines SL1 to i, For example, 0V and a word line sustain voltage, for example, -1V, are applied to the word lines WL1 to i.

The row controller 52 supplies a source line read voltage, for example, 2V to the source line SL1, and continuously applies a source line sustain voltage, for example, 0V, to the other source lines SL2 to i. do. The row controller 52 continuously supplies a word line sustain voltage, for example, -1V to the word lines WL1 to i.

In an embodiment, the read operation may be performed by supplying a source line read voltage connected to the memory cell being read. During the read operation, the bit lines BL1 to j may be electrically floated after being precharged by the sustain voltage, and the voltages of the bit lines BL1 to j may vary according to data stored in the memory cell. . That is, the column controller 54 does not need to supply the sustain voltage to the bit lines during the read operation. In addition, the above description is applicable to the case where the voltage sense amplifier is used as the bit line sense amplifier. However, it is not applicable if the current sense amplifier is used as a bit line sense amplifier.

The memory cells MC2 to i are maintained in a sustained state by supplying a bit line sustain voltage, for example, OV, a source line sustain voltage, for example, OV, and a word line sustain voltage, for example, -1V. Can be.

As shown in Fig. 3, when the voltage Vds between the drain and the source reaches 2V when Vg is -1V, the bipolar junction transistor operation is induced for the data "1" cell, not the data "0" cell. do. That is, the read current i1 caused by the bipolar junction transistor operation flows through the data “1” cell, and the read current i1 does not flow through the data “0” cell. In an embodiment, the write current i2 and the read current i1 may be the same.

As a result, the data can be identified by a later sense amplifier, for example a current sense amplifier or a voltage sense amplifier. In an embodiment, in a row operation such as that shown in FIG. 5, the same number of sense amplifiers are required as the data for each of the bit lines is read.

In addition, data “1” and data “0” stored in the memory cell connected to the selected source line SL1 during the read operation may be restored by the bipolar junction transistor operation and the coupling operation, respectively.

5 is an operation timing diagram illustrating a refresh operation according to an embodiment of the present invention.

As shown in FIG. 5, in the period T5 before the refresh operation, the bit lines BL1 to j may include a bit line sustain voltage, for example, 0V, a source line sustain voltage as the source lines SL1 to i, For example, 0V and a word line sustain voltage, for example -1V, are applied to the word lines WL1 to i.

When the refresh command REF is generated by an external device or an internal circuit, the row controller 52 supplies a refresh voltage, for example, 2V to all the source lines SL1 to i. In addition, the row controller 52 may sequentially supply the refresh voltage to at least two source lines, thereby reducing the current during the refresh operation. The number of source lines that are active at one time during the refresh operation can be set by the user using the setup steps described below in detail with respect to FIG. 20.

The memory cells connected to the source lines SL1 to i are refreshed by supplying voltages to the source lines SL1 to i that may cause a bipolar junction transistor operation to the cells in which the data “1” are stored. That is, cells in which data “1” are stored are refreshed by the bipolar junction transistor operation, and cells in which data “0” are stored are refreshed by the coupling effect between the source line and the floating body region. The row controller 52 continuously supplies a word line sustain voltage, for example, -1V to the word lines WL1 to i.

As shown in FIG. 5, during the refresh period Tre1, current i1 flows through a bit line connected to a cell in which data “1” is stored. In an embodiment, the refresh current i1 may be the same as the read current i1 and / or the write current i2.

In an embodiment, the refresh operation may be performed by supplying a refresh voltage to at least one bit line instead of applying a voltage to at least one source line.

As shown in FIG. 5, all source lines SL1 to i are refreshed. If a voltage that can cause bipolar junction transistor operation is supplied to the mode source lines or all the bit lines, all the memory cells can be refreshed at the same time. This may be referred to as block refresh.

In an embodiment, the number of source lines selected for a concurrent refresh operation is a group of source lines (eg, 2, 4 or 8) in a mode register set by a user, which will be described in detail below with respect to FIG. Can be in units. This may be referred to as a partial refresh operation.

In an embodiment, the refresh operation need not be performed by the sensing operation.

FIG. 6 is an operation timing diagram for describing an operation of one cell of the memory device of FIG. 4. FIG. 6 is an embodiment of a write operation (write operation for data “1” and data “0”), a read operation, and a refresh operation. It represents. In the embodiments described below, the refresh operation may be a block refresh operation or a partial refresh operation.

As shown in FIG. 6, the write operation and the read operation are performed only on the memory cell MC1 connected to the bit line BL1, the source line SL1, and the word line WL1, and the source line SL1 and the word are performed. The other memory cell MC1 connected to the line WL1 is not performed and is in a prohibition state. Other descriptions other than the prohibited state for both the write operation and the read operation may be easily understood with reference to the description of FIG. 5.

As described above, the difference between FIG. 5 and FIG. 6 is that in FIG. 6, one cell is written or read rather than one row. As a result, in FIG. 6, the remaining cells of one row that are not written or read are prohibited from being written or read. In an embodiment, the remaining cells of one row are prohibited from being written or read by applying the bit line write inhibit voltage or the bit line read inhibit voltage to the bit lines BL2 to j.

In the write operation, the bit line write prohibition voltage, for example, 1V is applied to the bit lines BL2 to j during the periods T1 and T2. As a result, Vds is 1V, and as shown in Fig. 3, the bipolar junction transistor operation is inhibited and no current flows.

Similarly, during the read operation, the bit line read prohibition voltage, for example, 1V, is applied to the bit lines BL2 to j during the period T4. As a result, Vds is 1V, and as shown in Fig. 3, the bipolar junction transistor operation is inhibited and no current flows.

The refresh operation shown in FIG. 6 is the same as the refresh operation shown in FIG. 5.

The timing diagram of FIG. 6 clearly shows that the random access operation of the memory cell array is possible.

As shown in Figs. 5 and 6, the memory device requires only two voltage levels, a word line write voltage and a word line sustain voltage for write, read and refresh operations.

FIG. 7 illustrates a memory device according to an embodiment of the present invention. Unlike the memory device according to the embodiment shown in FIG. 4, which shows a separate source line structure, the memory device of FIG. 7 may include, for example, adjacent memory cells ( The common source line structure in which MC2 and MC3 share the corresponding source line SL2 is shown. The description of the rest of FIG. 7 may be easily understood with reference to the description of FIG. 4.

As shown in FIG. 7, the number of source lines SL1 to k is smaller than the number of word lines WL1 to i. The advantage of this arrangement is that it reduces layout complexity. In addition, as described in the embodiment of FIG. 4, the row controller 52 and the column controller 54 may be implemented as one controller.

FIG. 8 is an operation timing diagram for describing a row operation of the memory device of FIG. 7 and illustrates a timing diagram of an embodiment of a write operation (data “1” and data “0” write operation), a read operation, and a refresh operation. In the embodiments described below, the refresh operation may be a block refresh operation or a partial refresh operation.

The timing diagram of FIG. 8 shows that the gate voltage Vg during the periods T0, T3, T5 is lower than that shown in FIG. 5 because the transistors sharing the common source lines SL1-k are likely to be off. It is similar to the timing diagram of FIG. 5 except that it can be a negative (eg -2V) voltage.

In the embodiment shown in FIG. 8, the order of the control signals applied to the bit lines BL1 to j, the source lines SL1 to k and the word lines WL1 to i during the write operation are described in FIG. 5. It may be the same as shown.

As shown in the timing diagram of FIG. 8, for the data “1”, during the period T1, Vds is 2V and Vg is 0V, so, according to FIG. 3, through the bit lines BL1 to j. Current i3 is caused by the avalanche generation of bipolar junction transistor operation. For the data “1”, during the period T2, even though Vds is 2V and Vg is -2V, the bit lines are maintained enough to create a forward bias between the bit lines BL1 to j. Current i4 through BL1-j is caused by the avalanche generation of the bipolar junction transistor operation. As shown in FIG. 8, the current i4 through the bit lines BL1 to j is smaller than the current i3 during the period T2. This is because the body potential decreases due to the coupling effect of the coupling capacitor CC.

As shown in the timing chart of Fig. 8, for the data " 0 ", Vds is 1.5V and Vg is 0V during the period T1. Thus, according to FIG. 3, avalanche generation of the bipolar junction transistor operation is not caused. Similarly, for the data " 0 ", during the period T2, Vds is 1.5V and Vg is -2V. Thus, according to FIG. 3, avalanche generation of the bipolar junction transistor operation is not caused. As a result, no current flows through the bit lines BL1 to j.

In an embodiment, the word line write voltage may be -1V rather than 0V as shown in FIGS. 5 and 8.

As shown in FIG. 8, three levels of voltage on word lines WL1 to i, -2V,-instead of two levels of voltage for word lines WL1 to i, as shown in FIG. 1V and 0V may be used, but two levels of voltage, for example, −1V and 0V, may be used as shown in FIG. 5.

In the embodiment shown in FIG. 8, the order of control signals applied to the bit lines BL1 to j, the source lines SL1 to k, and the word lines WL1 to i during a read operation is shown in FIG. 5. May be the same as

As shown in FIG. 8, during the read operation, the row controller 52 supplies a source line read voltage, for example, 2V to the source line SL1, and supplies the source line to all remaining source lines SL2 to k. A sustain voltage, for example 0V, is continuously supplied. The row controller 52 applies a word line read voltage, for example, -1V to the word line WL1, and continuously applies a word line sustain voltage, for example, -2V, to the other word lines WL2 to i. To supply.

In an embodiment, the read operation may be performed by supplying only the source line read voltage to the source line connected to the memory cell being read. In the read operation, the bit lines BL1 to j may be electrically floated after being precharged by the sustain voltage, and the voltages of the bit lines BL1 to j may be changed according to data stored in the memory cell. have. That is, the column controller 54 does not need to supply the sustain voltage to the bit lines BL1 to j during the read operation, and the above description can also be applied when the voltage sense amplifier is used as the bit line sense amplifier, It is not applicable when the current sense amplifier is used as a bit line sense amplifier.

As shown in Fig. 3, when the gate voltage Vg is -1V, if the voltage Vds between the drain and the source only reaches 2V, the bipolar junction transistor operation is not a cell in which data "0" is stored. “1” is triggered for the stored cell. That is, the read current i5 caused by the data bipolar junction transistor operation flows for the memory cell in which data "1" is stored, and not in the memory cell in which data "0" is stored.

As a result, the data can be identified by a sense amplifier, for example a current sense amplifier or a voltage sense amplifier.

In addition, during read operation, data “1” and data “0” may be restored by the bipolar junction transistor operation and the coupling effect, respectively.

In the embodiment of FIG. 8, except that the row controller 52 selects at least two word lines and supplies a word line refresh voltage to the at least two word lines, the bit lines BL1 to j, The order of the control signals for the refresh operation between the source lines SL1 to k and the word lines WL1 to i may be the same as the read operation illustrated in FIG. 5. The word line refresh voltage may be equal to the word line read voltage, and the read current i5 may be equal to the refresh current i6. The same description as the refresh operation of FIG. 5 may be applied to the refresh operation of FIG. 8.

FIG. 9 is a timing diagram for describing an operation of one cell of the memory device shown in FIG. 7. Fig. 9 shows a timing diagram of an embodiment of a write operation (write operation of data “1” and data “0”), read operation, and refresh operation. In the embodiments described below, the refresh operation may be a block refresh operation and a partial refresh operation.

As shown in FIG. 9, the write operation and the read operation are performed on only one memory cell MC1 connected to the bit line BL1, the source line SL1, and the word line WL1, and the source line SL1 and the word are performed. The other memory cells MC1 connected to the line WL1 are in a prohibited state. Except for the prohibition states for the write operation and the read operation, they are the same as those shown in FIG. 8.

As described above, the difference between FIG. 8 and FIG. 9 is not written or read in all cells connected to one row, but is written or read in only one cell in FIG. 9.

In the write operation, the bit line prohibition voltage, for example, 1V is applied to the bit lines BL2 to BLj during the periods T1 and T2. As a result, Vds is 1V, and as shown in Fig. 3, the bipolar junction transistor operation is prohibited and no current flows.

Similarly, during the read operation, a bit line read prohibition voltage, for example, 1V, is applied to the bit lines BL2 to BLj during the period T4. As a result, Vds is 1V, and as shown in Fig. 3, the bipolar junction transistor operation is prohibited, and no current flows.

As shown in FIG. 9, the refresh operation is the same as in FIG.

The timing diagram of FIG. 9 clearly shows that the random access operation of the memory cell array is possible.

As shown in Figures 8 and 9, although three levels of voltage (e.g., word line write voltage of 0V, word line refresh voltage and word line read voltage of -1V, and word line sustain voltage of -2V), Although shown for these word lines WL1 to i, a word line write voltage of 0 V for two levels of voltage (e.g., as shown in FIG. 5, and word lines WL1 to i) and- 1 V word line holding voltage, word line read voltage, word line refresh voltage) may be used.

10 illustrates a memory device according to an embodiment of the present invention. FIG. 10 illustrates a memory device including a plurality of memory blocks BK1, BK2,..., BKn as well as a row controller and a column controller. In an embodiment, each memory cell block may be the same as or similar to the memory cell blocks shown in FIGS. 4 and 7. In addition, as illustrated in FIG. 10, sense amplifiers SA1 to n may be provided between memory blocks, and the sense amplifiers SA1 to n may be voltage sense amplifiers or current sense amplifiers.

10 illustrates an open bit line structure, but may also be applied to a folded bit line structure.

In the embodiment shown in FIG. 10, the memory cell array may include a plurality of memory cell blocks as shown in FIGS. 4 and 7, and may write and read data to at least one selected memory cell block. In an embodiment, the row controller 52 ″ selects at least one memory block, source line and word line in the selected memory block in response to the write command WR, read command RD and / or address signal ADD. In addition, an appropriate voltage may be supplied to the selected source line and the word line.

In addition, the row controller 52 ″ selects at least one memory block in response to the refresh command REF and supplies a refresh voltage to at least two source lines in the selected memory block. In addition, the row controller 52 ″ may perform a block refresh operation when the refresh voltage is supplied to all the source lines SL1 to k in the selected memory block. In addition, all memory blocks of the memory device may be refreshed by supplying a refresh voltage to all source lines SL1 to k in each memory block.

In an embodiment, the column controller 54 ″ controls the bit line voltage level according to data information according to one row operation or one cell operation. In addition, the column controller 54 ″ may control the refresh operation by supplying a predetermined voltage to at least one bit line. If a predetermined voltage is applied to all the bit lines BL1 to j, all the memory cells in the memory cell array may be refreshed. The predetermined voltage may be the same as the refresh voltage applied to the source line.

In the embodiment shown in FIG. 10, each of the sense amplification blocks SA1 to n may supply data information to a corresponding bit line during a write operation, and sense and amplify data of a memory cell. For one row operation, the number of sense amplifiers of each of the sense amplification blocks SA1 to n may be equal to the number of bit lines. For the random access operation, the number of sense amplifiers of each sense amplification block SA1 to n may be the same. The number of sense amplifiers can be reduced.

Bipolar junction transistor operation for a memory device including a memory cell without a capacitor will be described according to an embodiment. Although the memory cell structures of FIGS. 1A and 1B may be used for a memory device such as FIGS. 4, 7, and 10 described above. Additional new memory cell structures for the memory devices of FIGS. 4, 7 and 10 according to an embodiment will be described later. In the figures, like elements of memory cells have like reference numerals.

11A and 11B show a memory cell structure according to an embodiment of the present invention. As shown, the source line may be connected to the collector / drain (C / D) and the bit line may be connected to the emitter / source (E / S). In an embodiment, the first and second nodes 14 and 16 in the silicon layer may be N-type impurities. In an embodiment, the emitter / source E / S may be an N-type impurity (eg, N +) having a higher impurity concentration than the collector / drain (C / D). In an embodiment, as shown in FIG. 11A, the gate, emitter / source (E / S) and / or collector / drain (C / D) do not overlap. As shown in FIG. 11A, the boundary between the floating body region 18, emitter / source (E / S) and / or collector / drain (C / D) is at the gate, emitter / source (E / S) and The collector / drain (C / D) does not have to overlap, and may have any form.

As shown in FIG. 3, the sensing margin may be determined by the voltage Vds between the data “1” and the data “0”. In order to increase the sensing margin, the capacitance of the gate G between the gate and the floating body region must be reduced in proportion to the drain capacitance Cd or the source capacitance Cs.

As a result, there should be no overlap between the gate and the source and / or drain. Because of the large spacing between the gate G and the emitter / source E / S and the collector / drain C / D, non-overlapping memory cell structures have lower energy band slopes than the memory cell structure of FIG. Can be. As a result, compared with the memory cell structure of FIG. 1A, the maximum electric field (E-field) can be reduced and the recombination rate can be reduced. Due to this property, the non-overlapping memory cell structure of FIG. 11A exhibits better retention time and / or better leakage characteristics.

In addition, since the capacitance Cgd between the gate and the drain becomes small, a gate induced drain leakage (GIDL) phenomenon that may damage the data “0” may be reduced.

Additionally, the reduced gate capacitance Cg can be compensated for by making the insulating layer 20 thinner to stabilize the coupling capacitance between the gate and the floating body region 18.

Although not shown in FIG. 11A, the gate may overlap only one of the first node 14 and the second node 16. For example, the gate may overlap only one of the first node 14 and the second node 16 that receives a higher voltage during the bipolar junction operation.

The sensing margin may vary depending on the charge difference stored in the floating body region between the cell where data “1” is stored and the cell where data “0” is stored. The cell in which data "1" is stored has more charge than the cell in which data "0" is stored, and the bipolar junction transistor is because the body potential of the cell in which data "1" is stored is higher than the body potential of the cell in which data "0" is stored. The operation is triggered in the cell in which data "1" is stored faster than in the cell in which data "0" is stored. This can be seen from the left side of the cell in which data “1” is stored for all the gate voltages Vg as shown in FIG. 3.

As a result, if more charge can be stored in the floating body region of the cell where data “1” is stored during the write operation, a better sensing margin is ensured.

In addition, the average free path of electrons between the base and the collector may be longer than the average free path of FIG. 1A. Accordingly, occurrence of avalanches may occur more easily. Also, more charge can be stored in the floating body region of the data “1” cell. In an embodiment, the impurity concentration between emitter / source (E / S) may be greater than the impurity concentration between collector / drain (C / D). Additionally, as described in the embodiment, holes accumulated by bipolar junction transistor operation can be maintained near the gate due to the negative word line sustain voltage. As shown in FIG. 11A, the retention time can be improved if the floating body region 18 near the gate G is wider than at least one other portion of the floating body region 18.

11B illustrates a memory cell having a vertical structure in accordance with an embodiment of the present invention. As shown in FIG. 11B, a capacitorless memory cell having a vertical structure includes a substrate 10, a first node 14 vertically stacked on the substrate 10, a floating body region 18, and a second node. 16). Floating body region 18 may be electrically floating. As shown in FIG. 11B, the floating body region 18 may have a floating body length L1.

The gate insulating layer 20 and the gate 22 may be formed to surround the floating body region 18. For example, the gate insulating layer 20 and the gate 22 may contact the front surface of the floating body region 18 or the surfaces of two or more portions. If the memory cell without the capacitor of the vertical structure is an NMOS transistor, the first and second nodes 14 and 16 may be of the first conductivity type, for example, the N conductivity type, and the floating body region 18 may be formed. It may be of two conductivity type, for example, P conductivity type. Also, a memory cell without a vertical capacitor may have a SOI substrate or a general bulk substrate as shown in FIG. 11B.

As shown, the source line may be connected to the collector / drain (C / D), and the bit line may be connected to the emitter / source (E / S). In an embodiment, there is no overlap between the gate electrode and emitter / source (E / S) and / or collector / drain (C / D), as shown in FIG. 11B. Features mentioned with respect to FIG. 11A may exist in the memory cell of the vertical structure of FIG. 11B.

12A and 12B illustrate a memory cell structure in accordance with an embodiment of the present invention, as shown in FIGS. 12A and 12B, in order to improve the multiplication and avalanche occurrence, the buffer region 24 is a floating body region 18. And between collector / drain (C / D). In an embodiment, the buffer region 24 is not provided between the floating body region 18 and the emitter / source E / S. In an embodiment, the impurity concentration of the buffer region 24 may be lower than the impurity concentration of the collector / drain (C / D) and / or floating body region 18. In an embodiment, intrinsic semiconductor may be used as buffer region 24. In an embodiment, the buffer region 24 may have the same height as the adjacent second node 16. In an embodiment, the buffer region 24 may cover all of the boundaries of the adjacent second node 16. In an embodiment, the buffer region 24 is in contact with the insulating layer 12.

In an embodiment, buffer region 24 increases the average free path of electrons from the base to the collector / drain (C / D). By increasing the average free path, impact ionization for avalanche generation can be improved. Thus, more charge can be stored in the data “1” cell.

In an embodiment, the impurity concentration of the emitter / source (E / S) may be greater than the impurity concentration of the collector / drain (C / D). In an embodiment, if the buffer region 24 is an impurity concentration of N−, L2 may be greater than L1. On the other hand, if the buffer region 24 is an impurity concentration of P−, L2 may be smaller than L1.

As shown in FIG. 12B, the vertical cell structure can be implemented without increasing the layout area of the buffer area 24. This is because the buffer region 24 is formed in the vertical direction as shown in Fig. 12B.

12B illustrates a vertical structure memory cell according to an embodiment of the present invention. As shown in FIG. 12B, a memory cell having no vertical capacitor is stacked vertically on the substrate 10 and the substrate 10. The first node 14 includes a first body 14, a floating body region 18, a buffer region 24, and a second node 16. Floating body region 18 is electrically floating, and as shown in FIG. 12B, floating body region 18 may have a floating body length L1.

The gate insulating layer 20 and the gate 22 may surround the floating body region 18. For example, the gate insulating layer 20 and the gate 22 may contact all surfaces of the floating body region 18 or the surfaces of two or more portions. If the memory cell without the capacitor of the vertical structure is an NMOS transistor, the first and second nodes 14 and 16 may be of the first conductivity type, for example, the N conductivity type, and the floating body region 18 may be formed. It may be of two conductivity type, for example, P conductivity type. In addition, a memory cell without a vertical capacitor may have a SOI substrate or a general bulk substrate as shown in FIG. 12B.

As shown, to improve multiplication and avalanche occurrence, a buffer region 24 may be formed between the floating body region 18 and the collector / drain (C / D). In an embodiment, the buffer region 24 is not provided between the floating body region 18 and the emitter / source E / S. In an embodiment, the impurity concentration of the buffer region 24 may be lower than the impurity concentration of the collector / drain (C / D) and / or floating body region 18. In an embodiment, intrinsic semiconductor can be used as buffer region 24. In an embodiment, the buffer region 24 may have one impurity concentration of N-, N, or P-. In an embodiment, the buffer region 24 has the same height as the adjacent second node 16. In an embodiment, the buffer region 24 may cover all of the boundaries of the adjacent second node 16. In an embodiment, the buffer region 24 is in contact with the insulating layer 12.

12A and 12B, the boundary between the floating body region 18, emitter / source (E / S), collector / drain (C / D), and / or buffer region 24 may be of any shape. Can have

Other features described above with respect to FIG. 12A may also exist for the memory cell of the vertical structure of FIG. 12B.

In an embodiment, the capacitorless memory cell of the vertical structure may have a SOI substrate or a general bulk substrate as shown in FIG. 12B.

13A and 13B show a memory cell structure according to an embodiment of the present invention, and FIGS. 13A and 13B show a structure combining the features shown in FIGS. 11 and 12A and 12B. In the embodiment shown in Figs. 13A and 13B, L1 is greater than L2 even when the buffer region 24 is N-. Compared to FIGS. 11A and 11B, the embodiment shown in FIGS. 13A and 13B may result in a reduction in gate induced drain leakage and / or an increase in average free path.

As shown, the source line may be connected to the collector / drain (C / D) and the bit line may be connected to the emitter / source (E / S). In an embodiment, there is no overlap between the gate electrode G, the collector / drain C / D, and the emitter / source E / S, as shown in FIG. 13A. As shown in FIG. 3, the sensing margin may be determined by the voltage difference Vds between the drain and the source between the data “1” cell and the data “0” cell. In order to increase the sensing margin, the gate capacitance Cg with respect to the drain capacitance Cd or the source capacitance Cs must be reduced.

As a result, there is no overlap between the gate and the source or the drain, and in addition, since the capacitance Cgd between the gate and the drain is reduced, the gate induced drain leakage phenomenon that may damage the data “0” cell can be reduced.

In addition, the reduced gate capacitance Cg can be compensated for by making the insulating layer 20 thinner, which stabilizes the coupling capacitance between the gate and the body. In an embodiment, the gate length L2 is less than the floating body length L1. These parameters can improve scalability.

The sensing margin may vary depending on the charge difference stored in the floating body region 18 between the data "1" cell and the data "0" cell. The data "1" cell has more charge than the data "0" cell. Accordingly, the body potential of the data "1" cell is higher than the body potential of the data "0" cell. Bipolar junction transistor operation occurs faster in data “1” cells than in data “0” cells. This is because the graph of the data "1" cell is to the left of the graph of the data "0" cell, as shown in FIG.

As a result, if more charge can be stored in the floating body region 18 which is a data “1” cell during the write operation, it will have a better sensing margin.

Additionally, the average free path of holes between the base and the collector / drain (C / D) may be longer than the average free path of FIG. 1A. Accordingly, impact ionization for avalanche generation can occur more quickly. As a result, more charge can be stored in data “1” cells. As an example, the impact ionization of the emitter / source (E / S) may be greater than the impact ionization of the collector / drain (C / D).

As shown in FIGS. 13A and 13B, to improve multiplication and avalanche generation, a buffer region 24 may be formed between the floating body region 18 and the collector / drain (C / D). In an embodiment, the buffer region 24 is not provided between the floating body region 18 and the emitter / source E / S. In an embodiment, the impurity concentration of the buffer region 24 may be lower than the impurity concentration of the collector / drain (C / D). In an embodiment, intrinsic semiconductor can be used as buffer region 24. In an embodiment, the buffer region 24 may have one impurity concentration of N-, N, or P-. In an embodiment, the buffer region 24 has the same height as the adjacent second node 16. In an embodiment, the buffer region 24 may cover all of the boundaries of the adjacent second node 16. In an embodiment, the buffer region 24 is in contact with the insulating layer 12. In an embodiment, buffer region 24 increases the average free path of holes from the base to the collector / drain (C / D). By increasing the mean free path, impact ionization for avalanche development can be improved. Thus, more charge can be stored in the data “1” cell.

In an embodiment, the impurity concentration of the emitter / source (E / S) may be higher than the impurity concentration of the collector / drain (C / D).

As shown in FIG. 13B, a memory cell having a vertical structure may be implemented without increasing the layout area of the buffer area 24. This is because the buffer region 24 is formed in a vertical structure as shown in Fig. 13B.

As shown in FIGS. 13A and 13B, the boundary between floating body region 18, emitter / source (E / S), collector / drain (C / D), and / or buffer region 24 may be of any shape. Can have

In an embodiment, the capacitorless memory cell of the vertical structure may have an SOI substrate or a general bulk substrate as shown in FIG. 13B.

14A and 14B show a memory cell structure according to an embodiment of the present invention. As shown in FIGS. 14A and 14B, an auxiliary body region 26 is provided to increase the electron injection efficiency from the emitter / source (E / S) to the floating body region 18. In an embodiment, the impurity concentration of the auxiliary body region 26 may be less than the impurity concentration of the floating body region 18. In an embodiment, the floating body region 18 can be longer than the secondary body region 26. In an embodiment, the secondary body region 26 is in contact with the emitter / source E / S.

In an embodiment, the auxiliary body region 26 allows more holes to be injected into the floating body region 18 and to be obtained at the base and collector / drain (C / D), thus more effective bipolar junction transistor operation This can happen. In an embodiment, the impurity concentration of the emitter / source (E / S) is higher than the impurity concentration of the collector / drain (C / D) and / or base.

As shown in FIG. 14B, a memory cell having a vertical structure may be implemented without increasing the layout of the auxiliary body region 26. This is because the auxiliary body region 26 is formed in the vertical direction as shown in Fig. 14B.

As shown in FIGS. 14A and 14B, the boundary between floating body region 18, emitter / source (E / S), collector / drain (C / D), and / or auxiliary body region 26 may be of any shape. It can have

In an embodiment, the memory cell of the vertical structure may have a SOI substrate or a general substrate as shown in FIG. 14B.

15A-15C show an embodiment memory cell structure combining the features of FIGS. 11A-14B. FIG. 15A shows a memory cell structure combining the features of FIGS. 11A and 14A, in particular FIG. 15A shows a gate 22 and floating body region 18, L1 may be larger than L2, and auxiliary body region 26 may be In order to increase the electron injection efficiency from the emitter / source (E / S) to the floating body region 18.

As shown, the source line may be connected to the collector / drain (C / D) and the bit line may be connected to the emitter / source (E / S). In an embodiment, there is no overlap between gate 22, collector / drain (C / D), and emitter / source (E / S), as shown in FIG. 11A. As shown in FIG. 3, the sensing margin may be determined by the voltage difference Vds between the drain and the source between the data “1” cell and the data “0” cell. In order to increase the sensing margin, the gate capacitance Cg with respect to the drain capacitance Cd or the source capacitance Cs must be reduced.

As a result, there is no overlap between the gate 22 and the emitter / source (E / S) or collector / drain (C / D), and in addition, the capacitance (Cgd) between the gate and drain is reduced, so that the data “0 The gate induced drain leakage, which can damage the cell, can be reduced.

In addition, the reduced gate capacitance Cg can be compensated for by making the insulating layer 20 thinner, which stabilizes the coupling capacitance between the gate and the body. In an embodiment, the gate length L2 is less than the floating body length L1. These parameters can improve scalability.

The sensing margin may vary depending on the charge difference stored in the floating body region 18 between the data "1" cell and the data "0" cell. The data "1" cell has more charge than the data "0" cell. Accordingly, the body potential of the data "1" cell is higher than the body potential of the data "0" cell. Bipolar junction transistor operation occurs faster in data “1” cells than in data “0” cells. This is because the graph of the data "1" cell is to the left of the graph of the data "0" cell, as shown in FIG.

As a result, if more charge can be stored in the floating body region 18 which is a data “1” cell during the write operation, it will have a better sensing margin.

Additionally, the average free path of holes between the base and the collector / drain (C / D) may be longer than the average free path of FIG. 1A. Accordingly, impact ionization for avalanche generation can occur more quickly. As a result, more charge can be stored in data “1” cells. In an embodiment, the impurity concentration of the emitter / source (E / S) may be higher than the impurity concentration of the collector / drain (C / D).

In an embodiment, the impurity concentration of the auxiliary body region 26 may be lower than the impurity concentration of the floating body region 18. In an embodiment, the floating body region 18 can be longer than the secondary body region 26. In an embodiment, the secondary body region 26 is in contact with the emitter / source E / S.

In an embodiment, the auxiliary body region 26 allows more holes to be injected into the floating body region 18 and to be obtained at the base and collector / drain (C / D), thus more effective bipolar junction transistor operation This can happen. In an embodiment, the impurity concentration of the emitter / source (E / S) is higher than the impurity concentration of the collector / drain (C / D) and / or base.

The memory cells of the vertical structure may be implemented without increasing the layout of the auxiliary body region 26. This is because the auxiliary body region 26 is formed in the vertical direction as shown in Fig. 14B.

In an embodiment, the vertical memory cell may have the features of 15a, and the vertical memory cell may have an SOI substrate or a general substrate as shown in FIG. 15A.

FIG. 15B illustrates a memory cell having a combination of the features shown in FIGS. 12A and 14A. As shown in FIG. 15B, the buffer region 24 may be formed between the floating body region 18 and the collector / drain (C / D) to improve multiplication and avalanche generation. In an embodiment, the buffer region 24 is not provided between the floating body region 18 and the emitter / source E / S. In an embodiment, the impurity concentration of the buffer region 24 may be lower than the impurity concentration of the collector / drain (C / D). In an embodiment, intrinsic semiconductor can be used as buffer region 24. In an embodiment, the buffer region 24 may have one impurity concentration of N-, N, or P-. In an embodiment, the buffer region 24 has the same height as the adjacent second node 16. In an embodiment, the buffer region 24 may cover all of the boundaries of the adjacent second node 16. In an embodiment, the buffer region 24 is in contact with the insulating layer 12.

In an embodiment, buffer region 24 increases the average free path of holes from the base to the collector / drain (C / D). By increasing the mean free path, impact ionization for avalanche development can be improved. Thus, more charge can be stored in the data “1” cell.

In an embodiment, the impurity concentration of the emitter / source (E / S) may be higher than the impurity concentration of the collector / drain (C / D). In an embodiment, if buffer region 24 is N-, L2 may be longer than L1, whereas if buffer region 24 is P-, L2 may be less than L1.

As shown in FIG. 15B, an auxiliary body region 26 is provided to increase the electron injection efficiency from the emitter / source (E / S) to the floating body region 18. In an embodiment, the impurity concentration of the auxiliary body region 26 may be lower than the impurity concentration of the floating body region 18. In an embodiment, the floating body region 18 can be longer than the secondary body region 26. In an embodiment, the secondary body region 26 is in contact with the emitter / source E / S.

In an embodiment, the auxiliary body region 26 allows more holes to be injected into the floating body region 18 and to be obtained at the base and collector / drain (C / D), thus more effective bipolar junction transistor operation This can happen. In an embodiment, the impurity concentration of the emitter / source (E / S) is higher than the impurity concentration of the collector / drain (C / D) and / or base.

The vertical memory cells may be implemented without increasing the layout of the buffer area 24 and the auxiliary body area 26. This is because the buffer region 24 and the auxiliary body region 26 are formed in the vertical direction as shown in Figs. 13B and 14B.

In an embodiment, the vertical memory cell may have features of 15b, and in an embodiment, the vertical memory cell may have an SOI substrate or a general substrate as shown in FIG. 15A.

FIG. 15C illustrates an embodiment memory cell combining the features of FIGS. 11A, 12A and 14A. As shown in FIG. 15C, the source line SL is connected to the collector / drain C / D and the bit line BL. ) May be connected to the emitter / source (E / S). In an embodiment, there is no overlap between gate 22, collector / drain (C / D), and emitter / source (E / S), as shown in FIG. 11A.

As shown in FIG. 3, the sensing margin may be determined by the voltage difference Vds between the drain and the source between the data “1” cell and the data “0” cell. In order to increase the sensing margin, the gate capacitance Cg must be reduced with respect to the drain capacitance Cd or the source capacitance Cs. As a result, the gate 22 and the emitter / source E / S or collector / Since there is no overlap between the drains C / D, and in addition, the capacitance Cgd between the gate and the drain is reduced, a gate induced drain leakage phenomenon that may damage the data “0” cell can be reduced.

In addition, the reduced gate capacitance Cg can be compensated for by making the insulating layer 20 thinner, which stabilizes the coupling capacitance between the gate and the body. In an embodiment, the gate length L2 is less than the floating body length L1. These parameters can improve scalability.

The sensing margin may vary depending on the charge difference stored in the floating body region 18 between the data "1" cell and the data "0" cell. The data "1" cell has more charge than the data "0" cell. Accordingly, the body potential of the data "1" cell is higher than the body potential of the data "0" cell. Bipolar junction transistor operation occurs faster in data “1” cells than in data “0” cells. This is because the graph of the data "1" cell is to the left of the graph of the data "0" cell, as shown in FIG.

As a result, if more charge can be stored in the floating body region 18 which is a data “1” cell during the write operation, it will have a better sensing margin.

Additionally, the average free path of holes between the base and the collector / drain (C / D) may be longer than the average free path of FIG. 1A. Accordingly, impact ionization for avalanche generation can occur more quickly. As a result, more charge can be stored in data “1” cells. In an embodiment, the impurity concentration of the emitter / source (E / S) may be higher than the impurity concentration of the collector / drain (C / D).

As shown in FIG. 15C, a buffer region 24 may be formed between the floating body region 18 and the collector / drain (C / D) to improve multiplication and avalanche occurrence. In an embodiment, the buffer region 24 is not provided between the floating body region 18 and the emitter / source E / S. In an embodiment, the impurity concentration of the buffer region 24 may be lower than the impurity concentration of the collector / drain (C / D) and / or floating body region 18. In an embodiment, intrinsic semiconductor may be used as buffer region 24. In an embodiment, the buffer region 24 may have the same height as the adjacent second node 16. In an embodiment, the buffer region 24 may cover all of the boundaries of the adjacent second node 16. In an embodiment, the buffer region 24 is in contact with the insulating layer 12.

In an embodiment, buffer region 24 increases the average free path of electrons from the base to the collector / drain (C / D). By increasing the average free path, impact ionization for avalanche generation can be improved. Thus, more charge can be stored in the data “1” cell.

In an embodiment, the impurity concentration of the emitter / source (E / S) may be higher than the impurity concentration of the collector / drain (C / D). As shown in FIG. 15C, an auxiliary body region 26 is provided to increase the electron injection efficiency from the emitter / source (E / S) to the floating body region 18. In an embodiment, the impurity concentration of the auxiliary body region 26 may be lower than the impurity concentration of the floating body region 18. In an embodiment, the floating body region 18 can be longer than the secondary body region 26. In an embodiment, the secondary body region 26 is in contact with the emitter / source E / S. In an embodiment, the auxiliary body region 26 allows more holes to be injected into the floating body region 18 and to be obtained at the base and collector / drain (C / D), thus more effective bipolar junction transistor operation This can happen. In an embodiment, the impurity concentration of the emitter / source (E / S) is higher than the impurity concentration of the collector / drain (C / D) and / or base.

The vertical memory cells may be implemented without increasing the layout of the buffer area 24 and the auxiliary body area 26. This is because the buffer region 24 and the auxiliary body region 26 are formed in the vertical direction as shown in Figs. 13B and 14B.

As shown in FIGS. 11A and 14B, the boundary between the regions may have any shape.

In an embodiment, the vertical memory cell may have the features of FIG. 15C, and the vertical memory cell may have an SOI substrate or a general substrate as shown in FIG. 14B.

FIG. 16A illustrates a plan view of a memory cell structure in accordance with an embodiment of the present invention. As shown in FIG. 16A, the memory cell structure may include a first node 14 (eg, emitter / source (E / S)). ), Second node 16 (e.g., collector / drain (C / D)), floating body region 18, word line 21, extended body region 27, first contact 30, Second contact 32, source line 34, and / or bit line 36. In an embodiment, the extended body region 27 may be disposed under the word line 21 and extend from one side of the floating body region 18 to be used as an additional charge accumulation region. In an embodiment, the extended body region 27 may improve the charge retention capability of the capacitorless memory.

16B is a cross-sectional view of the memory cell cut along the line II ′ of FIG. 16A. As shown in FIG. 16B, the memory cell structure includes a substrate 10, an insulating layer 12, and a first node (eg For example, it may include an emitter / source (E / S), a second node 16 (eg, collector / drain (C / D)), and a floating body region 18. The memory cell may further include isolation layers 44 adjacent to the first node 14 and the second node 16. The memory cell includes a gate 21 including a first contact 30 and a source line 34, a second contact 48 and a bit line 36, a gate insulating layer 20 and a gate layer 22, and Insulating layers 42 and 46 may be included. As shown in FIG. 16B, L1 is greater than L2 and the extended body region 27 does not appear in FIG. 16B.

FIG. 16C is a cross-sectional view of the memory cell when cut in the direction II-II 'of FIG. 16A, and FIG. 16C is a substrate 10, an insulating layer 12, a floating body region 18, and an extended body region 27. ), Isolation layers 44, gate 21, insulating layers 42 and 46, and bit line 36, and the extension body region 27 is shown in FIG. 16C as an extension of the floating body region 18. Is shown.

The extended body region 27 of FIGS. 16A-16C may be used in combination with all or some of the features described above in FIGS. 11A-15C.

Additionally, as shown in FIG. 17, a hole reservoir 140 may be formed below the floating body region 18. The hole reservoir 140 may be embedded in the insulating layer 12. The hole reservoir 140 may have a valence band higher than that of silicon (Si). For example, the hole reservoir 140 may include one of Ge, Si-Ge, Al-Sb, and Ga-Sb. Because the valence electron band of the hole reservoir 140 is higher than the valence electron band of silicon, holes can be more easily accumulated in the hole reservoir 140. The hole retainer 140 can be separated from the emitter / source (E / S) and the collector / drain (C / D), so that data retention characteristics can be improved by reducing the junction leakage current. Thus, a capacitorless memory according to an embodiment may have improved data retention characteristics. For further details on the hole reservoir, see US application number 12 / 005,399 filed Dec. 27, 2007 entitled “Capacitorless Dynamic Semiconductor Memory Devices and Methods of Manufacturing the Device”.

In addition, general CMOS technology based on bulk silicon substrates exhibits a critical short channel effect at gate channel lengths shorter than 40 nm. Due to the limitations of general MOS devices, active research is being conducted in the field of Fin Field Effect Transistor (FinFET) devices.

18 illustrates a memory cell structure according to an embodiment of the present invention. The pin field effect transistor memory cell shown in FIG. 18 is fabricated in the insulating layer 12 on the substrate 10. The fin field effect transistor memory cell includes a silicon pattern on an insulating layer 12 having a first node 14, a second node 16, and / or a floating body region 18. The fin field effect transistor memory cell further includes a gate insulating layer 20 and a gate 22. The gate 22 surrounds the floating body region 18, and the gate insulating layer 20 and the gate 22 may contact all surfaces or surfaces of two or more portions of the floating body region 18. As shown in FIG. 18, the gate insulating layer 20 and the gate 22 are in contact with the faces of three portions of the floating body region 18.

In an embodiment, as shown in FIG. 18, there is no overlap between the gate 22 and the first node 14 or the second node 16. That is, the gate length L2 may be shorter than the floating body length L1, as shown in FIG. 11A. In another embodiment, the gate 22 may overlap one or more of the first node 14 and the second node 16.

Similarly, the buffer region 24 and / or auxiliary body region 26 presented in the above embodiments can be used in combination with the fin field effect transistor of FIG. 18.

19 illustrates a memory cell structure according to an embodiment of the present invention, in which the memory cell structure of FIG. 19 has the same structure as that of FIG. 18. However, it is different that the expansion body region 27 is included above the floating body region 18 and below the gate structures 20 and 22. Gate structures 20 and 22 surround floating body region 18 and extended body region 27. Extended body region 27, which functions as an additional charge storage region, may improve the charge retention capability of the memory device. In an embodiment, as shown in FIG. 18, the memory device may include a buffer region 24 and / or an auxiliary body region 26 between the first node 14 and the second node 16.

Although embodiments have been described above, these embodiments can be modified in various ways. Modifications and / or substitutions in conjunction with FIGS. 11A-19 may be applied to the embodiment shown in FIGS. 1A-10. The specification discloses many different embodiments having many different features, and each of these features can be used in various combinations.

20 illustrates a memory system according to an exemplary embodiment of the present invention. As shown in FIG. 20, the memory system includes a memory controller 1800 and a memory device 1802 without a capacitor. In an embodiment, the capacitorless memory device 1802 may be one of the memories described above in FIGS. 4, 7 and 10. In addition, the memory controller 1800 may be included in an integrated circuit, for example, a central processing unit (CPU) or graphics controller that performs other specific functions.

As shown in FIG. 20, the memory controller 1800 provides commands CMD and an address ADDR to the memory device 1802, and the memory controller 1800 and the memory device 1802 store data DATA. Send and receive in both directions.

The memory controller 1800 may include a register 211, and the memory device 1802 may include a register 221. Each of the registers 211 and 221 may store information indicating whether the memory device 1802 operates in a block refresh mode or a partial refresh mode. Also, if memory 1802 is determined to be in partial refresh mode, each of registers 211 and 221 may store the number of source lines and bit lines that are activated at one time in the partial refresh mode.

As shown in FIG. 21, in an embodiment, the capacitorless memory device 1802 is a plurality of capacitorless memory devices 1802, eg, x memory devices 1802 ₁ , for increasing memory capacity. _x may be a memory module including (x is an integer of 1 or more).

In an embodiment, memory module 1804 identifies registers 231, for example, a cascade latency (CL), time tRCD (delay time from RAS to CAS), partial refresh mode, or block refresh mode. EEPROM that stores information, and / or the number of source lines and / or the number of bit lines that are refreshed at one time during a partial refresh operation.

In an embodiment, the memory controller 1800 reads the stored value from the register 231 of the memory module 1804 after the memory system is turned on, and writes the value read into the register 211 of the memory controller 1800. Accordingly, one or more values are written to the registers 221 ₁ to _x of the corresponding memory devices 1802 ₁ to _x of the memory module 1804 using the mode register set (MRS) command. For example, the memory controller 1800 may provide an MRS command to determine one of a block refresh mode and a partial refresh mode, and may provide a refresh command in a refresh operation. When determined as the partial refresh mode, the mode register setting command may include the number of source lines (or bit lines) that must be activated at a time in a refresh operation in the memory devices 1801 ₁ to _x .

The register in the memory controller register 211 and a memory device (1801 ₁ ~ _x) in the _{(1800) (221 1 ~ x} ) may be set as part of the initialization process, which occurs as the memory system is powered up or reset.

FIG. 22A illustrates a general operation timing diagram of a conventional memory system. As shown in FIG. 22A, in accordance with a clock signal CLK, a conventional memory controller generates a row address in order to activate a word line designated according to a row address. In addition to the R-ADDR, an active command ACT may be provided. After the time tRCD, the memory controller 1800 generates a write command WR, a column address C-ADDR, and write data WD, and the memory devices 1801 ₁ to _x have a row address R-ADDR. ) And the write data WR is written to the memory cell designated by the column address C-ADDR. In a read operation from a memory cell connected to a word line activated by the row address R-ADDR, the memory controller 1800 generates a read command RD together with the column address C-ADDR and generates a memory device ( Read data RD is read from 1801 ₁ to _x . If the read command RE is not the same row address, the memory controller 1800 must generate another active command ACT for the read command.

FIG. 22B illustrates an operation timing diagram of the memory system according to FIGS. 20 and 21. As illustrated in FIG. 22B, the memory controller 1800 does not need to generate a word line activation command ACT. Instead, the memory controller 1800 issues a write command WR with an address ADDR comprising a row address specifying the word line to be activated and a column address to select a memory cell without a capacitor connected to the word line to be activated. You can print The memory cell without the capacitor may be the memory cell of the embodiment described above.

In addition, the memory controller 1800 may output the read command RE together with the address ADDR including the row address and the column address without the active command ACT. Accordingly, the memory system according to the embodiment of the present invention does not require the time tRCD as in the conventional memory devices. Thus, it is possible to implement a faster operating system than a conventional memory system. In addition, since the memory controller 1800 outputs the row address and the column address at the same time, the control may be simplified and easy to implement. Conventional memory controllers require separate control to output row addresses and column addresses.

As shown in Fig. 22B, in an embodiment, the memory controller may generate a mode setting register command (MRS) to select one of the block refresh mode and the partial refresh mode, and if the partial refresh mode is selected, the mode setting register. The command MRS may include the number of source lines SL or bit lines BL that are activated at one time during the partial refresh operation. The memory controller 1800 may generate a refresh command REF after the mode register setting command MRS.

The changes and / or substitutions described above in conjunction with FIGS. 20-22B may be applied to the embodiment shown in FIGS. 1A-10 or 11A-19. The specification discloses many embodiments with many different features, each of which may be used in combination.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

1A illustrates a capacitorless memory cell of a horizontal structure in accordance with an embodiment of the present invention.

1B illustrates a memory cell without a capacitor having a vertical structure in accordance with an embodiment of the present invention.

2 shows an equivalent diagram of a memory cell without a capacitor according to an embodiment of the present invention.

3 illustrates a DC characteristic of a memory cell without a capacitor according to an embodiment of the present invention.

4 illustrates a memory device having a separate source line structure in accordance with an embodiment of the present invention.

FIG. 5 is an operation timing diagram for describing an operation of one row of the memory device of FIG. 4.

6 is an operation timing diagram for describing an operation of one cell of the memory device of FIG. 4.

7 illustrates a memory device having a common source line structure according to an embodiment of the present invention.

FIG. 8 is an operation timing diagram for describing an operation of one row of the memory device of FIG. 7.

FIG. 9 is an operation timing diagram for describing an operation of one cell of the memory device of FIG. 7.

Figure 10 shows a memory device of another embodiment of the present invention.

11A and 11B illustrate the structure of a memory cell without a capacitor according to an embodiment of the present invention.

12A and 12B illustrate the structure of a memory cell without a capacitor according to an embodiment of the present invention.

13A and 13B illustrate the structure of a capacitorless memory cell according to an embodiment of the present invention.

14A and 14B illustrate the structure of a memory cell without a capacitor according to an embodiment of the present invention.

15a, b, and c illustrate a structure of a capacitorless memory cell according to an embodiment of the present invention.

16A illustrates a top view of a memory cell structure in accordance with an embodiment of the present invention.

FIG. 16B is a cross-sectional view when cut along the line II ′ of FIG. 16A.

FIG. 16C is a cross-sectional view when cut in the direction II-II ′ of FIG. 16A.

Figure 17 illustrates a cross-sectional view of a memory cell without a capacitor in accordance with an embodiment of the present invention.

18 illustrates a memory cell having a fin field effect transistor structure according to an embodiment of the present invention.

19 illustrates a memory cell having a fin field effect transistor structure according to another embodiment of the present invention.

20 illustrates a memory system according to an embodiment of the present invention.

21 illustrates a memory system according to an embodiment of the present invention.

22A shows an operation timing diagram of a conventional memory system.

22B illustrates an operation timing diagram of a memory system according to an embodiment of the present invention.

Claims (56)

A floating body transistor having a plurality of memory cells, each of the plurality of memory cells having a first node, a second node, and a gate node connected to at least one bit line, at least one source line, and at least one word line, respectively. A memory array having a; And And a controller configured to perform a refresh operation in response to a refresh command by selecting one of the at least one source line and the at least one bit line, If the first data is stored in the memory cell connected to the selected line, the first current caused by the bipolar junction operation flows. 2. The memory device of claim 1, wherein if the second data is stored in the memory cell connected to the selected line, no current caused by the bipolar junction operation flows. The memory device of claim 1, wherein each of the plurality of memory cells includes a floating body region between the first node and the second node. The memory device of claim 1, wherein the floating body region has a floating body length, the gate has a gate length, and the floating body length is shorter than the gate length. The memory device of claim 1, wherein the number of source lines is equal to the number of bit lines. 6. The memory device of claim 5, wherein a difference between the voltage applied to the at least one source line and the at least one bit line and the voltage applied to the at least one word line induces a bipolar junction operation. . The memory device of claim 1, wherein the controller comprises a row controller for controlling the at least one source line and the at least one word line, and a column controller for controlling the at least one bit line. . The memory device of claim 1, wherein the number of source lines is smaller than the number of bit lines. The method of claim 8, wherein the memory cells adjacent in the bit line direction share one of the at least one source line, and the controller performs the refresh operation by additionally controlling the at least one word line. Memory device. A floating body transistor having a plurality of memory cells, each of the plurality of memory cells having a first node, a second node, and a gate node connected to at least one bit line, at least one source line, and at least one word line, respectively. A memory array having a; And The write operation is performed by applying a bit line write voltage to the at least one bit line, applying a source line write voltage to at least one source line, and applying a word line write voltage to at least one word line according to data information. And a control unit for controlling to perform the memory device. The memory device of claim 10, wherein the source line write voltage is greater than the bit line write voltage and the word line write voltage. 12. The memory device of claim 11, wherein a difference between the source line write voltage and the bit line write voltage with respect to the word line write voltage induces a bipolar junction operation according to the data information. The method of claim 10, wherein the control unit applies a word line holding voltage to at least one word line, applies a source line holding voltage to at least one source line, and then holds the bit line as at least one bit line. And performing a write operation by applying a voltage to the memory device. The memory device of claim 10, wherein the controller performs a write operation, a read operation, and a refresh operation by applying at least two voltage levels to at least one word line. The memory device of claim 10, wherein the number of source lines is equal to the number of word lines. The memory device of claim 10, wherein the number of the source lines is smaller than the number of the word lines. A substrate, an insulator, and a silicon layer, the silicon layer having impurity implanted first and second nodes, a floating body region, and a buffer region between one of the first and second nodes and the floating body region. Wherein the buffer region has an impurity concentration lower than that of the adjacent node or the floating body region, and the buffer region comprises: silicon on insulator covering all boundary portions of one of the first and second nodes; And And a gate structure over the silicon layer. 18. The memory cell structure of claim 17, wherein the buffer region has the same height as one of the first and second nodes. 18. The memory cell structure of claim 17, wherein the buffer region is in contact with the insulator. A substrate, an insulator, and a silicon layer, said silicon layer having a doped implanted first and second nodes, a floating body region having a floating body length between said first and second nodes, and said first layer And a buffer region between one of the second nodes and the floating body region, wherein the buffer region has an impurity concentration lower than an impurity concentration of the adjacent node or the floating body region; And A gate structure having a gate length on the silicon layer, And the floating body length is greater than the gate length. A substrate, an insulator, and a silicon layer, the silicon layer having an impurity implanted emitter / source and collector / drain, a floating body region, and an auxiliary body region between the emitter / source and the floating body region; Silicon on an insulator, wherein the auxiliary body region has an impurity concentration lower than that of the floating body region; And And a gate structure over the silicon layer. 22. The memory cell structure of claim 21, wherein said auxiliary body region covers said emitter / source. 22. The memory cell structure of claim 21, wherein the floating body region is longer than the auxiliary body region. A silicon on insulator having a substrate, an insulator, and a silicon layer, said silicon layer having impurity implanted first and second nodes, a floating body region, and an extended body region adjacent said floating body region; And And a gate structure over the silicon layer. 25. The memory cell structure of claim 24, wherein the extended body region extends in a direction orthogonal to the direction of the first and second nodes and the floating body region. 25. The memory cell structure of claim 24, wherein the extension body region extends downward in the gate structure. An insulating layer on the substrate; A silicon pattern formed on the insulating layer, the silicon pattern including a first node, a second node, and a floating body region; And A gate surrounding the floating body region, Wherein the length of the gate is shorter than the length of the floating body region, and a difference between voltages applied to the first node and the second node with respect to a voltage applied to the gate causes a bipolar junction operation. Memory cell structure. 28. The method of claim 27, further comprising a buffer region between the floating body region and one of the first node and the second node, wherein the buffer region is an impurity of one of the first node and the second node. A memory cell structure, characterized in that it has an impurity concentration lower than the concentration. An insulating layer on the substrate; A silicon pattern formed on the insulating layer and having a first node, a second node, and a floating body region; An extended body region on the floating body region; And And a gate structure surrounding the floating body region and the extended body region. 30. The memory cell structure of claim 29, wherein the gate length is longer than the length of the floating body region. 30. The method of claim 29, further comprising a buffer region between the floating body region and one of the first and second nodes, wherein the buffer region is less than an impurity concentration of one of the first and second nodes. A memory cell structure characterized by having a low impurity concentration. Provide a mode register setting instruction for specifying one of a block refresh operation and a partial refresh operation, And a plurality of capacitorless memory cells that provide a refresh command for the refresh operation. 33. The plurality of capacitorless memory cells of claim 32, wherein the mode register setting command additionally specifies the number of lines activated in the memory device when the partial refresh operation is determined. To control a memory device. 33. The method of claim 32, wherein the method is Provide a write command to the memory device without applying a row enable command in advance; And a plurality of capacitorless memory cells further comprising providing write data, a first row address, and a first column address to the memory device. The method of claim 34, wherein the method is Provide a read command to the memory device without applying a word line enable command, And a plurality of capacitorless memory cells further comprising receiving read data from the memory device. And a first register for storing a mode register setting command for selecting one of a block refresh and a partial refresh of the memory device. 37. The memory of claim 36, wherein the memory controller is And a second register for storing information about the number of at least one source line and the bit lines activated in the memory device. And a first register for storing information relating to a refresh operation for selecting one of block refresh and partial refresh. 39. The memory device of claim 38, wherein the memory device is And a second register for storing information about the number of at least one source line and the bit lines activated at the partial refresh. A silicon on an insulator comprising a substrate, an insulator, and a semiconductor pattern, the semiconductor pattern comprising a first node, a second node, and a floating body region; And A gate on the floating body region, The length of the gate is shorter than the length of the floating body region, and the difference between the voltages applied to the first node and the second node with respect to the voltage applied to the gate causes a bipolar junction operation. Memory cell structure. 41. The memory cell structure of claim 40, wherein the gate does not overlap the first node and the second node. 41. The memory cell structure of claim 40, wherein the gate does not overlap one of the first node and the second node. 43. The memory cell structure of claim 42, wherein one of the first node and the second node receives a higher voltage for the bipolar junction operation. A memory array including a plurality of memory cells, each of the plurality of memory cells including a first node, a second node, and a gate connected to each of at least one bit line, at least one source line, and at least one word line ; And A read operation is performed by selecting the at least one source line and not selecting at least one word line, and if the first data is stored in a memory cell connected to the selected source line, by a bipolar junction operation. And a first current to be caused to flow. 45. The memory device of claim 44, wherein if the second data is stored in a memory cell connected to the selected memory cell, the second current caused by the bipolar junction operation does not flow. 45. The memory device of claim 44, wherein the controller applies a source line read voltage to the selected at least one source line, and applies a word line sustain voltage to at least one word line. 47. The memory device of claim 46, wherein the controller performs a write operation by selecting the at least one source line, the at least one bit line, and the at least one word line. 48. The memory device of claim 47, wherein the controller applies a source line write voltage to the selected at least one source line and applies a word line write voltage to the selected at least one word line during a write operation. . 49. The memory device of claim 48, wherein the source line read voltage is equal to the source line write voltage. 48. The memory device of claim 47, wherein the controller selects at least two source lines and performs the refresh operation by not selecting the at least one word line. 51. The memory device of claim 50, wherein the controller applies a source line refresh voltage to the selected at least one source line and applies the word line sustain voltage to the at least one word line during a refresh operation. . 53. The memory device of claim 51, wherein the source line read voltage is the same as the source line write voltage and the source line refresh voltage. The memory device of claim 51, wherein the controller is further configured to perform the write operation, the read operation, and the refresh operation by applying a word line sustain voltage and a word line write voltage to at least one word line. 45. The memory device of claim 44, wherein the memory device is And a sensing unit which is one of a voltage sense amplifier and a current sense amplifier sensing the first and second currents. 45. The method of claim 44, wherein each of the plurality of memory cells has a floating body region between the first node and the second node, the floating body region has a floating body length, and the gate has a gate length, And the gate length is shorter than the floating body length. 55. The memory device of claim 54, wherein the number of source lines and the number of bit lines are equal.

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