KR20090002635A - Nonvolatile Memory Device and Manufacturing Method Thereof - Google Patents

Abstract

The present invention is to provide a non-volatile memory device and a method of manufacturing the same to create an environment to minimize the thickness of the dielectric film to improve the coupling ratio (coupling ratio) of the device, the present invention for this purpose A tunneling insulating film formed on the substrate, a floating gate formed on the tunneling insulating film, a barrier layer having a different conductivity type from the floating gate, a dielectric film formed on the barrier layer, and a control gate formed on the dielectric film. A nonvolatile memory device is provided.

Description

A nonvolatile memory device and a method of manufacturing the same {A NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME}

TECHNICAL FIELD The present invention relates to semiconductor manufacturing technology, and more particularly, to a nonvolatile memory device and a method of manufacturing the same.

Unlike DRAM (Dynamic Random Access Memory) devices, flash memory devices, which are nonvolatile memory devices, do not require capacitor devices, but require charge storage space to read and write data. In order to perform the data read and write operation, the entire capacitance including the capacitance formed in the tunneling insulating film and a dielectric film called IPD (Inter Poly Dielectric) or IPO (Inter Poly Oxide), that is, between the floating gate and the control gate, are performed. The ratio between the capacitances of the interposed dielectric films must be satisfied.

However, as the device is highly integrated, there is a limit in securing the capacitance when a dielectric film is formed of a laminated structure (oxide film / nitride film / oxide film) in which an oxide film, a nitride film, and an oxide film are stacked. Accordingly, efforts have been made to reduce the thickness of the dielectric film, particularly the thickness of the lowermost layer oxide film, in order to increase the capacitance. However, in this case, direct tunneling occurs to deteriorate leakage current characteristics.

Accordingly, the present invention has been proposed to solve the problems of the prior art, and a nonvolatile memory device capable of improving the coupling ratio of the device by forming an environment to minimize the thickness of the dielectric film and its manufacture The purpose is to provide a method.

According to an aspect of the present invention, there is provided a tunneling insulating film formed on a substrate, a floating gate formed on the tunneling insulating film, a barrier layer having a different conductivity type from the floating gate, and the barrier layer. A nonvolatile memory device comprising a dielectric film formed on and a control gate formed on the dielectric film.

According to another aspect of the present invention, there is provided a method of forming a tunneling insulating film on a substrate, forming a floating gate on the tunneling insulating film, and forming the floating gate on the floating gate. It provides a method of manufacturing a nonvolatile memory device comprising the steps of forming a barrier layer having different conductivity types, forming a dielectric film on the barrier layer, and forming a control gate on the dielectric film. .

As described above, according to the present invention, by forming a barrier layer between the floating gate and the dielectric film to increase the gap between the conduction band of the dielectric film and the floating gate, it is possible to improve the leakage current characteristics due to the decrease in the dielectric film thickness. . In addition, as the dielectric film thickness decreases, the coupling ratio can be increased to improve the operation reliability of the device.

Hereinafter, with reference to the accompanying drawings, the most preferred embodiment of the present invention will be described. In addition, in the drawings, the thicknesses and spacings of layers and regions are exaggerated for ease of explanation and clarity, and when referred to as being on or above another layer or substrate, it is different. It may be formed directly on the layer or the substrate, or a third layer may be interposed therebetween. In addition, the parts denoted by the same reference numerals throughout the specification represent the same layer, and when the reference numerals include the English, it means that the same layer is partially modified through an etching or polishing process.

Example

1 is a cross-sectional view illustrating a nonvolatile memory device according to an embodiment of the present invention. For convenience of description, a memory cell of a NAND flash memory device manufactured through a self-aligned-shallow trench isolation (SA-STI) process is illustrated as an example.

Referring to FIG. 1, a nonvolatile memory device according to an exemplary embodiment of the present invention has a type opposite to that of an impurity ion doped in a floating gate 105A between the floating gate 105A and the dielectric film 107. And a barrier layer 106 doped with impurity ions having a conductivity type of.

The barrier layer 106 is floated by increasing the gap between the dielectric film 107, particularly the oxide film 107-1 and the conduction band of the floating gate 105A, as shown in FIG. Electrons e of the gate 105A are blocked from being tunneled through the oxide film 107-1.

In other words, as described above, when the thickness of the dielectric film is reduced to increase the capacitance, the gap between the dielectric film and the conduction band of the floating gate decreases in proportion to the decrease in the dielectric film thickness. In this state, applying a high voltage of approximately 20V or more to the control gate for the write operation causes direct tunneling through which the electrons in the floating gate pass through the thinned conduction band, thereby deteriorating leakage current characteristics.

Therefore, in the embodiment of the present invention, the barrier layer 106 is formed between the floating gate 105A and the dielectric film 107, thereby increasing the gap between the conduction bands of the dielectric film 107 and the floating gate 105A. The gap between the conduction bands is compensated for by decreasing the thickness of the dielectric film 107.

Hereinafter, a method of manufacturing a nonvolatile memory device according to an exemplary embodiment of the present invention shown in FIG. 1 will be described with reference to FIGS. 2A to 2D. 2A to 2D are cross-sectional views of the process.

 First, as shown in FIG. 2A, triple n-type wells (not shown) are formed in a semiconductor substrate 100, for example, a p-type substrate, and then p-type wells ( Not shown).

Subsequently, an ion implantation process for adjusting the threshold voltage is performed in the channel region in the p-well.

Subsequently, a tunneling insulating film 101 is formed on the substrate 100 to substantially perform FN tunneling. At this time, the tunneling insulation film 101 is an oxide film, a silicon oxide film (SiO ₂₎ after forming, or forming a silicon oxide film (SiO ₂₎ of nitrogen, for example by carrying out the heat treatment process using a N ₂ gas of silicon oxide (SiO ₂₎ A nitride layer may be formed at the interface between the substrate 200 and the substrate 200. The manufacturing method may be a dry oxidation, a wet oxidation process or an oxidation process using radical ions. However, in view of characteristics, it is preferable to perform a dry oxidation and wet oxidation process instead of an oxidation process using radical ions. On the other hand, the heat treatment process using nitrogen gas can be carried out using a furnace (furnace) equipment. The tunneling insulating film 101 may be formed to a thickness of about 50 ~ 100Å.

Subsequently, the first conductive film 102 for floating gate is formed on the tunneling insulating film 101. In this case, the first conductive film 102 may be formed of a material having conductivity, and may be formed of any one material selected from a polysilicon film, a transition metal, a rare earth metal, or an alloy film containing these materials. For example, the polysilicon film may be an un-doped polysilicon film that is not doped with impurity ions or a doped polysilicon film that is doped with impurity ions, but may be impurity doped by a subsequent heat treatment process. In order to prevent ions from diffusing into the tunneling insulating film 101 and forming trap sites in the tunneling insulating film 101, it is preferable to form an undoped polycrystalline silicon film. The undoped polysilicon film is formed by a Low Pressure Chemical Vapor Deposition (LPCVD) method, wherein silane (SiH ₄ ) is used as the source gas. In addition, as a transition metal, iron (Fe), cobalt (Co), tungsten (W), nickel (Ni), palladium (Pd), platinum (Pt), molybdenum (Mo) or titanium (Ti) and the like are used, Rare earth metals include erbium (Er), ytterium (Yb), samarium (Sm), yttrium (Y), lanthanum (La), cerium (Ce), terbium (Tb), dysprosium (Dy), holmium (Ho), Tolium (Tm), lutetium (Lu), and the like.

Subsequently, a device isolation film 103 to be formed through a subsequent process is formed in a trench structure, and when a hard mask is applied as an etching mask, a buffer film (not shown) is formed on the first conductive film 102. You may. In this case, the buffer layer (not shown) is to prevent damage to the first conductive layer 102 during the hard mask deposition process and the removal process, it is preferably formed of a material having a high etching selectivity with the hard mask. For example, when the hard mask is formed of a nitride film, for example, a silicon nitride film (Si ₃ N ₄ ), it is formed of a silicon oxide film (SiO ₂ ).

Subsequently, after forming a hard mask (not shown) on the buffer film, the hard mask, the buffer film, the first conductive film 102, the tunneling insulating film 101 and the substrate 100 are partially etched to form trenches (not shown). ).

Subsequently, an insulating film for an isolation layer is formed to fill the trench, and then a planarization process, for example, chemical mechanical polishing (hereinafter, referred to as CMP), is performed to form an isolation layer 103 inside the trench. do. In this case, the device isolation layer 103 may be formed of a film (hereinafter referred to as HDP) formed of high density plasma (High Density Plasma) having excellent embedding characteristics even at a high aspect ratio, or SOD (Spin) formed by a spin coating method with HDP. On Dielectric) film can be formed into a laminated structure in which the films are laminated. In this case, a PSZ (polisilazane) film may be used as the SOD film.

Subsequently, as illustrated in FIG. 2B, a second conductive film 104 for floating gate is formed on the first conductive film 102. In this case, the second conductive film 104 is formed to have a larger line width than the first conductive film 102 and is formed of a doped polycrystalline silicon film doped with impurity ions. For example, the doped polysilicon film is formed by LPCVD method, in which a silane (SiH ₄ ) gas is used as the source gas, and phosphine (PH ₃ ), fluorine trichloride (BCl ₃ ) or giborane (B ₂ H) is used as the doping gas. ₆ ) Use gas.

Subsequently, as shown in FIG. 2C, a barrier layer 106 doped with impurity ions having a different conductivity type from the second conductive film 104A is formed on the second conductive film 104A. At this time, the barrier layer 106 is formed by a counter-doping process. Here, the counter doping step means a step of implanting impurities of a type opposite to the conductivity type of the impurity ion for the electrode. For example, the counter-doping process is performed in the case where the second conductive film 104A is doped with n-type impurity ions such as phosphorus (P) or arsenic (As), which is a Group 5 material, on the periodic table. p-type impurity ions are used. More specifically, when the second conductive layer 104 is doped with phosphorus (P), boron (B), boron fluoride (BF), boron difluoride (BF ₂ ), or a mixture thereof is used, wherein the ion implantation amount ( dose) is 1 × 10 ¹² to 5 × 10 ¹² ions / cm ² , and ion implantation energy is 5 to 10 KeV. In addition, the ion implantation angle (tilt) is 0-10 degrees or 15 degrees.

Subsequently, as illustrated in FIG. 2D, the dielectric film 107 is formed along the stepped surface of the substrate 100 including the barrier layer 106. In this case, the dielectric film 107 is formed in a structure in which an oxide film-nitride film-oxide film, for example, a silicon oxide film (SiO ₂ ) -silicon nitride film (Si ₃ N ₄ ) -silicon oxide film (SiO ₂ ) is laminated or has a dielectric constant of silicon oxide film ( It may be formed of an aluminum oxide film (Al ₂ O ₃ ), a zirconium oxide film (ZrO ₂ ), a hafnium oxide film (HfO ₂ ), or a laminate thereof, which is 3.9 or more higher than SiO ₂ ), or a mixed film in which these are mixed.

Next, a control gate conductive film (hereinafter referred to as a third conductive film) is formed on the dielectric film 107. In this case, the third conductive film may be formed of any one conductive film selected from a doped polycrystalline silicon film, a transition metal, a rare earth metal, or an alloy film containing these materials.

Subsequently, on the third conductive film, a metal nitride, a metal silicide layer, or a laminated film in which these layers are laminated may be further formed to lower the specific resistance. For example, a titanium nitride layer (TiN), a tantalum nitride layer (TaN), or a tungsten nitride layer (WN) is used as the metal nitride, and a titanium silicide layer (TiSi ₂ ), a tungsten silicide layer (Wsi), or the like is used as the metal silicide layer. do.

Subsequently, although not illustrated, the third conductive film 108, the dielectric film 107, the barrier layer 106, the second conductive film 104A, and the first conductive film 102 are etched to form a memory cell having a desired line width. To form a gate electrode.

Since the process is the same as the general process, a description thereof will be omitted.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In particular, the embodiment of the present invention has been described using a NAND flash memory device to which the SA-STI process is applied as an example, but for convenience of description, all non-volatile memory devices including a NOA flash memory device, or a stack on a plane The structure may be applied to a structure formed of a structure, a self-aligned-floating gate (SAFG), and a structure to which an advanced self-aligned-sti (ASA-STI) process is applied. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a cross-sectional view illustrating a nonvolatile memory device according to an embodiment of the present invention.

2A through 2D are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention.

3 is a conceptual diagram illustrating the function of the barrier layer according to an embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

100 semiconductor substrate 101 tunneling insulating film

102: first conductive film 103: device isolation film

104, 104A: second conductive film 105, 105A: floating gate

107: dielectric film 107-1, 107-3: oxide film

107-2: Nitride film 108: Third conductive film

Claims (10)

A tunneling insulating film formed on the substrate; A floating gate formed on the tunneling insulating layer; A barrier layer formed on the floating gate to have a different conductivity type from the floating gate; A dielectric film formed on the barrier layer; And A control gate formed on the dielectric layer Nonvolatile memory device comprising a. The method of claim 1, And the barrier layer is formed of a doped-polycrystalline silicon film implanted with impurity ions having a conductivity type opposite to that of the doped impurity ions doped into the floating gate. The method of claim 1, And the barrier layer is doped with n-type or p-type impurity ions. Forming a tunneling insulating film on the substrate; Forming a floating gate on the tunneling insulating film; Forming a barrier layer on the floating gate, the barrier layer having a different conductivity type from the floating gate; Forming a dielectric film on the barrier layer; And Forming a control gate on the dielectric layer Method of manufacturing a nonvolatile memory device comprising a. The method of claim 4, wherein The forming of the barrier layer may be performed by a counter doping process. The method of claim 5, wherein The counter doping process is a method of manufacturing a nonvolatile memory device using n-type or p-type impurity ions. The method of claim 5, wherein The counter doping process is a method of manufacturing a nonvolatile memory device using any one selected from boron (B), boron fluoride (BF), boron difluoride (BF ₂ ) or a mixture thereof. The method of claim 7, wherein In the counter doping step, the ion implantation amount is 1 × 10 ¹² to 5 × 10 ¹² ions / cm ² , and the ion implantation energy is 5 to 10 KeV. The method of claim 7, wherein The counter doping step is a method of manufacturing a non-volatile memory device to perform the ion implantation angle of 1 ~ 10 ° or 15 °. The method of claim 4, wherein Forming the floating gate, Forming an undoped polysilicon film on the tunneling insulating film; And Forming a doped polysilicon film on the undoped polysilicon film Method of manufacturing a nonvolatile memory device comprising a.

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