KR20080104461A - Manufacturing Method of Array Substrate and Array Substrate - Google Patents

Abstract

Disclosed are an array substrate manufacturing method and an array substrate having improved current drive capability. A method of manufacturing an array substrate includes a first passivation method on a base substrate on which a gate electrode, a semiconductor pattern formed on the gate electrode, an ohmic contact pattern formed on the semiconductor pattern, and a source electrode and a drain electrode disposed spaced apart from each other on the ohmic contact pattern are formed. Forming a layer, etching the first passivation layer to form a first residual pattern surrounding the source electrode and a second residual pattern surrounding the drain electrode, the first and second residual patterns being exposed by Etching the ohmic contact pattern to expose the semiconductor pattern, forming a second passivation layer on the exposed base substrate, and forming a pixel electrode electrically connected to the drain electrode on the second passivation layer. Steps. Accordingly, the current driving capability can be improved by minimizing the channel length.

Description

Method for manufacturing array substrate and array substrate {METHOD OF MANUFACTURING ARRAY SUBSTRATE AND ARRAY SUBSTRATE}

1 to 9 are process diagrams illustrating a method of manufacturing an array substrate according to an exemplary embodiment of the present invention.

10A through 10D are flowcharts illustrating a method of manufacturing an array substrate, according to another exemplary embodiment.

<Explanation of symbols for the main parts of the drawings>

110: base substrate 122, 124: first and second gate metal layers

142a: semiconductor layer 144a: ohmic contact layer

152, 154 and 156: first, second and third source metal layers

160: photo pattern 142b: semiconductor pattern

144b: ohmic contact patterns 146a and 146b: first and second ohmic contact portions

170: first passivation layer 172: first residual pattern

174: second residual pattern 180: second passivation layer

CNT: contact hole PE: pixel electrode

The present invention relates to a method for manufacturing an array substrate and an array substrate, and more particularly, to a method for manufacturing an array substrate and an array substrate with improved reliability of a product.

In general, a liquid crystal display panel includes a TFT substrate on which thin film transistors (hereinafter, referred to as TFTs), which are switching elements for driving respective pixel regions, a counter substrate facing the TFT substrate, the TFT substrate, It includes a liquid crystal layer formed interposed between the opposite substrate. The liquid crystal display panel displays an image by applying a voltage to the liquid crystal layer to control light transmittance.

On the other hand, in order to improve the reliability of a product, it is important to form a fine pattern TFT uniformly in manufacture of a TFT substrate. By using photolithography, which is common in the manufacture of TFTs, it is possible to easily implement a channel of a TFT having a thickness of less than or equal to a small area substrate such as a silicon wafer.

On the other hand, in the manufacture of a large-area TFT substrate according to the demand for medium-sized and large-sized liquid crystal display panels, a TFT having a large current driving capability is required to solve the RC time delay as the TFT substrate becomes larger. In order to improve the current driving capability of the TFT, for example, reducing the channel length of the TFT while maintaining the channel width of the TFT is a kickback voltage caused by an increase in the aperture ratio and parasitic capacitance. Can be reduced.

However, as the area of the TFT substrate increases in size, there is a limit in manufacturing the channel length of the TFT by minimizing the channel length using an existing equipment, for example, an exposure machine, for general photolithography.

Accordingly, the technical problem of the present invention was conceived in this respect, and an object of the present invention is to provide a method of manufacturing an array substrate with a minimum channel length.

Another object of the present invention is to provide an array substrate with a minimum channel length.

An array substrate manufacturing method according to an embodiment for realizing the object of the present invention is a gate electrode, a semiconductor pattern formed on the gate electrode, an ohmic contact pattern formed on the semiconductor pattern, spaced apart from each other on the ohmic contact pattern Forming a first passivation layer on the base substrate on which the source electrode and the drain electrode are disposed, wherein the first passivation layer is etched to surround the source electrode, and the first electrode is disposed on the drain electrode. Forming a residual pattern, etching the ohmic contact pattern exposed by the first and second residual patterns to expose the semiconductor pattern, and forming a second passivation layer on the base substrate to which the semiconductor pattern is exposed. Forming and electrically contacting the drain electrode on the second passivation layer; And forming a pole.

According to another aspect of the present invention, an array substrate includes a gate electrode formed on a base substrate, a semiconductor pattern formed on the gate electrode, a source electrode and a drain spaced apart from each other on the semiconductor pattern. An electrode, a first residual pattern surrounding the source electrode and a second residual pattern surrounding the drain electrode, a first ohmic contact portion disposed between the source electrode and the first residual pattern and the semiconductor pattern; And a pixel electrode spaced apart from the first ohmic contact part to expose the semiconductor pattern, the second electrode contact part disposed between the drain electrode, the second residual pattern and the semiconductor pattern, and the pixel electrode electrically connected to the drain electrode. .

According to the method of manufacturing the array substrate and the array substrate, the first and second ohmic contact portions are formed using the residual patterns formed by etching the first passivation layer, thereby minimizing the channel length to improve the current driving capability. You can.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 to 9 are process diagrams illustrating a method of manufacturing an array substrate according to an exemplary embodiment of the present invention.

1 is a plan view of a base substrate on which a gate wiring, a gate electrode, and a storage electrode are formed, and FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1.

Referring to FIG. 1, gate lines GLn, GLn + 1, and n are natural numbers, the gate electrode GE, and the storage electrode STE on the base substrate 110 including the pixel region P. Referring to FIG. Form.

The gate lines GLn and GLn + 1 extend in the first direction D1 of the base substrate 110 and are disposed in parallel to each other in a second direction D2 different from the first direction D1. The first direction D1 and the second direction D2 may be perpendicular to each other, for example. The gate electrode GE is connected to one gate line GLn and is formed in the pixel area P, and the storage electrode STE is formed in another gate adjacent to the gate line GLn in the second direction D2. The pixel region P is connected to the line GLn + 1 to form the gate electrode GE.

The gate electrode GE formed in the pixel region P is a control electrode of a thin film transistor (TFT), which is a switching element, and the storage electrode STE is sheared together with a pixel electrode (not shown) to be formed later. A gate storage capacitor Cst is defined. In contrast, the storage electrode STE may be connected to a separate common wire (not shown).

Referring to FIG. 2, the gate lines GLn and GLn + 1, the gate electrode GE, and the storage electrode STE shown in FIG. 1 may include gate metal layers (not shown) formed on the base substrate 110. It is formed by patterning using the first mask (MASK1).

Specifically, the gate metal layers are formed on the base substrate 110. The gate metal layers may include two or more metal layers having different physical properties. The gate metal layers may include, for example, a first gate metal layer 122 including molybdenum and a second gate metal layer 124 including aluminum. Alternatively, a single metal layer (not shown) may be formed on the base substrate 110 to form gate lines GLn and GLn + 1, a gate electrode GE, and a storage electrode STE. The gate metal layers may be patterned into the gate lines GLn and GLn + 1, the gate electrode GE, and the storage electrode STE through a conventional photolithography process.

3 is a plan view of a base substrate on which a data line, a source pattern, a semiconductor pattern, and a first ohmic contact pattern are formed, and FIG. 4 is a cross-sectional view taken along the line II ′ of FIG. 3.

Referring to FIG. 3, the data lines DLm, DLm + 1, and m are natural numbers on the base substrate 110 on which the gate lines GLn and GLn + 1 and the gate electrode GE are formed, and each data line. A source pattern SP connected to the DLm is formed.

The data lines DLm and DLm + 1 extend in the second direction D2 and are arranged in parallel in parallel in the first direction D1. The data lines DLm and DLm + 1 cross the gate lines GLn and GLn + 1.

The source pattern SP may be connected to each data line DLm to overlap the gate electrode GE, and a portion of the source pattern SP may extend from the region overlapping the gate electrode GE to the pixel region P. The source pattern SP is later etched to form a source electrode (not shown) and a drain electrode (not shown) which are signal electrodes of the thin film transistor TFT.

Referring to FIG. 4A, the gate insulating layer 130, the semiconductor layer 142a, and the ohmic contact layer 144a are formed on the base substrate 110 on which the gate lines GLn and GLn + 1 and the gate electrode GE are formed. The source metal layer 150 is sequentially formed.

The gate insulating layer 130 is formed on the base substrate 110 on which the gate lines GLn and GLn + 1 and the gate electrode GE are formed. The gate insulating layer 130 may be formed of, for example, silicon nitride (SiNx, 0 <x <1).

The semiconductor layer 142a is formed on the base substrate 110 on which the gate insulating layer 130 is formed. The semiconductor layer 142a may be formed of, for example, amorphous silicon (a-Si).

An ohmic contact layer 144a is formed on the base substrate 110 on which the semiconductor layer 142a is formed. The ohmic contact layer 144a may be formed of, for example, amorphous silicon (n + a-Si) doped with a high concentration of n-type impurities.

The source metal layer 150 is formed on the base substrate 110 on which the ohmic contact layer 144a is formed. The source metal layer 150 may include, for example, a first source metal layer 142 including molybdenum, a second source metal layer 144 including aluminum, and a third source metal layer including molybdenum.

The photo pattern 160a is formed on the base substrate 110 on which the source metal layer 150 is formed. In the subsequent process, the photo pattern 160a includes a first thickness portion 162 having a first thickness a in a region where a source electrode and a drain electrode are to be formed, and regions where the source electrode and the drain electrode are to be formed. And a second thickness portion 164 formed at a second thickness b in the region therebetween. The first thickness a of the first thickness portion 162 has a larger value than the second thickness b of the second thickness portion 164.

The photo pattern 160a forms a photoresist layer (not shown) on the source metal layer 150, and after disposing a second mask MASK2 on the base substrate 110 on which the photoresist layer is formed, the photoresist. The layer may be exposed and developed to form. The photoresist layer may be formed of, for example, a negative photoresist material that is cured and remains when light is irradiated and is removed by a developer when light is blocked. The second mask MASK2 includes a light transmitting unit 210, a diffraction unit 220, and a light blocking unit 230. The first thickness portion 162 is formed on the light source 210 and the source metal layer 150, and the second thickness portion 164 is formed on the source metal layer 150 corresponding to the diffractive portion. Light blocking portion 230 The photoresist layer on the source metal layer 150 corresponding to the light blocking portion is removed.

Referring to FIG. 4B, the source metal layer 150, the ohmic contact layer 144a, and the semiconductor layer 142a are sequentially etched using the photo pattern 160a, and the source pattern SP, the ohmic contact pattern 144b, and the like. The semiconductor pattern 142b is formed. The source pattern SP, the ohmic contact pattern 144b, and the semiconductor pattern 142b may be formed to have substantially the same pattern by etching the photo pattern 160a using a mask.

Next, the second thickness portion 164 of the photo pattern 160a formed on the source pattern SP is removed. A portion of the source pattern SP is exposed through the remaining photo pattern 160b after the second thickness portion 164 is removed. The second thickness portion 164 may be removed by, for example, ashing using oxygen gas.

5 is a plan view of a base substrate on which a source electrode, a drain electrode and a channel are formed, FIG. 6 is a cross-sectional view illustrating a step of forming a source electrode and a drain electrode, and FIGS. 7A to 7D are cross-sectional views illustrating steps of forming a channel. .

5 and 6, the source electrode SE and the drain electrode DE spaced apart from the source electrode SE are formed using the remaining photo pattern 160b and the source pattern SP. The source pattern SP exposed through the remaining photo pattern 160b is etched to form a source electrode SE and a drain electrode DE.

A portion of the source pattern SP is etched to expose the first sidewall SW1, which is an end of the source electrode SE. The first sidewall SW1 is an end portion facing the drain electrode DE of the source electrode SE. The second sidewall SW2, which is an end of the drain electrode DE and faces the first sidewall SW1, is exposed. Subsequently, the remaining photo pattern 160b is removed from the base substrate 110.

Referring to FIG. 7A, a first passivation layer 170 is formed on the base substrate 110 on which the source electrode SE and the drain electrode DE are formed. The first passivation layer 170 is formed to have a fourth thickness y that is the same as the third thickness x of the source metal layer 150 or thicker than the third thickness x.

The first passivation layer 170 may be formed of, for example, silicon nitride (SiNx, 0 <x <1) or silicon oxide (SiOy, 0 <y <1). The first passivation layer 170 may be formed on the base substrate 110 on which the source electrode SE and the drain electrode DE are formed, for example, by a sputtering method.

Alternatively, the first passivation layer 170 may be deposited on the base substrate 110 on which the source electrode SE and the drain electrode DE are formed by plasma enhanced chemical vapor deposition (PECVD). .

Alternatively, the first passivation layer 170 may be formed of aluminum oxide (AlOz, 0 <z <1). In order to form the first passivation layer 170 from the aluminum oxide, the first passivation layer 170 may be formed on the base substrate 110 on which the source electrode SE and the drain electrode DE are formed by atomic layer deposition (ALD). have.

Referring to FIG. 7B, the first passivation layer 170 is etched to form a first residual pattern 172 and a second residual pattern 174.

The first residual pattern 172 is formed to surround the source electrode SE, and the second residual pattern 174 is formed to surround the drain electrode DE. The first residual pattern 172 formed on the first sidewall SW1 of the source electrode SE and the second residual pattern 174 formed on the second sidewall SW2 of the drain electrode are spaced apart from each other. Although not illustrated, the first passivation layer 170 etched to surround the data lines DLm and DLm + 1 may remain.

The first and second residual patterns 172 and 174 may be formed by, for example, wet etching or dry etching the first passivation layer 170. For example, the first passivation layer 170 may be etched through a dry etching process such that ends of the first and second residual patterns 172 and 174 are about 90 ° based on the exposed ohmic contact pattern 144b. It can be formed to form a slope of.

Referring to FIG. 7C, the first ohmic contact portion 146a and the second ohmic contact portion 146b are formed using the first and second residual patterns 172 and 174.

The first and second ohmic contact portions 146a and 146b are formed by etching the ohmic contact pattern 144b exposed between the first and second residual patterns 172 and 174. The first and second ohmic contact portions 146a and 146b etch the ohmic contact pattern 144b using the first and second residual patterns 172 and 174 as masks.

The first ohmic contact portion 146a is disposed under the source electrode SE, and the second ohmic contact portion 146b is spaced apart from the first ohmic contact portion 146a and disposed under the drain electrode DE. All. The first ohmic contact portion 146a is formed to protrude relatively than the first sidewall SW1 of the source electrode SE. The second ohmic contact portion 146b is formed to protrude relatively than the second sidewall SW2 of the drain electrode DE. The semiconductor pattern 142b may be removed by a predetermined thickness while forming the first and second ohmic contact portions 146a and 146b.

The channel CH is formed by partially exposing the semiconductor pattern 142b through the first and second ohmic contact portions 146a and 146b spaced apart from each other. The distance L from which the first and second ohmic contact parts 146a and 146b are spaced apart from each other is defined as a channel length. Channel length L according to an embodiment of the present invention may be about 5㎛ or less. In general, the channel length is defined as the separation distance L + Lx + Ly between the source electrode SE and the drain electrode DE, but according to an embodiment of the present invention, the channel length L may be defined as the first and the first lengths. The two ohmic contact portions 146a and 146b may be defined as spaced distances, and the channel length may be formed to be relatively shorter than the existing spaced distance L + Lx + Ly. Channel lengths Lx and Ly, which may be reduced by the first and second residual patterns 172 and 174, may each be approximately 1 μm, for example. By shortening the channel length L, the current driving capability of the thin film transistor TFT can be improved.

In addition, according to an embodiment of the present invention, since no additional equipment is used, an increase in manufacturing cost does not occur.

Referring to FIG. 7D, a second passivation layer 180 is formed on the base substrate 110 on which the first and second ohmic contact portions 146a and 146b are formed. The second passivation layer 180 may be formed of, for example, silicon nitride (SiNx, 0 <x <1).

FIG. 8 is a plan view of a base substrate on which contact holes and pixel electrodes are formed, and FIG. 9 is a cross-sectional view taken along the line II ′ of FIG. 8.

Referring to FIG. 8, the pixel electrode PE is electrically connected to one end of the drain electrode DE through the contact hole CNT. The pixel electrode PE may be formed in an area defined by the gate lines GLn and GLn + 1 and the data lines DLm and DLm + 1 of the base substrate 110. The pixel electrode PE defines a storage capacitor Cst together with the gate insulating layer 130 and the second passivation layer 180 formed between the storage electrode STE, the pixel electrode PE, and the storage electrode STE. .

Referring to FIG. 9, the contact hole CNT is formed by removing the second passivation layer 180 on one end of the drain electrode DE. One end of the drain electrode DE is exposed through the contact hole CNT, and the exposed drain electrode DE contacts the pixel electrode PE.

The pixel electrode PE is formed of a transparent and conductive material. The pixel electrode PE may be formed of, for example, indium zinc oxide (IZO), indium tin oxide (ITO), or the like.

10A through 10D are flowcharts illustrating a method of manufacturing an array substrate, according to another exemplary embodiment.

A method of manufacturing an array substrate according to another exemplary embodiment of the present invention is an embodiment of the present invention illustrated in FIGS. 1 to 9 except for forming a semiconductor pattern, a first ohmic contact pattern, a source electrode, and a drain electrode. Since the same as the manufacturing method of the array substrate according to, overlapping detailed description will be omitted.

Referring to FIG. 10A, a gate metal layer (not shown) is formed on the base substrate 110, and the gate metal layer is patterned to form a gate electrode GE. The gate metal layer may include metal layers having different physical properties.

The gate insulating layer 130 is formed on the base substrate on which the gate electrode GE is formed.

A semiconductor layer (not shown) and an ohmic contact layer (not shown) are sequentially stacked on the base substrate 110 on which the gate insulating layer 130 is formed. The semiconductor layer and the ohmic contact layer are patterned to form a semiconductor pattern 142b and an ohmic contact pattern 144b disposed on the gate electrode GE.

Referring to FIG. 10B, a source metal layer (not shown) is formed on the base substrate 110 on which the semiconductor pattern 142b and the ohmic contact pattern 144b are formed. The source metal layer may include metal layers having different physical properties. The source metal layer is patterned to form a source electrode SE and a drain electrode DE spaced apart from the source electrode SE. The ohmic contact pattern 144b is exposed between the source electrode SE and the drain electrode DE spaced apart from each other.

Referring to FIG. 10C, a first passivation layer 170 is formed on the base substrate 110 on which the semiconductor pattern 142b, the ohmic contact pattern 144b, the source electrode SE, and the drain electrode DE are formed. The processes are the same as those shown in FIGS. 7B-7D.

Referring to FIG. 10D, the semiconductor pattern 142b is exposed through the first residual pattern 172 and the second residual pattern 174 formed using the first passivation layer 170. The channel length L is defined as the distance between the first and second residual patterns 172 and 174 spaced apart from each other.

A second passivation layer 180 is formed to cover the base substrate 110 on which the channel CH is formed, and is formed through the contact hole CNT of the second passivation layer 180 exposing one end of the drain electrode DE. The pixel electrode PE and the drain electrode DE formed on the second passivation layer 180 are electrically connected to each other.

As described in detail above, the first and second ohmic contact portions 146a and 146b may be formed using the first and second residual patterns 172 and 174 formed by etching the first passivation layer 170. By forming the channel length L, the current driving capability of the thin film transistor TFT may be improved.

According to the method of manufacturing the array substrate and the array substrate as described above, the current driving capability of the thin film transistor may be improved by reducing the channel length without increasing additional masks and introducing new materials.

Although described with reference to the above embodiments, those skilled in the art will understand that various modifications and changes can be made without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (9)

A first passivation layer is formed on a base substrate on which a gate electrode, a semiconductor pattern formed on the gate electrode, an ohmic contact pattern formed on the semiconductor pattern, a source electrode and a drain electrode spaced apart from each other on the ohmic contact pattern are formed. Doing; Etching the first passivation layer to form a first residual pattern surrounding the source electrode and a second residual pattern surrounding the drain electrode; Etching the ohmic contact pattern exposed by the first and second residual patterns to expose the semiconductor pattern; Forming a second passivation layer on the base substrate to which the semiconductor pattern is exposed; And Forming a pixel electrode on the second passivation layer, the pixel electrode being in contact with the drain electrode. The method of claim 1, wherein the first thickness of the first passivation layer is And a thickness equal to a second thickness of the source electrode and the drain electrode. The method of claim 2, wherein the forming of the second residual pattern is performed. And etching the first passivation layer by dry etching. The method of claim 1, wherein the forming of the second passivation layer is performed. And etching the second passivation layer formed on one end of the drain electrode to expose one end of the drain electrode. The method of claim 4, further comprising: forming a semiconductor layer and an ohmic contact layer on the base substrate; Etching the semiconductor layer and the ohmic contact layer to form the semiconductor pattern and the ohmic contact pattern; Forming a source metal layer on the base substrate on which the ohmic contact pattern is formed; And Etching the source metal layer to form the source electrode and the drain electrode. The method of claim 4, further comprising: sequentially forming a semiconductor layer, an ohmic contact layer, and a source metal layer on the base substrate; Etching the source metal layer to form a source pattern; Etching the semiconductor layer and the ohmic contact layer using the source pattern to form the semiconductor pattern and the ohmic contact pattern; And Etching the source pattern to form the source electrode and the drain electrode. A gate electrode formed on the base substrate; A semiconductor pattern formed on the gate electrode; Source and drain electrodes spaced apart from each other on the semiconductor pattern; A first residual pattern surrounding the source electrode and a second residual pattern surrounding the drain electrode; A first ohmic contact portion disposed between the source electrode and the first residual pattern and the semiconductor pattern, the first ohmic contact portion spaced apart from the first ohmic contact portion to expose the semiconductor pattern, A second ohmic contact portion disposed between the semiconductor patterns; And And a pixel electrode in electrical contact with the drain electrode. 8. The array substrate of claim 7, wherein a distance between the first and second residual patterns spaced apart from each other is defined by a channel length. The array substrate of claim 8, further comprising a passivation layer formed between the base substrate including the source electrode, the drain electrode, the first and second residual patterns, and the pixel electrode.

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