KR20080098941A - OLED display and manufacturing method thereof - Google Patents

Abstract

The present invention relates to an organic light emitting diode display and a method of manufacturing the same. In particular, the organic light emitting diode display includes a first substrate and a second substrate facing each other, a gate line formed in one direction on the first substrate, and the gate line; Intersecting the data line and the power supply voltage supply line and the switching thin film transistor formed at the intersection of the gate line and the data line, and defining the pixel region. A driving thin film transistor formed at an intersection, a gate pad spaced apart from an end of the gate line, a data pad formed at an end of the data line, a connection pattern connecting the end of the gate line and the gate pad, 2 an organic light emitting layer formed on the substrate, the lower portion of the organic light emitting layer and It is configured to include a first electrode and a second electrode, and a contact electrode connecting the second electrode and the driving thin film transistor formed in the portion.

Description

Organic light-emitting display device and manufacturing method therefor {ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME}

1 is a cross-sectional view illustrating a general organic light emitting display device.

2 is a plan view illustrating an organic light emitting display device of the present invention.

3 is a cross-sectional view illustrating an organic light emitting display device according to an exemplary embodiment of the present invention taken along lines II ′, II-II ′, and III-III ′ of FIG. 2.

4A through 4E are process plan views illustrating a method of manufacturing an organic light emitting display device according to the present invention.

5A through 5F are cross-sectional views illustrating a method of manufacturing an organic light emitting display device according to an embodiment of the present invention, taken along lines II ′, II-II ′, and III-III ′ of FIGS. 4A to 4E.

<Description of Major Symbols in Drawing>

110: first substrate 112: gate line

118: data line 128: power supply voltage supply line

144 contact electrode

150: lower gate pad pattern 152: upper gate pad pattern

160: lower data pad pattern 162: upper data pad pattern

210: second substrate 212: first electrode

214: partition 216: organic light emitting layer

218: second electrode 220: seal pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting display device and a method of manufacturing the same, and more particularly, to an organic light emitting display device and a method of manufacturing the same, which can prevent corrosion of a pad part and simplify a process.

As the information society develops, the demand for display devices is increasing in various forms, and in recent years, organic light emitting display devices, liquid crystal display devices, and plasma display panels have been developed. Various flat panel display devices such as Plasma Display Panel and Vacuum Fluorescent Display have been studied, and some of them are already used as display devices in various devices.

Among the flat panel display devices, the organic light emitting display device is a self-light emitting device, and since the backlight is not required as compared to the liquid crystal display device which is a non-light emitting device, it is possible to have a light weight. In addition, high color purity is possible, low power consumption, low voltage driving, suitable for portable electronic devices, fast response speed, wide temperature range. In particular, there is an advantage in that it is cheap in terms of manufacturing costs.

The organic light emitting diode display is a self-luminous display that uses light phenomena generated by combining electrons and holes in an organic compound thin film layer when a current flows through a fluorescent or phosphorescent organic compound thin film. It has a wide viewing angle.

In general, an organic light emitting diode display is classified into a bottom emission method or a top emission method according to where the emission layer is positioned on the upper and lower substrates.

Hereinafter, a conventional organic light emitting diode display will be described with reference to the accompanying drawings.

1 is a cross-sectional view illustrating a general organic light emitting display device.

As shown in FIG. 1, a general organic light emitting diode display includes a first substrate 10 made of glass, a thin film transistor array 12 formed on the first substrate 10, and a thin film transistor array 12. The light emitting layer 14 formed on the upper portion, the seal member 16 formed surrounding the outer portion of the first substrate 10, and the second substrate 18 bonded to the first substrate 10 by the seal member 16. It consists of.

The thin film transistor array 12 is formed on a gate line (not shown) and data line (not shown) formed on the first substrate 10 to cross each other, and formed at the intersection of the gate line and the data line, respectively. It consists of a thin film transistor (not shown).

The light emitting layer may include a first electrode (not shown) used as a common electrode, a partition (not shown) positioned at a boundary portion of each subpixel on the first electrode, an organic light emitting layer (not shown) in a region within the partition wall, The second electrode (not shown) is formed in a pattern separated in units of subpixels. In this case, the organic light emitting layer has a structure in which the first carrier transporting layer, the light emitting layer, and the second carrier transporting layer are sequentially stacked, and the first and second carrier transporting layers inject electrons or holes into the light emitting layer. It serves to injection and transport.

The dual plate organic light emitting display device (DOD) has the following problems in forming a pad part.

The conductive spacer, which serves to connect the organic light emitting diode and the thin film transistor, may be formed of a material capable of lowering the contact resistance. On the other hand, unlike the surface metal of the conductive spacer, the upper portion of the pad portion of the organic light emitting diode display is formed of a metal oxide such as indium tin oxide (ITO) to prevent corrosion as a portion exposed to air. However, metal oxides such as ITO generally have very high resistance.

Accordingly, although the conductive spacer and the upper metal layer of the pad part are formed on the same layer, a material having different characteristics is used, so that the process is complicated by performing two patterning on the same layer.

The present invention has been made to solve the above problems, first, forming a contact electrode connecting the organic light emitting diode and the thin film transistor with a low specific resistance material, the upper metal layer of the pad portion is formed of a material resistant to corrosion It is an object of the present invention to provide a light emitting display device and a method of manufacturing the same.

Another object of the present invention is to provide an organic light emitting display device and a method of manufacturing the same, which can simplify a process by simultaneously patterning a source / drain metal layer and a metal layer of a pad part.

The organic light emitting diode display according to the above object has a first substrate and a second substrate facing each other, a gate line formed in one direction on the first substrate, and intersects with the gate line so as to define a pixel region. A data line and a power supply voltage line formed at regular intervals from each other, a switching thin film transistor formed at an intersection portion of the gate line and the data line, and a driving thin film transistor formed at an intersection portion of the gate line and the power supply voltage supply line. A gate pad spaced apart from an end of the gate line and a data pad formed at an end of the data line, a connection pattern connecting the end of the gate line and the gate pad, and an organic light emitting layer formed on the second substrate And first and second electrodes formed on the lower and upper portions of the organic light emitting layer. It is polar, and comprises a contact electrode connecting the second electrode and the driving thin film transistor.

According to an aspect of the present invention, a method of manufacturing an organic light emitting display device includes: forming a gate line in one direction on a first substrate, data lines spaced apart from each other so as to define a pixel area intersecting the gate line; Forming a power supply voltage supply line, a gate pad spaced apart from an end of the gate line, and a data pad at an end portion of the data line in an upper and lower layer stacked structure, forming a passivation layer on the entire surface of the first substrate, and the passivation layer. Patterning to form first and second contact holes on an end of the gate line and an upper portion of the gate pad, respectively, and forming a gate pad hole and a data pad hole on the other side of the gate pad and on an upper portion of the data pad, respectively. And electrically connecting the gate line and the gate pad through the first and second contact holes. Gyeolhaneun connection pattern, and comprise the step of forming a contact electrode in each of the pixel regions.

Hereinafter, an organic light emitting diode display according to an exemplary embodiment will be described with reference to the accompanying drawings.

FIG. 2 is a plan view illustrating an organic light emitting diode display according to an exemplary embodiment of the present invention, and FIG. 3 is a cross-sectional view illustrating the organic light emitting diode display of the present invention taken along lines II ′, II-II ′, and III-III ′ of FIG. 2. to be.

The organic light emitting diode display according to the present invention includes a first substrate 110 and a second substrate 210 that face each other, a gate line 112 formed in one direction on the first substrate 110, and a gate line 112. And a switching thin film transistor formed at an intersection of the data line 118 and the power supply voltage supply line 128 and the gate line 112 and the data line 118 that are formed at regular intervals to cross each other. A driving thin film transistor (DTFT) formed at an intersection of the STFT, the gate line 112, and the power supply voltage supply line 128, the first electrode 212 formed on the entire upper surface of the second substrate 210; The barrier rib 214 formed corresponding to the boundary of each pixel region, the organic emission layers 216: 216a, 216b, and 216c formed in the barrier rib 214 on the first electrode 212, and the organic emission layer 216. The second electrode 218, the driving thin film transistor DTDT, and the second electrode 218 are formed on the upper side. A contact electrode 144 for connecting, a gate pad formed over the display area and the non-display area on the first substrate 110, and a first connection pattern 154 connecting the end of the gate line 112 and the gate pad. ) And a data pad formed at an end of the data line 118.

The organic light emitting diode display according to the present invention is defined as a pad portion outside the A line, a inside of the display area and a pad connection portion outside the B line. A switching thin film transistor (STFT) and a driving thin film transistor (DTFT) are formed in a display area, a gate pad and a data pad are formed in a pad part, and a pad connection part electrically connects the gate line 112 and the gate pad. The first connection pattern 154 is formed.

At this time, the seal pattern 220 is formed along the A line, the first substrate 110 and the second substrate 210 is bonded to each other by the seal pattern 220 and the device located inside the seal pattern 220 They are isolated from the outside air. In addition, upper portions of the gate pad and the data pad formed in the pad part are exposed to air.

The switching TFT may include a first gate electrode 112a protruding from the gate line 112, a first semiconductor layer 116 formed on the first gate electrode 112a, and a data line 118. The first source electrode 118a is formed to protrude toward one side of the first semiconductor layer 116, and the first drain electrode 120 is formed on the other side of the first semiconductor layer 116. In addition, a first electrode pattern 132 is formed on the data line 118 and the first source electrode 118a, and a second electrode pattern 134 is formed on the first drain electrode 120. have.

The driving thin film transistor DTFT includes a second gate electrode 122 formed in an island shape at an intersection of the gate line 112 and the power voltage supply line 128, and a second gate electrode 122 formed on the second gate electrode 122. The second semiconductor layer 126, the first source electrode 128a protruding from the power supply voltage supply line 128 to one side of the second semiconductor layer 126, and the other side of the second semiconductor layer 126. The second drain electrode 130 is formed. In addition, a third electrode pattern 136 is formed on the power supply voltage supply line 128 and the second source electrode 128a, and a fourth electrode pattern 138 is formed on the second drain electrode 130. Formed.

The switching thin film transistor STFT and the driving thin film transistor DTFT are electrically connected to each other. A first contact hole 170 and a second contact hole 172 are formed on the second electrode pattern 134 of the switching thin film transistor STFT and the second gate electrode 122 of the driving thin film transistor DTFT, respectively. have. The second connection pattern 142 is formed to electrically connect the second electrode pattern 134 and the second gate electrode 122 through the first and second contact holes 170 and 172.

Unlike the spacers for liquid crystal displays, the contact electrode 144 is intended to electrically connect the elements formed on the first substrate 110 and the second substrate 210 rather than the cell gap retention function. It is desirable to select from metal materials with a low resistivity for high energization. In this case, the contact electrode 144 serves as the conductive spacer mentioned in the related art.

The gate pads are formed to be spaced apart from end portions of the gate lines 112 and are formed inside and outside the A line, and the lower gate pad pattern 150 and the upper gate pad pattern 152 are stacked. A fourth contact hole 176 is formed at an upper end of the gate line 112 between an A line and a B line, and a fifth contact hole 178 is formed at an upper part of the upper gate pad pattern 152. A gate pad hole 180 is formed on the upper gate pad pattern 152 on the pad portion outside the B line. The first connection pattern 154 is formed to electrically connect the gate line 112 and the upper gate pad pattern 152 through the fourth and fifth contact holes 176 and 178.

The data pad is connected to an end of each data line 118 to be formed on the pad portion of the first substrate 110, and the lower data pad pattern 160 and the upper data pad pattern 162 are stacked. The data pad hole 182 is formed on the upper data pad pattern 162.

In the above, the first gate electrode 112a and the second gate electrode 122 are formed on the same layer, and the first semiconductor layer 116 and the second semiconductor layer 126 are formed on the same layer. In this case, the gate insulating layer 114 is formed to insulate the layer on which the first gate electrode 112a and the second gate electrode 122 are formed and the layer on which the first semiconductor layer 116 and the second semiconductor layer 126 are formed. do.

The first and second source electrodes 118a and 128a, the first and second drain electrodes 120 and 130, the lower gate pad pattern 150, and the lower data pad pattern 160 may be connected to the data line 118. The first to fourth electrode patterns 132, 134, 136, and 138, the upper gate pad pattern 152, and the upper data pad pattern 162 are formed on the same layer, and are formed on the same layer. In this case, the upper gate pad pattern 152 and the upper data pad pattern 162 may be formed of metal oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO) to prevent corrosion as portions exposed in the air. In addition, the first and second connection patterns 154 and 142 and the contact electrode 144 are formed on the same layer.

In this case, the passivation layer 140 may be formed on the upper layer of the first to fourth electrode patterns 132, 134, 136, and 138, the upper gate pad pattern 152, and the upper data pad pattern 162. Is formed.

In addition, the partition wall 214 is formed to surround the boundary of each pixel area and serves to distinguish between pixels.

The organic light emitting layer 216 has a structure in which the first carrier transporting layer 216a, the light emitting layer 216b, and the second carrier transporting layer 216c are sequentially stacked, and the first and second carrier transporting layers 216a and 216c are stacked. ) May inject and transport electrons or holes into the light emitting layer 216b.

The first and second carrier transfer layers 216a and 216c are determined according to the arrangement of the anode and the cathode. For example, the light emitting layer 216b is selected from a polymer material, and the first electrode 212 is the anode ( When the anode and the second electrode 218 are configured as a cathode, the first carrier transfer layer 216a adjacent to the first electrode 212 has a structure in which a hole injection layer and a hole transport layer are sequentially stacked. The second carrier transport layer 216c adjacent to the second electrode 218 has a structure in which an electron injection layer and an electron transport layer are sequentially stacked adjacent to the second electrode 218.

The second drain electrode 130 of the driving thin film transistor DTFT formed on the first substrate 110 and the second electrode 218 formed on the second substrate 210 are fourth electrodes formed on the first substrate 110. The pattern 138 and the contact electrode 144 are electrically connected.

As described above, the lower gate pad pattern 150 made of metal in the gate pad has an upper gate pad pattern 152 made of metal oxide formed thereon to prevent exposure to air. In addition, since the passivation layer 140 is formed on the side surface of the lower gate pad pattern 150, there is no risk of corrosion due to exposure to air.

Similarly, in the data pad, the lower data pad pattern 160 made of metal is formed on the upper data pad pattern 162 made of metal oxide to prevent exposure to air. In addition, since the passivation layer 140 is formed on the side surface of the lower data pad pattern 160, there is no danger of corrosion due to exposure to air.

Next, a method of manufacturing the organic light emitting display device of the present invention will be described in detail with reference to the accompanying drawings.

4A through 4E are process plan views illustrating a method of manufacturing an organic light emitting display device, and FIGS. 5A through 5F are lines II ′, II-II ′, and III-III ′ of FIGS. 4A through 4E. It is a process cross section which shows the manufacturing method of the organic light emitting display device of this invention along the line.

4A to 4E, the inside of the line A represents the display area, and the outside of the A line represents the non-display area.

First, as shown in FIGS. 4A and 5A, a first substrate 110 having pixel regions defined in a matrix form is prepared, and copper (Cu), aluminum (Al), and aluminum alloy (AlNd) are formed on the first substrate 110. ), At least one or more low-resistance metal materials such as molybdenum (Mo) and chromium (Cr) are deposited.

Subsequently, the metal material is patterned with a first mask through a photo and etching process to form a gate line 112 and a first gate electrode 112a protruding from the gate line 112 on the first substrate 110. The second gate electrode 122 is spaced apart from the first gate electrode 112a by a predetermined distance.

Subsequently, an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) is deposited on the entire surface of the first substrate 110 including the first and second gate electrodes 112a and 122 to form the gate insulating layer 114. .

As shown in FIGS. 4B and 5B, a pure amorphous silicon layer and an amorphous silicon layer containing impurities are stacked on the entire surface of the first substrate 110 on the gate insulating layer 114.

Subsequently, a pure amorphous silicon layer and an amorphous silicon layer containing impurities are selectively removed by a second mask through a photo and etching process, so that the first semiconductor layer is formed on the gate insulating layer 114 on the first gate electrode 112a. 116 is formed, and a second semiconductor layer 126 is formed on the gate insulating layer 114 on the second gate electrode 122.

4C and 5C, copper (Cu), aluminum (Al), aluminum alloy (AlNd), and molybdenum (Mo) are formed on the entire surface of the first substrate 110 including the first and second semiconductor layers 116 and 126. , Any one of low-resistance metal materials such as chromium (Cr), titanium (Ti), tantalum (Ta) and molybdenum-tungsten (MoW) is deposited by sputtering, and ITO (Indium Tin Oxide) And deposit a transparent metal such as IZO (Indium Zinc Oxide).

Next, the data line 118 and the data line 118 that define the pixel region by crossing the gate line 112 by patterning the stacked transparent metal and the low resistance metal material with a third mask through a photo and etching process. A first source electrode 118a protruding from the first semiconductor layer 116 toward one side, a first electrode pattern 132, and a first semiconductor on the data line 118 and the first source electrode 118a. The first drain electrode 120 is formed on the other side of the layer 116 and the second electrode pattern 134 is formed on the first drain electrode. The power supply voltage supply line 128 spaced apart from the data line 118 by a predetermined distance, the second source electrode 128a protruding from the power supply voltage supply line 128 toward one side of the second semiconductor layer 126, The third electrode pattern 136 on the power supply voltage supply line 128 and the second source electrode 128a, the second drain electrode 130 on the other side of the second semiconductor layer 126, and the second drain electrode. The fourth electrode pattern 138 is formed on the 130. In addition, the lower gate pad pattern 150 and the upper gate pad pattern 152 are formed on the display area and the non-display area of the first substrate 110 adjacent to the end of the gate line 112. The lower data pad pattern 160 and the upper data pad pattern 162 are formed on the lower data pad pattern 160 so as to be connected to an end of the data line 118.

The data line 118, the first source electrode 118a, the first drain electrode 120, the power voltage supply line 128, the second source electrode 128a, the second drain electrode 130, and the lower portion of the data line 118. The gate pad pattern 150 and the lower data pad pattern 160 are formed by patterning a low resistance metal material and are formed on the same layer.

In addition, the first to fourth electrode patterns 132, 134, 136, and 138, the upper gate pad pattern 152, and the upper data pad pattern 162 are formed by patterning transparent metal and are formed on the same layer.

4D and 5D, a first including second, third, and fourth electrode patterns 132, 134, 136, and 138, an upper gate pad pattern 152, and an upper data pad pattern 162. Silicon nitride (SiN _x ) or silicon oxide (SiO ₂ ), which is an inorganic material, is deposited on the entire surface of the substrate 110 by chemical vapor deposition, or BCB (benzoicbutene) or an acrylic resin, which is an organic material, is coated to form a protective film ( 140).

Subsequently, a surface of a predetermined portion of each of the ends of the second electrode pattern 134, the second gate electrode 122, the fourth electrode pattern 138, and the gate line 112 may be formed using a fourth mask through a photo and etching process. The passivation layer 140 is patterned to expose the first contact hole 170, the second contact hole 172, the third contact hole 174, and the fourth contact hole 176, respectively. In addition, the fifth contact hole 178 and the gate pad hole 180 are formed to expose the upper surface of the display area and the non-display area of the upper gate pad pattern 152, and the upper surface of the upper data pad pattern is formed. The data pad hole 182 is formed to be exposed.

4E and 5E, copper (Cu), aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta), and molybdenum-tungsten (MoW) Any one of low resistance metal materials, such as these, is deposited by a sputtering method.

Subsequently, the low resistance metal material is patterned with a fifth mask through a photo and etching process to electrically connect the gate line 112 and the upper gate pad pattern 152 through the fourth and fifth contact holes 176 and 178. A second connection pattern 142 electrically connecting the second electrode pattern 134 and the second gate electrode 122 through the first connection pattern 154 and the first and second contact holes 170 and 172. ) And a contact electrode 144 electrically connected to the fourth electrode pattern 138 through the third contact hole 174.

In this embodiment, the first and second semiconductor layers 116 and 126 are formed using a third mask, and the data line 118, the first source electrode 118a, and the first drain electrode are formed using a fourth mask. 120, the power supply voltage supply line 128, the second source electrode 128a, the second drain electrode 130, the lower gate pad pattern 150, the lower data pad pattern 160, and the first to fourth electrodes. Patterns 132, 134, 136, and 138, an upper gate pad pattern 152, and an upper data pad pattern 162 are formed. That is, two masks are needed to form the layers.

In this case, if the mask for diffraction exposure is used, it is also possible to form all of the layers with one mask. This reduces the photo process once, further simplifying the process.

As shown in FIG. 5F, a first electrode 212 is formed by depositing metal on the entire upper surface of the second substrate 210, and a partition wall having a constant height is formed on the first electrode 212 corresponding to the boundary of each pixel region. Form.

Subsequently, a light emitting solution is deposited on the first electrode 212 positioned in each pixel area by using a shadow mask (not shown) to form the organic light emitting layer 216. In this case, the luminescent solution exhibits colors such as red, green, and blue. The organic light emitting layer 216 has a structure in which the first carrier transfer layer 216a, the light emitting layer 216b, and the second carrier transfer layer 216c are stacked in this order.

Next, a second electrode 218 is formed on the organic emission layer 216 of each pixel area. In addition, a seal pattern 220 is formed along an A line which is a boundary between the display area and the non-display area, and the first substrate 110 and the second substrate 210 are bonded to each other and fixed.

Thus, the organic light emitting diode display according to the present invention is completed.

At least six masks are required to form the lower substrate of the conventional dual plate type organic light emitting display. That is, six masks, such as a mask for forming a gate line, a mask for forming a semiconductor layer, a mask for forming a data line, a mask for forming a contact hole, a mask for forming a gate and a data pad, and a mask for forming a contact electrode. The lower substrate of the dual plate type organic light emitting diode display device is formed by using a.

On the other hand, when the organic light emitting diode display of the present invention is formed as described in the above embodiment, it can be manufactured using five masks. That is, a dual plate type using five masks such as a mask for forming a gate line, a mask for forming a semiconductor layer, a mask for forming a data line and pad metal, a mask for forming a contact hole, and a mask for forming a contact electrode. A lower substrate of the organic light emitting display device is formed.

In addition, when the mask for diffraction exposure is used, the semiconductor layer, the data line, and the pad metal can be formed using one mask, so the process becomes simpler, and the lower part of the dual plate type organic light emitting diode display using four masks is used. The substrate can be formed.

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

The organic light emitting diode display and a method of manufacturing the same as described above have the following effects.

First, the contact electrode connecting the organic light emitting diode and the thin film transistor is formed of a material having a low specific resistance to lower the contact resistance, and the upper metal layer of the pad part is formed of a material resistant to corrosion, so that the gate pad and the data pad exposed to air are corroded. It is effective to prevent that.

Second, there is an effect that can simplify the process by patterning the source / drain metal layer and the metal layer of the pad portion at the same time.

Claims (20)

A first substrate and a second substrate facing each other; A gate line formed in one direction on the first substrate; A data line and a power supply voltage supply line which are formed at regular intervals from each other so as to cross the gate line and define a pixel area; A switching thin film transistor formed at an intersection of the gate line and a data line and a driving thin film transistor formed at an intersection of the gate line and a power supply voltage supply line; A gate pad spaced apart from an end of the gate line and a data pad formed at an end of the data line; A connection pattern connecting an end of the gate line and the gate pad; An organic light emitting layer formed on the second substrate, and first and second electrodes formed under and over the organic light emitting layer; And And a contact electrode connecting the driving thin film transistor and the second electrode. The method of claim 1, The data line, the gate pad, and the data pad are formed on the same layer. The method of claim 1, The gate pad and the data pad are formed of upper and lower double layers, respectively, and an upper layer is a metal layer having corrosion resistance. The method of claim 3, wherein And the upper layer is indium tin oxide (ITO) or indium zinc oxide (IZO). The method of claim 3, wherein The lower layer is formed of any one of copper (Cu), aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta), and molybdenum-tungsten (MoW). An organic light emitting display device. The method of claim 1, And the contact electrode and the connection pattern are formed on the same layer. The method of claim 6, The contact electrode and the connection pattern may include copper (Cu), aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta), and molybdenum-tungsten (MoW). Organic light emitting display device; The method of claim 6, And a protective layer formed under the contact electrode and the connection pattern to cover the gate line, the data line, the power supply voltage supply line, the switching thin film transistor, the driving thin film transistor, the gate pad, and the data pad. Light emitting display device. The method of claim 8, In the protective film, And a second contact hole formed above the gate line end and a second contact hole formed above the gate pad. The method of claim 9, And the connection pattern electrically connects the gate line and the gate pad through the first and second contact holes. The method of claim 8, Within the protective film A gate pad hole formed on the gate pad; And a data pad hole formed on the data pad. The method of claim 11, And a seal pattern formed at a boundary line between the data line, the data pad, the connection pattern, and a boundary line between the gate pad hole. Forming a gate line in one direction on the first substrate; A data layer and a power supply voltage line spaced apart from each other so as to define a pixel region intersecting the gate line, a gate pad spaced apart from an end portion of the gate line, and a data pad formed at an end portion of the data line, and an upper and lower layer stacked structure. Forming to; Forming a protective film on the entire surface of the first substrate; The passivation layer is patterned to form first and second contact holes, respectively, on an end of the gate line and one side of the gate pad, and a gate pad hole and a data pad hole on the other side of the gate pad and on the data pad, respectively. Forming a; And forming a connection pattern electrically connecting the gate line and the gate pad through the first and second contact holes, and forming a contact electrode in each pixel area. Manufacturing method. The method of claim 13, Simultaneously with forming the data line and the power supply voltage supply line, And a switching thin film transistor at an intersection of the gate line and a data line and a driving thin film transistor at an intersection of the gate line and a power supply voltage supply line. The method of claim 14, Forming the switching thin film transistor and the driving thin film transistor, Forming a first gate electrode protruding from the gate line and a second gate electrode spaced apart from the first gate electrode by a predetermined distance; Forming a gate insulating film on an entire surface of the first substrate including the first and second gate electrodes; Forming a first semiconductor layer and a second semiconductor layer on the gate insulating layer on the first gate electrode and the second gate electrode, respectively; Forming a first source electrode and a first drain electrode on both sides of the first semiconductor layer, and forming a second source electrode and a second drain electrode on both sides of the second semiconductor layer. Method for manufacturing a display device. The method of claim 13, And the gate pad and the data pad are respectively formed of upper and lower double layers, and an upper layer is a metal layer having corrosion resistance. The method of claim 16, The upper layer is made of indium tin oxide (ITO) or indium zinc oxide (IZO). The method of claim 16, The lower layer is formed of any one of copper (Cu), aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta), and molybdenum-tungsten (MoW). A method of manufacturing an organic light emitting display device. The method of claim 13, Forming a first electrode on an upper surface of the second substrate; Forming an organic emission layer on each pixel area above the first electrode; And forming a second electrode in each pixel area above the organic light emitting layer. The method of claim 19, Forming a seal pattern on a boundary line between the data line and the data pad, a connection line between the connection pattern, and the gate pad hole; And bonding both substrates such that the contact electrode of the first substrate and the second electrode of the second substrate are in contact with each other.

Images