KR20080078348A - Thin film transistor array panel and manufacturing method thereof - Google Patents

Abstract

The present invention includes a gate electrode, a gate insulating film formed on the gate electrode, a source electrode and a drain electrode formed on the gate insulating film and facing each other, and an organic semiconductor in contact with the source electrode and the drain electrode. The difference in the surface contact angles of the gate insulating film, the source electrode and the drain electrode relates to a thin film transistor array panel having a 5 ° or less angle and a method of manufacturing the same.

Description

Thin film transistor array panel and manufacturing method therefor {THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME}

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along the line II-II.

3, 5, 8, and 10 are layout views sequentially illustrating a continuous process of the thin film transistor array panel of FIGS. 1 and 2;

4 is a cross-sectional view of the thin film transistor array panel of FIG. 3 taken along the line IV-IV.

FIG. 6 is a cross-sectional view of the thin film transistor array panel of FIG. 5 taken along the line VI-VI.

7 is a cross-sectional view illustrating a process subsequent to the thin film transistor array panel of FIGS. 5 and 6.

FIG. 9 is a cross-sectional view of the thin film transistor array panel of FIG. 8 taken along the line IX-IX.

FIG. 11 is a cross-sectional view of the thin film transistor array panel of FIG. 10 taken along the line XI-XI.

 <Description of Drawing>

110: insulating substrate 121: gate line

124: gate electrode 129: end of gate line

140: gate insulating film 154: organic semiconductor

171: data line

172, 176: horizontal section 174, 177: vertical section

173: source electrode 175: drain electrode

180: protective film 191: pixel electrode

81, 82: contact auxiliary members 181, 182, and 185: contact holes

Q: channel of thin film transistor

The present invention relates to a thin film transistor array panel and a method of manufacturing the same.

In general, a flat panel display device such as a liquid crystal display (LCD), an organic light emitting device (OLED), an electrophoretic display, or the like, includes a plurality of pairs of electric field generating electrodes It contains an electro-optical active layer. The liquid crystal display device includes a liquid crystal layer as the electro-optical active layer, and the organic light emitting display device includes an organic light emitting layer as the electro-optical active layer.

One of the pair of field generating electrodes is typically connected to a switching element to receive an electrical signal, and the electro-optical active layer converts the electrical signal into an optical signal to display an image.

In the flat panel display device, a thin film transistor (TFT), which is a three-terminal element, is used as a switching element. A data line to be transmitted is provided in the flat panel display.

Among these thin film transistors, studies on organic thin film transistors (OTFTs) including organic semiconductors instead of inorganic semiconductors such as silicon (Si) have been actively conducted.

The organic thin film transistor is attracting attention as a core element of a flexible display device because the organic thin film transistor may be formed in a fiber or film form due to the nature of the organic material.

In addition, the organic thin film transistor may be manufactured by a solution process such as inkjet printing, and thus may be easily applied to a large area flat panel display device having a limitation only by the deposition process.

The organic thin film transistor array panel in which the organic thin film transistors are arranged in a matrix form has many differences in structure and manufacturing method compared with the conventional thin film transistor array panel.

In particular, in order to reduce the influence on the organic semiconductor during the process and to improve the characteristics of the organic thin film transistor, the process becomes complicated and the number of masks required increases.

Accordingly, the technical problem to be solved by the present invention is to solve the problem and to simplify the process while reducing the influence on the organic semiconductor during the manufacturing process of the organic thin film transistor array panel.

The thin film transistor array panel according to the exemplary embodiment of the present invention may include a gate electrode, a gate insulating film formed on the gate electrode, a source electrode and a drain electrode formed on the gate insulating film and facing each other, and the source electrode and the drain electrode; And a contacting organic semiconductor, wherein a difference in surface contact angle between the gate insulating film, the source electrode, and the drain electrode is 5 ° or less.

Surfaces of the gate insulating layer, the source electrode, and the drain electrode may be plasma treated.

The plasma treatment may be performed by supplying a fluorine-containing gas.

The thin film transistor array panel may further include a self-assembled thin film formed on the gate insulating layer, the source electrode and the drain electrode.

The organic semiconductor may not be partitioned by a partition wall.

A method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention includes forming a gate electrode, forming a gate insulating film on the gate electrode, forming a source electrode and a drain electrode on the gate insulating film, and forming the gate insulating film. And surface treating the source electrode and the drain electrode so that surface contact angles of the gate insulating film, the source electrode and the drain electrode are 5 ° or less, and forming an organic semiconductor in contact with the source electrode and the drain electrode. It includes a step.

The surface treatment of the gate insulating layer, the source electrode, and the drain electrode may include plasma treatment by supplying a fluorine-containing gas.

The surface treatment of the gate insulating layer, the source electrode, and the drain electrode may include forming a self-assembled thin film on the gate insulating layer, the source electrode, and the drain electrode.

The forming of the organic semiconductor may be performed by an inkjet printing method.

The inkjet printing method may be performed without a partition wall for partitioning the organic semiconductor.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Next, a thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along line II-II.

The gate line 121 is formed on an insulating substrate 110 made of transparent glass, silicon, or plastic.

The gate line 121 transmits a gate signal and mainly extends in a horizontal direction. Each gate line 121 includes a plurality of gate electrodes 124 protruding upwards and a wide end portion 129 for connection with another layer or an external driving circuit. A gate driving circuit (not shown) that generates a gate signal is mounted on a flexible printed circuit film (not shown) attached over the substrate 110, directly mounted on the substrate 110, or integrated into the substrate 110. Can be. When the gate driving circuit is integrated on the substrate 110, the gate line 121 may extend to be directly connected to the gate driving circuit.

The gate line 121 may be formed of aluminum-based metal such as aluminum (Al) or aluminum alloy, silver-based metal such as silver (Ag) or silver alloy, gold-based metal such as gold (Au) or gold alloy, copper (Cu), copper alloy, etc. Copper-based metals, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloys, low-resistance conductors such as chromium (Cr), tantalum (Ta) and titanium (Ti), or indium tin oxide (ITO) and indium zinc oxide (IZO) It may be made of a conductive oxide such as. However, they may have a multilayer structure including two conductive films (not shown) having different physical properties.

The gate line 121 may be inclined at an inclined angle of about 30 ° to about 80 ° with respect to the surface of the substrate 110.

The gate insulating layer 140 is formed on the gate line 121. The gate insulating layer 140 may be made of an organic material or an inorganic material. Examples of the organic material may include polyimide, polyvinyl alcohol, polyfluorane, parylene, and the like. A soluble high molecular compound is mentioned, An example of an inorganic substance is a silicon oxide surface-treated with octadecyl trichlorosilane (OTS).

A data line 171 and a drain electrode 175 are formed on the gate insulating layer 140.

The data line 171 transmits a data signal and mainly extends in the vertical direction to cross the gate line 121. Each data line 171 includes a wide end portion 179 for connecting a source electrode 173 protruding to the side and another layer or an external driving circuit. A data driving circuit (not shown) for generating a data signal is mounted on a flexible printed circuit film (not shown) attached to the substrate 110, directly mounted on the substrate 110, or integrated in the substrate 110. Can be.

The source electrode 173 includes a horizontal portion 172 connected to the data line 171 and a vertical portion 174 overlapping the gate electrode 124.

The drain electrode 175 is island-shaped and includes a vertical portion 177 facing the vertical portion 174 of the source electrode 173 and a horizontal portion 176 extending laterally from the gate electrode 124.

Like the gate line 121, the data line 171 and the drain electrode 175 may be made of a low resistance conductor or a conductive oxide.

Side surfaces of the data line 171 and the drain electrode 175 may be inclined at an inclination angle of about 30 ° to 80 ° with respect to the surface of the substrate 110.

The surface treatment layer 160 is formed on the data line 171, the drain electrode 175, and the gate insulating layer 140. The surface treatment layer 160 may be a self assembly monolayer (SAM). Alternatively, when the surfaces of the data line 171, the drain electrode 175, and the gate insulating layer 140 are plasma treated, an additional surface treatment layer 160 may be omitted.

The surface treatment layer 160 or plasma treatment may make their surface contact angles substantially the same or similar on the gate insulating layer 140, the data line 171, and the drain electrode 175. The surface contact angle is a measure of how much the solution spreads when a predetermined solution is dropped. The low surface contact angle allows the solution to spread well and the high surface contact angle prevents the solution from spreading well.

The difference between the surface contact angles of the gate insulating layer 140, the data line 171, and the drain electrode 175 is 5 ° or less.

When the surface contact angles of the gate insulating layer 140, the data line 171, and the drain electrode 175 are large, the organic semiconductor solution, which will be described later, is biased to one side, and thus a desired position, for example, the source electrode 173 and the drain electrode ( The organic semiconductor cannot be formed at the position in contact with 175.

For example, when the surface contact angles of the data line 171 and the drain electrode 175 are larger than the surface contact angles of the gate insulating layer 140, the organic semiconductor solution on the gate insulating layer 140 may be the data line 171 and the drain electrode 175. Since the organic semiconductor solution spreads better than the above, the contact between the organic semiconductor solution and the source electrode 173 and the drain electrode 175 may be poor. In this case, the movement of the charge may be affected, thereby degrading characteristics of the organic thin film transistor.

In contrast, when the surface contact angle of the gate insulating layer 140 is greater than the surface contact angles of the data line 171 and the drain electrode 175, the organic semiconductor solution flows along the data line 171 or the source electrode 173 and the drain. An adhesion may be poor on the gate insulating layer 140 between the electrodes 175. Also in this case, the movement of electric charges may be affected, thereby degrading the characteristics of the organic thin film transistor.

Therefore, by controlling the difference between the surface contact angles of the gate insulating layer 140, the source electrode 173, and the drain electrode 175 to about 5 ° or less, the organic semiconductor solution can be formed at a desired position without any bias.

The organic semiconductor 154 is formed on the source electrode 173 and the drain electrode 175.

The organic semiconductor 154 may include a high molecular compound or a low molecular compound dissolved in an aqueous solution or an organic solvent, and may be formed by inkjet printing.

The organic semiconductor 154 includes pentacene and its precursors, tetrabenzoporphyrin and its derivatives, polyphenylenevinylene and its derivatives, polyfluorene and its derivatives, and polytinylene vinyl. Polythienylenevinylene and its derivatives, polythiophene and its derivatives, polythienothiophene and its derivatives, polyarylamine and its derivatives, phthalocyanine and its derivatives, metallized phthalocyanine (metallized phthalocyanine) or halogenated derivatives thereof, perylenetetracarboxylic dianhydride (PTCDA), naphthalenetetracarboxylic dianhydride (NTCDA) or imide derivatives thereof, perylene or It may be made of at least one selected from derivatives including coronene and their substituents. have.

Even when the organic semiconductor 154 is formed by an inkjet printing method, a separate partition for confining them is not necessary. As described above, the difference between the surface contact angles of the gate insulating layer 140, the source electrode 173, and the drain electrode 175 at the position where the organic semiconductor solution is to be dropped is not large, so that each pixel is not biased or flows without any partition. It can be formed uniformly every time.

One gate electrode 124, one source electrode 173, and one drain electrode 175 form one thin film transistor together with the organic semiconductor 154, and the channel Q of the thin film transistor is The organic semiconductor 154 is formed between the source electrode 173 and the drain electrode 175. In this case, the portions of the source electrode 173 and the drain electrode 175 facing each other may be bent to increase the channel width to improve current characteristics.

A passivation layer 180 having a plurality of contact holes 181, 182, and 185 is formed on the organic semiconductor 154 and the surface treatment layer 160. The passivation layer 180 may be made of an organic insulating material or an inorganic insulating material.

The pixel electrode 191 and the contact assistants 81 and 82 are formed on the passivation layer 180.

The pixel electrode 191 is connected to the drain electrode 175 through the contact hole 185. The pixel electrode 191 receives an data voltage from the drain electrode 175 and generates an electric field together with a common electrode (not shown) of another display panel (not shown) to which a common voltage is applied. This determines the direction of the liquid crystal molecules of the liquid crystal layer (not shown) between the two electrodes. The pixel electrode 191 and the common electrode form a capacitor (hereinafter, referred to as a "liquid crystal capacitor") to maintain an applied voltage even after the thin film transistor is turned off.

The pixel electrode 191 may overlap the gate line 121 and / or the data line 171 to increase an aperture ratio.

The contact auxiliary members 81 and 82 are connected to the end portion 129 of the gate line 121 and the end portion 179 of the data line 171 through the contact holes 181 and 182, respectively. The contact auxiliary members 81 and 82 compensate for and protect the adhesion between the end portion 129 of the gate line 121 and the end portion 179 of the data line 171 and an external device.

The pixel electrode 191 and the contact auxiliary members 81 and 82 may be made of a transparent conductive material such as IZO or ITO, and may have a thickness of about 300 kPa to about 2000 kPa.

 Next, a method of manufacturing the organic thin film transistor array panel shown in FIGS. 1 and 2 will be described in detail with reference to FIGS. 3 to 11.

3, 5, 8, and 10 are layout views sequentially illustrating the continuous process of the thin film transistor array panels of FIGS. 1 and 2, and FIG. 4 is a cutaway view of the thin film transistor array panel of FIG. 3 along the line IV-IV. 6 is a cross-sectional view of the thin film transistor array panel of FIG. 5 taken along the line VI-VI. FIG. 7 is a cross-sectional view illustrating a process subsequent to the thin film transistor array panels of FIGS. 5 and 6. 8 is a cross-sectional view of the thin film transistor array panel of FIG. 8 taken along the line IX-IX, and FIG. 11 is a cross-sectional view of the thin film transistor array panel of FIG. 10 taken along the line XI-XI.

First, referring to FIGS. 3 and 4, a gate layer 121 including a gate electrode 124 and an end portion 129 is formed by stacking a conductive layer on an insulating substrate 110 by sputtering and then photolithography. To form.

Next, referring to FIGS. 5 and 6, after the gate insulating layer 140 is stacked on the substrate 110 and the gate line 121, the conductive layer is stacked on the substrate 110 and the photo-etched to form the source electrode 173 and the end portion. The data line 171 and the drain electrode 175 including 179 are formed.

Next, referring to FIG. 7, the surface treatment layer 160 is formed on the gate insulating layer 140, the data line 171, and the drain electrode 175. The surface treatment layer 160 may be formed by depositing a material such as (3-aminopropyl) triethoxysilane or spraying it with a solution and then drying it.

Alternatively, instead of separately forming the surface treatment layer 160, the surfaces of the gate insulating layer 140, the data line 171, and the drain electrode 175 may be plasma treated. At this time, the plasma treatment may be performed by supplying a fluorine-containing gas such as CF ₄ , C ₂ F ₆ and SF ₆ together with oxygen gas (O ₂ ) and / or an inert gas in a vacuum atmosphere. For example, CF ₄ may be plasma treated by feeding it at a rate of 50 sccm for 5 to 8 seconds.

The surface of the gate insulating layer 140, the data line 171, and the drain electrode 175 may be modified by the formation or the plasma treatment of the surface treatment layer 160 to control their surface contact angles substantially the same or similar. have.

8 and 9, an organic semiconductor 154 is formed on the source electrode 173 and the drain electrode 175. The organic semiconductor 154 may be formed by a solution process such as an inkjet printing method. In this case, a step of spraying and drying the organic semiconductor solution while moving the inkjet head (not shown) on the substrate is required.

Meanwhile, the surfaces of the gate insulating layer 140, the source electrode 173, and the drain electrode 175, which are the positions at which the organic semiconductor solution is to be dropped, have substantially the same or similar surface contact angles as described above, so that each pixel does not have a separate partition. The organic semiconductor solution can be dropped, and the organic semiconductor solution can be prevented from flowing or flowing to either side due to the difference in the surface contact angle. Therefore, the number of masks required to form the partition wall can be reduced, thereby reducing the process cost and time.

Next, referring to FIGS. 10 and 11, the passivation layer 180 is stacked on the organic semiconductor 154 and the surface treatment layer 160, and a plurality of contact holes 181, 182, and 185 are formed by a photolithography process.

1 and 2, ITO or IZO is stacked on the passivation layer 180, and then photo-etched to form the pixel electrode 191 and the contact assistants 81 and 82.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of the invention.

The manufacturing process can be simplified while improving the characteristics of the organic thin film transistor array panel.

Claims (10)

Gate electrode, A gate insulating film formed on the gate electrode, A source electrode and a drain electrode formed on the gate insulating film and facing each other; and An organic semiconductor in contact with the source electrode and the drain electrode Including; The difference in surface contact angle between the gate insulating film, the source electrode and the drain electrode is 5 ° or less. Thin film transistor display panel. In claim 1, And a surface of the gate insulating film, the source electrode, and the drain electrode are plasma treated. In claim 2, The plasma treatment is performed by supplying a fluorine-containing gas. In claim 1, And a self-assembled thin film formed on the gate insulating film, the source electrode and the drain electrode. In claim 1, The organic semiconductor is a thin film transistor array panel not partitioned by a partition. Forming a gate electrode, Forming a gate insulating film on the gate electrode; Forming a source electrode and a drain electrode on the gate insulating film, Surface-treating the gate insulating film, the source electrode and the drain electrode such that surface contact angles of the gate insulating film, the source electrode and the drain electrode are 5 ° or less; and Forming an organic semiconductor in contact with the source electrode and the drain electrode Method of manufacturing a thin film transistor array panel comprising a. In claim 6, The surface treatment of the gate insulating layer, the source electrode and the drain electrode includes supplying a fluorine-containing gas to perform plasma treatment. In claim 6, The surface treating of the gate insulating film, the source electrode and the drain electrode includes forming a self-assembled thin film on the gate insulating film, the source electrode and the drain electrode. In claim 6, The forming of the organic semiconductor may be performed by an inkjet printing method. In claim 9, And the inkjet printing method is performed without a partition wall for partitioning the organic semiconductor.

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